| T371 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.3623011442 |
|
|
Sep 01 11:13:08 PM UTC 24 |
Sep 01 11:13:36 PM UTC 24 |
228568504 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.2555311010 |
|
|
Sep 01 11:13:18 PM UTC 24 |
Sep 01 11:13:37 PM UTC 24 |
305394424 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.3438864906 |
|
|
Sep 01 11:12:53 PM UTC 24 |
Sep 01 11:13:37 PM UTC 24 |
2079864262 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.2057527788 |
|
|
Sep 01 11:13:17 PM UTC 24 |
Sep 01 11:13:38 PM UTC 24 |
350120275 ps |
| T29 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.1389013908 |
|
|
Sep 01 11:13:34 PM UTC 24 |
Sep 01 11:13:39 PM UTC 24 |
325003645 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.847496755 |
|
|
Sep 01 11:13:27 PM UTC 24 |
Sep 01 11:13:41 PM UTC 24 |
559144323 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.3292653975 |
|
|
Sep 01 11:13:17 PM UTC 24 |
Sep 01 11:13:41 PM UTC 24 |
793892690 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.2892845832 |
|
|
Sep 01 11:13:32 PM UTC 24 |
Sep 01 11:13:42 PM UTC 24 |
196146361 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.3426533446 |
|
|
Sep 01 11:13:40 PM UTC 24 |
Sep 01 11:13:42 PM UTC 24 |
60582814 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.1097673687 |
|
|
Sep 01 11:13:42 PM UTC 24 |
Sep 01 11:13:45 PM UTC 24 |
46048722 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2309239871 |
|
|
Sep 01 11:13:42 PM UTC 24 |
Sep 01 11:13:45 PM UTC 24 |
18002229 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.2356554114 |
|
|
Sep 01 11:12:56 PM UTC 24 |
Sep 01 11:13:45 PM UTC 24 |
8553139784 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.665829425 |
|
|
Sep 01 11:13:18 PM UTC 24 |
Sep 01 11:13:46 PM UTC 24 |
717582300 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.1414914771 |
|
|
Sep 01 11:13:27 PM UTC 24 |
Sep 01 11:13:46 PM UTC 24 |
1504769338 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.165321055 |
|
|
Sep 01 11:10:49 PM UTC 24 |
Sep 01 11:13:48 PM UTC 24 |
7069830879 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.2278675299 |
|
|
Sep 01 11:13:37 PM UTC 24 |
Sep 01 11:13:49 PM UTC 24 |
722137697 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.3287928448 |
|
|
Sep 01 11:13:45 PM UTC 24 |
Sep 01 11:13:49 PM UTC 24 |
102663639 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.116796389 |
|
|
Sep 01 11:13:32 PM UTC 24 |
Sep 01 11:13:50 PM UTC 24 |
367356802 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.2239758038 |
|
|
Sep 01 11:13:34 PM UTC 24 |
Sep 01 11:13:53 PM UTC 24 |
1557245540 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.768717184 |
|
|
Sep 01 11:11:36 PM UTC 24 |
Sep 01 11:13:54 PM UTC 24 |
16548097341 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.2345900358 |
|
|
Sep 01 11:13:47 PM UTC 24 |
Sep 01 11:13:56 PM UTC 24 |
604451714 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.1655521964 |
|
|
Sep 01 11:13:38 PM UTC 24 |
Sep 01 11:13:57 PM UTC 24 |
1997236962 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.3697087713 |
|
|
Sep 01 11:13:49 PM UTC 24 |
Sep 01 11:13:58 PM UTC 24 |
672579401 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.1025114785 |
|
|
Sep 01 11:13:43 PM UTC 24 |
Sep 01 11:13:58 PM UTC 24 |
579354344 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.3429957679 |
|
|
Sep 01 11:12:35 PM UTC 24 |
Sep 01 11:13:58 PM UTC 24 |
35770543470 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.3146752301 |
|
|
Sep 01 11:13:46 PM UTC 24 |
Sep 01 11:13:59 PM UTC 24 |
293355832 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.2479259088 |
|
|
Sep 01 11:13:17 PM UTC 24 |
Sep 01 11:14:01 PM UTC 24 |
6308763746 ps |
| T30 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.4113070011 |
|
|
Sep 01 11:13:51 PM UTC 24 |
Sep 01 11:14:01 PM UTC 24 |
808391504 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.1069451682 |
|
|
Sep 01 11:13:58 PM UTC 24 |
Sep 01 11:14:01 PM UTC 24 |
140920780 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3000720305 |
|
|
Sep 01 11:14:00 PM UTC 24 |
Sep 01 11:14:03 PM UTC 24 |
120092489 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.30257131 |
|
|
Sep 01 11:13:52 PM UTC 24 |
Sep 01 11:14:06 PM UTC 24 |
859965037 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.3759149875 |
|
|
Sep 01 11:14:00 PM UTC 24 |
Sep 01 11:14:07 PM UTC 24 |
128815044 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.2152934501 |
|
|
Sep 01 11:14:02 PM UTC 24 |
Sep 01 11:14:07 PM UTC 24 |
32633934 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.181637610 |
|
|
Sep 01 11:13:55 PM UTC 24 |
Sep 01 11:14:07 PM UTC 24 |
1653687879 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.3879845613 |
|
|
Sep 01 11:13:25 PM UTC 24 |
Sep 01 11:14:09 PM UTC 24 |
953808211 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.3474738141 |
|
|
Sep 01 11:13:55 PM UTC 24 |
Sep 01 11:14:10 PM UTC 24 |
4494699965 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.3302044433 |
|
|
Sep 01 11:14:04 PM UTC 24 |
Sep 01 11:14:12 PM UTC 24 |
614274750 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.3797267274 |
|
|
Sep 01 11:14:01 PM UTC 24 |
Sep 01 11:14:13 PM UTC 24 |
266052536 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.1698901278 |
|
|
Sep 01 11:14:07 PM UTC 24 |
Sep 01 11:14:14 PM UTC 24 |
236774341 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.1146252438 |
|
|
Sep 01 11:13:46 PM UTC 24 |
Sep 01 11:14:14 PM UTC 24 |
500856120 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.932982394 |
|
|
Sep 01 11:11:14 PM UTC 24 |
Sep 01 11:14:15 PM UTC 24 |
4894434888 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.35885946 |
|
|
Sep 01 11:13:32 PM UTC 24 |
Sep 01 11:14:15 PM UTC 24 |
3209875023 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.4194333706 |
|
|
Sep 01 11:14:15 PM UTC 24 |
Sep 01 11:14:17 PM UTC 24 |
65201498 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2531250044 |
|
|
Sep 01 11:14:16 PM UTC 24 |
Sep 01 11:14:19 PM UTC 24 |
126786480 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.2329327503 |
|
|
Sep 01 11:14:15 PM UTC 24 |
Sep 01 11:14:21 PM UTC 24 |
168512354 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.1898223385 |
|
|
Sep 01 11:14:08 PM UTC 24 |
Sep 01 11:14:21 PM UTC 24 |
679711582 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_errors.701334504 |
|
|
Sep 01 11:14:02 PM UTC 24 |
Sep 01 11:14:23 PM UTC 24 |
5094673909 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.375815199 |
|
|
Sep 01 11:14:08 PM UTC 24 |
Sep 01 11:14:23 PM UTC 24 |
352249818 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.3281912373 |
|
|
Sep 01 11:14:23 PM UTC 24 |
Sep 01 11:14:38 PM UTC 24 |
1108026919 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.577819802 |
|
|
Sep 01 11:14:10 PM UTC 24 |
Sep 01 11:14:23 PM UTC 24 |
732125041 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.1446801790 |
|
|
Sep 01 11:13:47 PM UTC 24 |
Sep 01 11:14:23 PM UTC 24 |
778587480 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.151938528 |
|
|
Sep 01 11:14:11 PM UTC 24 |
Sep 01 11:14:24 PM UTC 24 |
257184617 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.140792005 |
|
|
Sep 01 11:14:04 PM UTC 24 |
Sep 01 11:14:24 PM UTC 24 |
380101993 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.2709209695 |
|
|
Sep 01 11:14:19 PM UTC 24 |
Sep 01 11:14:25 PM UTC 24 |
210398867 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.1418749457 |
|
|
Sep 01 11:12:21 PM UTC 24 |
Sep 01 11:14:25 PM UTC 24 |
4407382540 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.426513662 |
|
|
Sep 01 11:13:31 PM UTC 24 |
Sep 01 11:14:26 PM UTC 24 |
1279710213 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.1538957514 |
|
|
Sep 01 11:14:07 PM UTC 24 |
Sep 01 11:14:28 PM UTC 24 |
1193738968 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.1108740721 |
|
|
Sep 01 11:14:18 PM UTC 24 |
Sep 01 11:14:29 PM UTC 24 |
60996659 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.3974668511 |
|
|
Sep 01 11:14:24 PM UTC 24 |
Sep 01 11:14:38 PM UTC 24 |
448188689 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.3041165971 |
|
|
Sep 01 11:14:25 PM UTC 24 |
Sep 01 11:14:29 PM UTC 24 |
951347266 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.2716205389 |
|
|
Sep 01 11:14:00 PM UTC 24 |
Sep 01 11:14:31 PM UTC 24 |
218845193 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.1319045000 |
|
|
Sep 01 11:13:43 PM UTC 24 |
Sep 01 11:14:32 PM UTC 24 |
339247365 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.4121590747 |
|
|
Sep 01 11:14:30 PM UTC 24 |
Sep 01 11:14:32 PM UTC 24 |
28254496 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3113155218 |
|
|
Sep 01 11:14:32 PM UTC 24 |
Sep 01 11:14:34 PM UTC 24 |
40381243 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.2865029437 |
|
|
Sep 01 11:13:50 PM UTC 24 |
Sep 01 11:14:34 PM UTC 24 |
2375165483 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.1377976177 |
|
|
Sep 01 11:14:30 PM UTC 24 |
Sep 01 11:14:35 PM UTC 24 |
76244322 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.639020826 |
|
|
Sep 01 11:14:24 PM UTC 24 |
Sep 01 11:14:36 PM UTC 24 |
10451841097 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.447552747 |
|
|
Sep 01 11:14:34 PM UTC 24 |
Sep 01 11:14:39 PM UTC 24 |
192386177 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.3083145182 |
|
|
Sep 01 11:14:33 PM UTC 24 |
Sep 01 11:14:42 PM UTC 24 |
86443848 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.3818365629 |
|
|
Sep 01 11:14:26 PM UTC 24 |
Sep 01 11:14:43 PM UTC 24 |
303204841 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.4039914654 |
|
|
Sep 01 11:14:39 PM UTC 24 |
Sep 01 11:14:45 PM UTC 24 |
92715801 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.3031705242 |
|
|
Sep 01 11:14:36 PM UTC 24 |
Sep 01 11:14:45 PM UTC 24 |
218378233 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.4274925255 |
|
|
Sep 01 11:14:22 PM UTC 24 |
Sep 01 11:14:46 PM UTC 24 |
809702349 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.1515920574 |
|
|
Sep 01 11:14:35 PM UTC 24 |
Sep 01 11:14:47 PM UTC 24 |
2498482809 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.43100233 |
|
|
Sep 01 11:13:47 PM UTC 24 |
Sep 01 11:14:47 PM UTC 24 |
5932460741 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.468842960 |
|
|
Sep 01 11:14:13 PM UTC 24 |
Sep 01 11:14:47 PM UTC 24 |
3270118446 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.4036827069 |
|
|
Sep 01 11:14:26 PM UTC 24 |
Sep 01 11:14:48 PM UTC 24 |
517210890 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.1463860634 |
|
|
Sep 01 11:14:39 PM UTC 24 |
Sep 01 11:14:48 PM UTC 24 |
325678236 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.942167894 |
|
|
Sep 01 11:14:36 PM UTC 24 |
Sep 01 11:14:49 PM UTC 24 |
341820511 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.2360481784 |
|
|
Sep 01 11:13:18 PM UTC 24 |
Sep 01 11:14:50 PM UTC 24 |
12129114854 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3142189020 |
|
|
Sep 01 11:14:48 PM UTC 24 |
Sep 01 11:14:50 PM UTC 24 |
13360582 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.4246759470 |
|
|
Sep 01 11:14:48 PM UTC 24 |
Sep 01 11:14:51 PM UTC 24 |
60713883 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.128289061 |
|
|
Sep 01 11:14:37 PM UTC 24 |
Sep 01 11:14:51 PM UTC 24 |
2688158314 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.650383616 |
|
|
Sep 01 11:14:27 PM UTC 24 |
Sep 01 11:14:51 PM UTC 24 |
2324733838 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.2069719279 |
|
|
Sep 01 11:13:17 PM UTC 24 |
Sep 01 11:14:51 PM UTC 24 |
1892320180 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.1466184287 |
|
|
Sep 01 11:14:50 PM UTC 24 |
Sep 01 11:14:53 PM UTC 24 |
84073087 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.223002057 |
|
|
Sep 01 11:14:44 PM UTC 24 |
Sep 01 11:14:54 PM UTC 24 |
328590992 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.1814791284 |
|
|
Sep 01 11:14:42 PM UTC 24 |
Sep 01 11:14:55 PM UTC 24 |
178871188 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.596974605 |
|
|
Sep 01 11:14:24 PM UTC 24 |
Sep 01 11:14:55 PM UTC 24 |
2539985818 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.2906800709 |
|
|
Sep 01 11:14:48 PM UTC 24 |
Sep 01 11:14:57 PM UTC 24 |
347108040 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.4164458140 |
|
|
Sep 01 11:14:52 PM UTC 24 |
Sep 01 11:14:57 PM UTC 24 |
116469933 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.2964375932 |
|
|
Sep 01 11:14:46 PM UTC 24 |
Sep 01 11:14:58 PM UTC 24 |
496238063 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.555174469 |
|
|
Sep 01 11:14:49 PM UTC 24 |
Sep 01 11:15:00 PM UTC 24 |
86623692 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.2661343582 |
|
|
Sep 01 11:14:56 PM UTC 24 |
Sep 01 11:15:03 PM UTC 24 |
593357278 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.2067834644 |
|
|
Sep 01 11:15:01 PM UTC 24 |
Sep 01 11:15:04 PM UTC 24 |
27884208 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.805637845 |
|
|
Sep 01 11:14:52 PM UTC 24 |
Sep 01 11:15:04 PM UTC 24 |
1039765790 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.49683926 |
|
|
Sep 01 11:14:51 PM UTC 24 |
Sep 01 11:15:05 PM UTC 24 |
350879260 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.826497093 |
|
|
Sep 01 11:14:16 PM UTC 24 |
Sep 01 11:15:05 PM UTC 24 |
698553171 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3796041323 |
|
|
Sep 01 11:15:04 PM UTC 24 |
Sep 01 11:15:06 PM UTC 24 |
11013846 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.4147029004 |
|
|
Sep 01 11:15:03 PM UTC 24 |
Sep 01 11:15:07 PM UTC 24 |
570709918 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.2902109166 |
|
|
Sep 01 11:14:05 PM UTC 24 |
Sep 01 11:15:09 PM UTC 24 |
4768735046 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.3834479478 |
|
|
Sep 01 11:14:08 PM UTC 24 |
Sep 01 11:15:09 PM UTC 24 |
2785345741 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.352720419 |
|
|
Sep 01 11:14:57 PM UTC 24 |
Sep 01 11:15:12 PM UTC 24 |
2939974237 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.409994438 |
|
|
Sep 01 11:14:33 PM UTC 24 |
Sep 01 11:15:12 PM UTC 24 |
272552131 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.3915351845 |
|
|
Sep 01 11:14:51 PM UTC 24 |
Sep 01 11:15:13 PM UTC 24 |
1168279173 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.4268105117 |
|
|
Sep 01 11:15:07 PM UTC 24 |
Sep 01 11:15:13 PM UTC 24 |
315942485 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.1056844040 |
|
|
Sep 01 11:15:07 PM UTC 24 |
Sep 01 11:15:14 PM UTC 24 |
184902000 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2191326723 |
|
|
Sep 01 11:13:20 PM UTC 24 |
Sep 01 11:15:14 PM UTC 24 |
5556635531 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.4076762623 |
|
|
Sep 01 11:14:56 PM UTC 24 |
Sep 01 11:15:15 PM UTC 24 |
1202153786 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.1723606391 |
|
|
Sep 01 11:14:58 PM UTC 24 |
Sep 01 11:15:17 PM UTC 24 |
1291810356 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.3352351151 |
|
|
Sep 01 11:15:08 PM UTC 24 |
Sep 01 11:15:17 PM UTC 24 |
1574587190 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.3347270654 |
|
|
Sep 01 11:15:14 PM UTC 24 |
Sep 01 11:15:17 PM UTC 24 |
167240468 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.2736334273 |
|
|
Sep 01 11:14:52 PM UTC 24 |
Sep 01 11:15:18 PM UTC 24 |
1655348825 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.2230625007 |
|
|
Sep 01 11:15:10 PM UTC 24 |
Sep 01 11:15:20 PM UTC 24 |
1740557589 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.2470249471 |
|
|
Sep 01 11:15:19 PM UTC 24 |
Sep 01 11:15:21 PM UTC 24 |
17338503 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2574242811 |
|
|
Sep 01 11:15:19 PM UTC 24 |
Sep 01 11:15:21 PM UTC 24 |
12859359 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.1406382077 |
|
|
Sep 01 11:14:49 PM UTC 24 |
Sep 01 11:15:24 PM UTC 24 |
1671536816 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.3652410546 |
|
|
Sep 01 11:15:19 PM UTC 24 |
Sep 01 11:15:24 PM UTC 24 |
75314373 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.1177712587 |
|
|
Sep 01 11:15:05 PM UTC 24 |
Sep 01 11:15:47 PM UTC 24 |
206231949 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3119109872 |
|
|
Sep 01 11:15:08 PM UTC 24 |
Sep 01 11:15:25 PM UTC 24 |
526089663 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.248798003 |
|
|
Sep 01 11:14:25 PM UTC 24 |
Sep 01 11:15:26 PM UTC 24 |
35258329236 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.4208902908 |
|
|
Sep 01 11:15:22 PM UTC 24 |
Sep 01 11:15:27 PM UTC 24 |
221211584 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.580000978 |
|
|
Sep 01 11:15:14 PM UTC 24 |
Sep 01 11:15:28 PM UTC 24 |
361718412 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.2050384978 |
|
|
Sep 01 11:14:24 PM UTC 24 |
Sep 01 11:15:28 PM UTC 24 |
5503615845 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.3956433357 |
|
|
Sep 01 11:15:08 PM UTC 24 |
Sep 01 11:15:29 PM UTC 24 |
1597022935 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.1259315587 |
|
|
Sep 01 11:15:15 PM UTC 24 |
Sep 01 11:15:29 PM UTC 24 |
1016771927 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.487339419 |
|
|
Sep 01 11:15:26 PM UTC 24 |
Sep 01 11:15:29 PM UTC 24 |
86026467 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.3709164264 |
|
|
Sep 01 11:14:54 PM UTC 24 |
Sep 01 11:15:29 PM UTC 24 |
1596765120 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.3384945345 |
|
|
Sep 01 11:15:21 PM UTC 24 |
Sep 01 11:15:34 PM UTC 24 |
105942217 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.3590608400 |
|
|
Sep 01 11:15:14 PM UTC 24 |
Sep 01 11:15:34 PM UTC 24 |
7222957992 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.140847835 |
|
|
Sep 01 11:15:28 PM UTC 24 |
Sep 01 11:15:35 PM UTC 24 |
476227191 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.1324996512 |
|
|
Sep 01 11:15:24 PM UTC 24 |
Sep 01 11:15:37 PM UTC 24 |
228007204 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.3493560216 |
|
|
Sep 01 11:15:35 PM UTC 24 |
Sep 01 11:15:38 PM UTC 24 |
19080536 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.405109950 |
|
|
Sep 01 11:15:36 PM UTC 24 |
Sep 01 11:15:39 PM UTC 24 |
13450146 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.3770113039 |
|
|
Sep 01 11:15:35 PM UTC 24 |
Sep 01 11:15:40 PM UTC 24 |
197352921 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.1040665458 |
|
|
Sep 01 11:15:22 PM UTC 24 |
Sep 01 11:15:40 PM UTC 24 |
256232409 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.4111712970 |
|
|
Sep 01 11:12:22 PM UTC 24 |
Sep 01 11:15:40 PM UTC 24 |
4269363421 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.1791170475 |
|
|
Sep 01 11:15:29 PM UTC 24 |
Sep 01 11:15:41 PM UTC 24 |
2148344245 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.575505878 |
|
|
Sep 01 11:14:52 PM UTC 24 |
Sep 01 11:15:41 PM UTC 24 |
5071176981 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.2738989761 |
|
|
Sep 01 11:15:29 PM UTC 24 |
Sep 01 11:15:42 PM UTC 24 |
510711965 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.3570486491 |
|
|
Sep 01 11:15:39 PM UTC 24 |
Sep 01 11:15:43 PM UTC 24 |
65054947 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.3715572254 |
|
|
Sep 01 11:15:26 PM UTC 24 |
Sep 01 11:15:46 PM UTC 24 |
2034509057 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.1438688739 |
|
|
Sep 01 11:15:29 PM UTC 24 |
Sep 01 11:15:49 PM UTC 24 |
784602717 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.1114035064 |
|
|
Sep 01 11:15:31 PM UTC 24 |
Sep 01 11:15:47 PM UTC 24 |
380005845 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.395123554 |
|
|
Sep 01 11:11:58 PM UTC 24 |
Sep 01 11:15:47 PM UTC 24 |
31145518551 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.629596600 |
|
|
Sep 01 11:14:39 PM UTC 24 |
Sep 01 11:15:47 PM UTC 24 |
3685295465 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1995383438 |
|
|
Sep 01 11:15:48 PM UTC 24 |
Sep 01 11:15:51 PM UTC 24 |
32610352 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.1152241889 |
|
|
Sep 01 11:13:39 PM UTC 24 |
Sep 01 11:15:49 PM UTC 24 |
9430153929 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.1847054766 |
|
|
Sep 01 11:15:42 PM UTC 24 |
Sep 01 11:15:51 PM UTC 24 |
1687841913 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.4007160498 |
|
|
Sep 01 11:15:48 PM UTC 24 |
Sep 01 11:15:51 PM UTC 24 |
294968158 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.2211940319 |
|
|
Sep 01 11:15:41 PM UTC 24 |
Sep 01 11:15:53 PM UTC 24 |
3205734515 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.1920606905 |
|
|
Sep 01 11:15:50 PM UTC 24 |
Sep 01 11:15:53 PM UTC 24 |
68797706 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.2495070955 |
|
|
Sep 01 11:15:39 PM UTC 24 |
Sep 01 11:15:53 PM UTC 24 |
128275085 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.1392840683 |
|
|
Sep 01 11:15:20 PM UTC 24 |
Sep 01 11:15:54 PM UTC 24 |
327369090 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.3386909354 |
|
|
Sep 01 11:15:49 PM UTC 24 |
Sep 01 11:15:54 PM UTC 24 |
582434231 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.727545199 |
|
|
Sep 01 11:14:37 PM UTC 24 |
Sep 01 11:15:55 PM UTC 24 |
1730207999 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.3146682556 |
|
|
Sep 01 11:15:48 PM UTC 24 |
Sep 01 11:15:56 PM UTC 24 |
214228019 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.2821063126 |
|
|
Sep 01 11:15:10 PM UTC 24 |
Sep 01 11:15:57 PM UTC 24 |
899169386 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.1736421842 |
|
|
Sep 01 11:15:42 PM UTC 24 |
Sep 01 11:15:57 PM UTC 24 |
219812455 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.2819479684 |
|
|
Sep 01 11:15:43 PM UTC 24 |
Sep 01 11:15:57 PM UTC 24 |
824370007 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.227938114 |
|
|
Sep 01 11:15:55 PM UTC 24 |
Sep 01 11:15:57 PM UTC 24 |
22664702 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.2002039422 |
|
|
Sep 01 11:15:41 PM UTC 24 |
Sep 01 11:15:58 PM UTC 24 |
451753572 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2836894965 |
|
|
Sep 01 11:15:57 PM UTC 24 |
Sep 01 11:16:00 PM UTC 24 |
42556350 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.3362505857 |
|
|
Sep 01 11:15:56 PM UTC 24 |
Sep 01 11:16:01 PM UTC 24 |
326321258 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.3567378927 |
|
|
Sep 01 11:15:51 PM UTC 24 |
Sep 01 11:16:01 PM UTC 24 |
968173643 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.50691109 |
|
|
Sep 01 11:15:58 PM UTC 24 |
Sep 01 11:16:01 PM UTC 24 |
27039806 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.2510851562 |
|
|
Sep 01 11:15:42 PM UTC 24 |
Sep 01 11:16:02 PM UTC 24 |
1489276240 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.554417770 |
|
|
Sep 01 11:15:51 PM UTC 24 |
Sep 01 11:16:06 PM UTC 24 |
618956716 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.3985295332 |
|
|
Sep 01 11:15:52 PM UTC 24 |
Sep 01 11:16:07 PM UTC 24 |
1726167331 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.1054551226 |
|
|
Sep 01 11:16:01 PM UTC 24 |
Sep 01 11:16:08 PM UTC 24 |
133897467 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.2491404950 |
|
|
Sep 01 11:15:53 PM UTC 24 |
Sep 01 11:16:10 PM UTC 24 |
1306602103 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.503795343 |
|
|
Sep 01 11:16:08 PM UTC 24 |
Sep 01 11:16:10 PM UTC 24 |
43450867 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.440992252 |
|
|
Sep 01 11:16:09 PM UTC 24 |
Sep 01 11:16:11 PM UTC 24 |
14926548 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.1624420402 |
|
|
Sep 01 11:15:57 PM UTC 24 |
Sep 01 11:16:12 PM UTC 24 |
220603992 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.3240652568 |
|
|
Sep 01 11:16:00 PM UTC 24 |
Sep 01 11:16:12 PM UTC 24 |
347357238 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.2074238335 |
|
|
Sep 01 11:15:38 PM UTC 24 |
Sep 01 11:16:12 PM UTC 24 |
217808516 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1207318589 |
|
|
Sep 01 11:16:11 PM UTC 24 |
Sep 01 11:16:14 PM UTC 24 |
15089385 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.2193090740 |
|
|
Sep 01 11:15:59 PM UTC 24 |
Sep 01 11:16:14 PM UTC 24 |
333744560 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.2584201984 |
|
|
Sep 01 11:15:55 PM UTC 24 |
Sep 01 11:16:16 PM UTC 24 |
721074803 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.2184190240 |
|
|
Sep 01 11:16:02 PM UTC 24 |
Sep 01 11:16:18 PM UTC 24 |
261329977 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.3515788306 |
|
|
Sep 01 11:15:49 PM UTC 24 |
Sep 01 11:16:18 PM UTC 24 |
1101648365 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.1310417121 |
|
|
Sep 01 11:16:15 PM UTC 24 |
Sep 01 11:16:18 PM UTC 24 |
290283850 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.4119974077 |
|
|
Sep 01 11:16:02 PM UTC 24 |
Sep 01 11:16:19 PM UTC 24 |
671798580 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.2973856504 |
|
|
Sep 01 11:15:08 PM UTC 24 |
Sep 01 11:16:19 PM UTC 24 |
5139283897 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.3310352622 |
|
|
Sep 01 11:16:13 PM UTC 24 |
Sep 01 11:16:20 PM UTC 24 |
369139384 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.1989439835 |
|
|
Sep 01 11:15:52 PM UTC 24 |
Sep 01 11:16:21 PM UTC 24 |
1129626855 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.3243050316 |
|
|
Sep 01 11:16:02 PM UTC 24 |
Sep 01 11:16:21 PM UTC 24 |
263973662 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.3795082621 |
|
|
Sep 01 11:16:19 PM UTC 24 |
Sep 01 11:16:22 PM UTC 24 |
23775018 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.3179304452 |
|
|
Sep 01 11:16:13 PM UTC 24 |
Sep 01 11:16:22 PM UTC 24 |
1003552679 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.925993651 |
|
|
Sep 01 11:16:21 PM UTC 24 |
Sep 01 11:16:23 PM UTC 24 |
129725169 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.2198448493 |
|
|
Sep 01 11:15:28 PM UTC 24 |
Sep 01 11:16:24 PM UTC 24 |
1711301647 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.3255309242 |
|
|
Sep 01 11:16:21 PM UTC 24 |
Sep 01 11:16:26 PM UTC 24 |
53695818 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.3099954067 |
|
|
Sep 01 11:16:22 PM UTC 24 |
Sep 01 11:16:26 PM UTC 24 |
94568843 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1158104309 |
|
|
Sep 01 11:15:17 PM UTC 24 |
Sep 01 11:16:27 PM UTC 24 |
39193212018 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.2777170683 |
|
|
Sep 01 11:16:12 PM UTC 24 |
Sep 01 11:16:27 PM UTC 24 |
127286058 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.3084651899 |
|
|
Sep 01 11:16:13 PM UTC 24 |
Sep 01 11:16:28 PM UTC 24 |
756691471 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.1730459809 |
|
|
Sep 01 11:16:23 PM UTC 24 |
Sep 01 11:16:29 PM UTC 24 |
400754145 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.3664643872 |
|
|
Sep 01 11:16:28 PM UTC 24 |
Sep 01 11:16:31 PM UTC 24 |
16734922 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1191155432 |
|
|
Sep 01 11:16:30 PM UTC 24 |
Sep 01 11:16:32 PM UTC 24 |
12985405 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.3894464276 |
|
|
Sep 01 11:16:35 PM UTC 24 |
Sep 01 11:16:51 PM UTC 24 |
316968320 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.2724990559 |
|
|
Sep 01 11:16:17 PM UTC 24 |
Sep 01 11:16:33 PM UTC 24 |
615925003 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.2690313526 |
|
|
Sep 01 11:16:28 PM UTC 24 |
Sep 01 11:16:33 PM UTC 24 |
122028337 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.1722223193 |
|
|
Sep 01 11:15:57 PM UTC 24 |
Sep 01 11:16:34 PM UTC 24 |
1293740585 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.1710533358 |
|
|
Sep 01 11:16:19 PM UTC 24 |
Sep 01 11:16:34 PM UTC 24 |
970685416 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3483909825 |
|
|
Sep 01 11:16:48 PM UTC 24 |
Sep 01 11:16:51 PM UTC 24 |
11440424 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.951294549 |
|
|
Sep 01 11:16:15 PM UTC 24 |
Sep 01 11:16:35 PM UTC 24 |
658566935 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.2373291272 |
|
|
Sep 01 11:16:26 PM UTC 24 |
Sep 01 11:16:36 PM UTC 24 |
163274297 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.112881570 |
|
|
Sep 01 11:16:23 PM UTC 24 |
Sep 01 11:16:36 PM UTC 24 |
5189054855 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.4211984209 |
|
|
Sep 01 11:16:23 PM UTC 24 |
Sep 01 11:16:38 PM UTC 24 |
1420557180 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.2468013400 |
|
|
Sep 01 11:16:22 PM UTC 24 |
Sep 01 11:16:38 PM UTC 24 |
60050307 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.305176018 |
|
|
Sep 01 11:16:32 PM UTC 24 |
Sep 01 11:16:39 PM UTC 24 |
372341669 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.3525617787 |
|
|
Sep 01 11:16:37 PM UTC 24 |
Sep 01 11:16:40 PM UTC 24 |
24817130 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.644459740 |
|
|
Sep 01 11:16:38 PM UTC 24 |
Sep 01 11:16:41 PM UTC 24 |
12583893 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.3270748593 |
|
|
Sep 01 11:16:37 PM UTC 24 |
Sep 01 11:16:41 PM UTC 24 |
76284855 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.655682502 |
|
|
Sep 01 11:16:31 PM UTC 24 |
Sep 01 11:16:41 PM UTC 24 |
73164675 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.1835741953 |
|
|
Sep 01 11:13:39 PM UTC 24 |
Sep 01 11:16:44 PM UTC 24 |
4269738934 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.763330251 |
|
|
Sep 01 11:16:25 PM UTC 24 |
Sep 01 11:16:44 PM UTC 24 |
296733430 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.4279574684 |
|
|
Sep 01 11:16:41 PM UTC 24 |
Sep 01 11:16:45 PM UTC 24 |
86902616 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.3934516628 |
|
|
Sep 01 11:16:35 PM UTC 24 |
Sep 01 11:16:45 PM UTC 24 |
1588853515 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.1358747384 |
|
|
Sep 01 11:16:21 PM UTC 24 |
Sep 01 11:16:45 PM UTC 24 |
1455438180 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.3286322560 |
|
|
Sep 01 11:16:41 PM UTC 24 |
Sep 01 11:16:47 PM UTC 24 |
224750105 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.1767260008 |
|
|
Sep 01 11:15:26 PM UTC 24 |
Sep 01 11:16:47 PM UTC 24 |
10962884321 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.1884117816 |
|
|
Sep 01 11:16:42 PM UTC 24 |
Sep 01 11:16:47 PM UTC 24 |
172632264 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.2512805914 |
|
|
Sep 01 11:16:33 PM UTC 24 |
Sep 01 11:16:49 PM UTC 24 |
426034196 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.3980515150 |
|
|
Sep 01 11:16:33 PM UTC 24 |
Sep 01 11:16:49 PM UTC 24 |
871031363 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.2334712419 |
|
|
Sep 01 11:16:11 PM UTC 24 |
Sep 01 11:16:50 PM UTC 24 |
1058321139 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.1498409844 |
|
|
Sep 01 11:16:48 PM UTC 24 |
Sep 01 11:16:51 PM UTC 24 |
39114735 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.1650165840 |
|
|
Sep 01 11:16:27 PM UTC 24 |
Sep 01 11:16:52 PM UTC 24 |
2641099450 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.1035078361 |
|
|
Sep 01 11:16:33 PM UTC 24 |
Sep 01 11:16:52 PM UTC 24 |
255547352 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.4011724086 |
|
|
Sep 01 11:16:42 PM UTC 24 |
Sep 01 11:16:53 PM UTC 24 |
1023352359 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.1805744977 |
|
|
Sep 01 11:16:36 PM UTC 24 |
Sep 01 11:16:53 PM UTC 24 |
364806603 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.1787236602 |
|
|
Sep 01 11:16:48 PM UTC 24 |
Sep 01 11:16:53 PM UTC 24 |
256034339 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.1882368186 |
|
|
Sep 01 11:16:31 PM UTC 24 |
Sep 01 11:16:56 PM UTC 24 |
763765084 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.2403290847 |
|
|
Sep 01 11:16:46 PM UTC 24 |
Sep 01 11:16:56 PM UTC 24 |
260360364 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.602494876 |
|
|
Sep 01 11:16:45 PM UTC 24 |
Sep 01 11:16:56 PM UTC 24 |
197430666 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.4249420923 |
|
|
Sep 01 11:16:51 PM UTC 24 |
Sep 01 11:16:57 PM UTC 24 |
665432345 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.2717832871 |
|
|
Sep 01 11:10:17 PM UTC 24 |
Sep 01 11:16:57 PM UTC 24 |
38783602805 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.1818619832 |
|
|
Sep 01 11:16:42 PM UTC 24 |
Sep 01 11:16:57 PM UTC 24 |
616236544 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1861637274 |
|
|
Sep 01 11:16:57 PM UTC 24 |
Sep 01 11:17:00 PM UTC 24 |
45345640 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.2727844333 |
|
|
Sep 01 11:16:57 PM UTC 24 |
Sep 01 11:17:00 PM UTC 24 |
71099069 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.321591678 |
|
|
Sep 01 11:16:45 PM UTC 24 |
Sep 01 11:17:01 PM UTC 24 |
3117334074 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.1027033889 |
|
|
Sep 01 11:16:52 PM UTC 24 |
Sep 01 11:17:01 PM UTC 24 |
1760041685 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.2255140054 |
|
|
Sep 01 11:16:57 PM UTC 24 |
Sep 01 11:17:03 PM UTC 24 |
111802197 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.3061802609 |
|
|
Sep 01 11:16:59 PM UTC 24 |
Sep 01 11:17:04 PM UTC 24 |
131343661 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.3513801878 |
|
|
Sep 01 11:16:54 PM UTC 24 |
Sep 01 11:17:06 PM UTC 24 |
1172481423 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.2799687888 |
|
|
Sep 01 11:16:54 PM UTC 24 |
Sep 01 11:17:08 PM UTC 24 |
182992944 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_errors.1618671275 |
|
|
Sep 01 11:16:52 PM UTC 24 |
Sep 01 11:17:08 PM UTC 24 |
196107286 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.95356720 |
|
|
Sep 01 11:16:54 PM UTC 24 |
Sep 01 11:17:11 PM UTC 24 |
1761751159 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.596767820 |
|
|
Sep 01 11:17:09 PM UTC 24 |
Sep 01 11:17:11 PM UTC 24 |
27726369 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.2525891746 |
|
|
Sep 01 11:16:51 PM UTC 24 |
Sep 01 11:17:11 PM UTC 24 |
66611411 ps |