| T578 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.1321172668 |
|
|
Sep 01 11:16:59 PM UTC 24 |
Sep 01 11:17:12 PM UTC 24 |
172188110 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.3304492915 |
|
|
Sep 01 11:16:52 PM UTC 24 |
Sep 01 11:17:12 PM UTC 24 |
810217454 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.720333408 |
|
|
Sep 01 11:17:02 PM UTC 24 |
Sep 01 11:17:13 PM UTC 24 |
1693882835 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.3254311209 |
|
|
Sep 01 11:17:01 PM UTC 24 |
Sep 01 11:17:13 PM UTC 24 |
3408792832 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.940604307 |
|
|
Sep 01 11:17:12 PM UTC 24 |
Sep 01 11:17:15 PM UTC 24 |
18149302 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.3490633888 |
|
|
Sep 01 11:17:02 PM UTC 24 |
Sep 01 11:17:16 PM UTC 24 |
210247025 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.713650515 |
|
|
Sep 01 11:15:13 PM UTC 24 |
Sep 01 11:17:17 PM UTC 24 |
80909450996 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.4185634033 |
|
|
Sep 01 11:17:13 PM UTC 24 |
Sep 01 11:17:17 PM UTC 24 |
21481684 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.8421736 |
|
|
Sep 01 11:17:12 PM UTC 24 |
Sep 01 11:17:18 PM UTC 24 |
55744967 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.4116561155 |
|
|
Sep 01 11:17:01 PM UTC 24 |
Sep 01 11:17:18 PM UTC 24 |
1176928202 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.314364218 |
|
|
Sep 01 11:17:16 PM UTC 24 |
Sep 01 11:17:20 PM UTC 24 |
142568811 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.3627601234 |
|
|
Sep 01 11:17:20 PM UTC 24 |
Sep 01 11:17:23 PM UTC 24 |
38335232 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.3366141648 |
|
|
Sep 01 11:17:04 PM UTC 24 |
Sep 01 11:17:23 PM UTC 24 |
905048433 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.3957544477 |
|
|
Sep 01 11:17:05 PM UTC 24 |
Sep 01 11:17:24 PM UTC 24 |
349458973 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.2542207114 |
|
|
Sep 01 11:16:50 PM UTC 24 |
Sep 01 11:17:25 PM UTC 24 |
422468952 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.2395219991 |
|
|
Sep 01 11:17:13 PM UTC 24 |
Sep 01 11:17:25 PM UTC 24 |
899027897 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.1104694805 |
|
|
Sep 01 11:17:14 PM UTC 24 |
Sep 01 11:17:25 PM UTC 24 |
1188847547 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.1505995460 |
|
|
Sep 01 11:16:40 PM UTC 24 |
Sep 01 11:17:26 PM UTC 24 |
1007546880 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2427708944 |
|
|
Sep 01 11:17:24 PM UTC 24 |
Sep 01 11:17:26 PM UTC 24 |
10936973 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.68445358 |
|
|
Sep 01 11:17:21 PM UTC 24 |
Sep 01 11:17:26 PM UTC 24 |
34716777 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_errors.3997843602 |
|
|
Sep 01 11:17:46 PM UTC 24 |
Sep 01 11:17:57 PM UTC 24 |
495974475 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.2854547371 |
|
|
Sep 01 11:17:18 PM UTC 24 |
Sep 01 11:17:29 PM UTC 24 |
295481586 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.1366509921 |
|
|
Sep 01 11:17:26 PM UTC 24 |
Sep 01 11:17:30 PM UTC 24 |
76197128 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.354102098 |
|
|
Sep 01 11:17:17 PM UTC 24 |
Sep 01 11:17:31 PM UTC 24 |
225140497 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2790563139 |
|
|
Sep 01 11:17:53 PM UTC 24 |
Sep 01 11:17:55 PM UTC 24 |
23402406 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.3448915985 |
|
|
Sep 01 11:16:57 PM UTC 24 |
Sep 01 11:17:31 PM UTC 24 |
465202233 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.3019747193 |
|
|
Sep 01 11:17:15 PM UTC 24 |
Sep 01 11:17:31 PM UTC 24 |
1607595497 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3889174008 |
|
|
Sep 01 11:17:30 PM UTC 24 |
Sep 01 11:17:33 PM UTC 24 |
13486168 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.4293261364 |
|
|
Sep 01 11:17:30 PM UTC 24 |
Sep 01 11:17:33 PM UTC 24 |
17967890 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.2037742894 |
|
|
Sep 01 11:17:30 PM UTC 24 |
Sep 01 11:17:34 PM UTC 24 |
89477712 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.3259967049 |
|
|
Sep 01 11:17:18 PM UTC 24 |
Sep 01 11:17:34 PM UTC 24 |
971245194 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.3479391343 |
|
|
Sep 01 11:17:25 PM UTC 24 |
Sep 01 11:17:35 PM UTC 24 |
64807106 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.1853868323 |
|
|
Sep 01 11:16:03 PM UTC 24 |
Sep 01 11:17:35 PM UTC 24 |
2794780699 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.2791374054 |
|
|
Sep 01 11:17:32 PM UTC 24 |
Sep 01 11:17:37 PM UTC 24 |
873510890 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.2047986515 |
|
|
Sep 01 11:17:26 PM UTC 24 |
Sep 01 11:17:40 PM UTC 24 |
341016113 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.3567367165 |
|
|
Sep 01 11:17:28 PM UTC 24 |
Sep 01 11:17:41 PM UTC 24 |
1365630008 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3968217933 |
|
|
Sep 01 11:16:36 PM UTC 24 |
Sep 01 11:17:41 PM UTC 24 |
4489016293 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3054050010 |
|
|
Sep 01 11:16:28 PM UTC 24 |
Sep 01 11:17:43 PM UTC 24 |
7095822814 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.3492611986 |
|
|
Sep 01 11:17:28 PM UTC 24 |
Sep 01 11:17:44 PM UTC 24 |
1473272798 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.371107964 |
|
|
Sep 01 11:17:35 PM UTC 24 |
Sep 01 11:17:44 PM UTC 24 |
585445924 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.391069654 |
|
|
Sep 01 11:17:32 PM UTC 24 |
Sep 01 11:17:45 PM UTC 24 |
210417940 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.2155427979 |
|
|
Sep 01 11:17:42 PM UTC 24 |
Sep 01 11:17:45 PM UTC 24 |
25236154 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.2950417510 |
|
|
Sep 01 11:17:28 PM UTC 24 |
Sep 01 11:17:45 PM UTC 24 |
322100712 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.3187798000 |
|
|
Sep 01 11:17:47 PM UTC 24 |
Sep 01 11:17:56 PM UTC 24 |
234687909 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.3559977016 |
|
|
Sep 01 11:17:42 PM UTC 24 |
Sep 01 11:17:47 PM UTC 24 |
105771642 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3716320144 |
|
|
Sep 01 11:17:45 PM UTC 24 |
Sep 01 11:17:47 PM UTC 24 |
13497095 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_errors.1644330916 |
|
|
Sep 01 11:17:26 PM UTC 24 |
Sep 01 11:17:48 PM UTC 24 |
4423426654 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.933936724 |
|
|
Sep 01 11:17:35 PM UTC 24 |
Sep 01 11:17:49 PM UTC 24 |
604190079 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.1858807983 |
|
|
Sep 01 11:13:02 PM UTC 24 |
Sep 01 11:17:50 PM UTC 24 |
9501930157 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.2857427066 |
|
|
Sep 01 11:17:35 PM UTC 24 |
Sep 01 11:17:51 PM UTC 24 |
545076255 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.1764137034 |
|
|
Sep 01 11:17:34 PM UTC 24 |
Sep 01 11:17:51 PM UTC 24 |
1449740789 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.2885729060 |
|
|
Sep 01 11:17:46 PM UTC 24 |
Sep 01 11:17:51 PM UTC 24 |
217079813 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.2212845424 |
|
|
Sep 01 11:17:27 PM UTC 24 |
Sep 01 11:17:57 PM UTC 24 |
4602944846 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.4054681307 |
|
|
Sep 01 11:17:45 PM UTC 24 |
Sep 01 11:17:52 PM UTC 24 |
329228776 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.3139500307 |
|
|
Sep 01 11:17:34 PM UTC 24 |
Sep 01 11:17:53 PM UTC 24 |
385047356 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.2965474658 |
|
|
Sep 01 11:17:53 PM UTC 24 |
Sep 01 11:17:56 PM UTC 24 |
44841125 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.2671743818 |
|
|
Sep 01 11:17:37 PM UTC 24 |
Sep 01 11:17:54 PM UTC 24 |
480861365 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.3619893385 |
|
|
Sep 01 11:17:53 PM UTC 24 |
Sep 01 11:17:58 PM UTC 24 |
207228685 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.3092664505 |
|
|
Sep 01 11:17:46 PM UTC 24 |
Sep 01 11:17:59 PM UTC 24 |
1016685756 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.2758547553 |
|
|
Sep 01 11:17:56 PM UTC 24 |
Sep 01 11:18:00 PM UTC 24 |
68020348 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.2571201247 |
|
|
Sep 01 11:17:55 PM UTC 24 |
Sep 01 11:18:00 PM UTC 24 |
47548958 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.2354489498 |
|
|
Sep 01 11:17:54 PM UTC 24 |
Sep 01 11:18:00 PM UTC 24 |
135387308 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.1394743706 |
|
|
Sep 01 11:17:12 PM UTC 24 |
Sep 01 11:18:00 PM UTC 24 |
1030141460 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.2100551695 |
|
|
Sep 01 11:17:32 PM UTC 24 |
Sep 01 11:18:01 PM UTC 24 |
930337304 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1513833238 |
|
|
Sep 01 11:16:08 PM UTC 24 |
Sep 01 11:18:02 PM UTC 24 |
16240862625 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1499914547 |
|
|
Sep 01 11:18:01 PM UTC 24 |
Sep 01 11:18:04 PM UTC 24 |
12339517 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.2198435850 |
|
|
Sep 01 11:18:01 PM UTC 24 |
Sep 01 11:18:04 PM UTC 24 |
15839572 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.2231653352 |
|
|
Sep 01 11:17:47 PM UTC 24 |
Sep 01 11:18:05 PM UTC 24 |
371100811 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.12651185 |
|
|
Sep 01 11:15:55 PM UTC 24 |
Sep 01 11:18:06 PM UTC 24 |
9944039882 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.1958743342 |
|
|
Sep 01 11:18:01 PM UTC 24 |
Sep 01 11:18:06 PM UTC 24 |
64679686 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.791039530 |
|
|
Sep 01 11:17:25 PM UTC 24 |
Sep 01 11:18:06 PM UTC 24 |
207246130 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.646775530 |
|
|
Sep 01 11:17:49 PM UTC 24 |
Sep 01 11:18:07 PM UTC 24 |
394619732 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.1269810174 |
|
|
Sep 01 11:17:47 PM UTC 24 |
Sep 01 11:18:08 PM UTC 24 |
973724821 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.2732869051 |
|
|
Sep 01 11:17:56 PM UTC 24 |
Sep 01 11:18:09 PM UTC 24 |
395105744 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.2304344971 |
|
|
Sep 01 11:17:58 PM UTC 24 |
Sep 01 11:18:09 PM UTC 24 |
323672886 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.3545693680 |
|
|
Sep 01 11:17:07 PM UTC 24 |
Sep 01 11:18:10 PM UTC 24 |
7228520459 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.3122214035 |
|
|
Sep 01 11:18:04 PM UTC 24 |
Sep 01 11:18:10 PM UTC 24 |
1412547331 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.610203264 |
|
|
Sep 01 11:18:08 PM UTC 24 |
Sep 01 11:18:10 PM UTC 24 |
45096686 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.882202371 |
|
|
Sep 01 11:17:45 PM UTC 24 |
Sep 01 11:18:12 PM UTC 24 |
700449361 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.1485860295 |
|
|
Sep 01 11:17:58 PM UTC 24 |
Sep 01 11:18:12 PM UTC 24 |
313744746 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3634709866 |
|
|
Sep 01 11:18:04 PM UTC 24 |
Sep 01 11:18:12 PM UTC 24 |
384101037 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.1694614592 |
|
|
Sep 01 11:17:59 PM UTC 24 |
Sep 01 11:18:13 PM UTC 24 |
2286582870 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3152550831 |
|
|
Sep 01 11:18:11 PM UTC 24 |
Sep 01 11:18:13 PM UTC 24 |
15607974 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.2725184302 |
|
|
Sep 01 11:17:55 PM UTC 24 |
Sep 01 11:18:13 PM UTC 24 |
2053689366 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.3212489141 |
|
|
Sep 01 11:14:27 PM UTC 24 |
Sep 01 11:18:13 PM UTC 24 |
9952199152 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.2619689225 |
|
|
Sep 01 11:18:12 PM UTC 24 |
Sep 01 11:18:15 PM UTC 24 |
177759689 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.2756100041 |
|
|
Sep 01 11:18:03 PM UTC 24 |
Sep 01 11:18:16 PM UTC 24 |
80778816 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.1438825594 |
|
|
Sep 01 11:18:13 PM UTC 24 |
Sep 01 11:18:16 PM UTC 24 |
48785995 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.2228316191 |
|
|
Sep 01 11:18:09 PM UTC 24 |
Sep 01 11:18:17 PM UTC 24 |
1481705405 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.4028148243 |
|
|
Sep 01 11:18:11 PM UTC 24 |
Sep 01 11:18:50 PM UTC 24 |
1176928996 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.2882595733 |
|
|
Sep 01 11:18:07 PM UTC 24 |
Sep 01 11:18:17 PM UTC 24 |
205597258 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.1214862641 |
|
|
Sep 01 11:18:16 PM UTC 24 |
Sep 01 11:18:19 PM UTC 24 |
110602030 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.4141069043 |
|
|
Sep 01 11:18:17 PM UTC 24 |
Sep 01 11:18:19 PM UTC 24 |
14165986 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.1882455868 |
|
|
Sep 01 11:18:17 PM UTC 24 |
Sep 01 11:18:20 PM UTC 24 |
52210314 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.2301258886 |
|
|
Sep 01 11:18:07 PM UTC 24 |
Sep 01 11:18:20 PM UTC 24 |
1637439315 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.3168113917 |
|
|
Sep 01 11:18:04 PM UTC 24 |
Sep 01 11:18:20 PM UTC 24 |
608366905 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.3795726802 |
|
|
Sep 01 11:18:06 PM UTC 24 |
Sep 01 11:18:22 PM UTC 24 |
1627422409 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.3467975620 |
|
|
Sep 01 11:18:04 PM UTC 24 |
Sep 01 11:18:22 PM UTC 24 |
1619951261 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.2099887091 |
|
|
Sep 01 11:17:29 PM UTC 24 |
Sep 01 11:18:23 PM UTC 24 |
1020397961 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.1165693725 |
|
|
Sep 01 11:18:19 PM UTC 24 |
Sep 01 11:18:24 PM UTC 24 |
53081879 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.3088614408 |
|
|
Sep 01 11:17:53 PM UTC 24 |
Sep 01 11:18:25 PM UTC 24 |
221644938 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.2962118777 |
|
|
Sep 01 11:18:11 PM UTC 24 |
Sep 01 11:18:25 PM UTC 24 |
112644572 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.1957760878 |
|
|
Sep 01 11:18:14 PM UTC 24 |
Sep 01 11:18:26 PM UTC 24 |
729193755 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.2814666739 |
|
|
Sep 01 11:18:25 PM UTC 24 |
Sep 01 11:18:27 PM UTC 24 |
83725270 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.2554940275 |
|
|
Sep 01 11:18:13 PM UTC 24 |
Sep 01 11:18:28 PM UTC 24 |
1368762387 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.2692520746 |
|
|
Sep 01 11:18:19 PM UTC 24 |
Sep 01 11:18:28 PM UTC 24 |
157926569 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.438323361 |
|
|
Sep 01 11:18:26 PM UTC 24 |
Sep 01 11:18:29 PM UTC 24 |
50022261 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.4237478411 |
|
|
Sep 01 11:16:36 PM UTC 24 |
Sep 01 11:18:29 PM UTC 24 |
14590522224 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.1808060558 |
|
|
Sep 01 11:18:12 PM UTC 24 |
Sep 01 11:18:30 PM UTC 24 |
446478986 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.3706257092 |
|
|
Sep 01 11:18:21 PM UTC 24 |
Sep 01 11:18:30 PM UTC 24 |
1462655856 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.4002458758 |
|
|
Sep 01 11:18:29 PM UTC 24 |
Sep 01 11:18:33 PM UTC 24 |
107856905 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.2595313018 |
|
|
Sep 01 11:18:26 PM UTC 24 |
Sep 01 11:18:35 PM UTC 24 |
89746473 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.3320855965 |
|
|
Sep 01 11:18:30 PM UTC 24 |
Sep 01 11:18:36 PM UTC 24 |
415527275 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.2117783301 |
|
|
Sep 01 11:18:21 PM UTC 24 |
Sep 01 11:18:37 PM UTC 24 |
2595063657 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.85271606 |
|
|
Sep 01 11:18:20 PM UTC 24 |
Sep 01 11:18:37 PM UTC 24 |
1071176359 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.2950640117 |
|
|
Sep 01 11:18:36 PM UTC 24 |
Sep 01 11:18:38 PM UTC 24 |
62741083 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.1754777185 |
|
|
Sep 01 11:18:20 PM UTC 24 |
Sep 01 11:18:38 PM UTC 24 |
433384675 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.1320660000 |
|
|
Sep 01 11:18:37 PM UTC 24 |
Sep 01 11:18:39 PM UTC 24 |
173266966 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.607231742 |
|
|
Sep 01 11:18:13 PM UTC 24 |
Sep 01 11:18:40 PM UTC 24 |
815817051 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.2823005731 |
|
|
Sep 01 11:18:23 PM UTC 24 |
Sep 01 11:18:40 PM UTC 24 |
596646437 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2294007170 |
|
|
Sep 01 11:18:38 PM UTC 24 |
Sep 01 11:18:41 PM UTC 24 |
15947336 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.1117558527 |
|
|
Sep 01 11:18:21 PM UTC 24 |
Sep 01 11:18:41 PM UTC 24 |
2634733742 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.1220041893 |
|
|
Sep 01 11:18:27 PM UTC 24 |
Sep 01 11:18:41 PM UTC 24 |
169486428 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.645870541 |
|
|
Sep 01 11:17:09 PM UTC 24 |
Sep 01 11:18:42 PM UTC 24 |
6686793112 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.3014268462 |
|
|
Sep 01 11:18:39 PM UTC 24 |
Sep 01 11:18:43 PM UTC 24 |
66282962 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.2404279802 |
|
|
Sep 01 11:18:14 PM UTC 24 |
Sep 01 11:18:43 PM UTC 24 |
3805224731 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.903384536 |
|
|
Sep 01 11:18:30 PM UTC 24 |
Sep 01 11:18:44 PM UTC 24 |
1522940971 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.3600353432 |
|
|
Sep 01 11:18:31 PM UTC 24 |
Sep 01 11:18:45 PM UTC 24 |
266936720 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.2085089408 |
|
|
Sep 01 11:18:30 PM UTC 24 |
Sep 01 11:18:45 PM UTC 24 |
3855535381 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.3547136377 |
|
|
Sep 01 11:16:19 PM UTC 24 |
Sep 01 11:18:46 PM UTC 24 |
13833771269 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.604562737 |
|
|
Sep 01 11:16:46 PM UTC 24 |
Sep 01 11:18:46 PM UTC 24 |
6159078555 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.1300716485 |
|
|
Sep 01 11:18:44 PM UTC 24 |
Sep 01 11:18:47 PM UTC 24 |
26017859 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2141497533 |
|
|
Sep 01 11:18:46 PM UTC 24 |
Sep 01 11:18:48 PM UTC 24 |
27691939 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.3169085611 |
|
|
Sep 01 11:18:39 PM UTC 24 |
Sep 01 11:18:49 PM UTC 24 |
56781933 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.2170876555 |
|
|
Sep 01 11:18:46 PM UTC 24 |
Sep 01 11:18:49 PM UTC 24 |
91662612 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.2939356410 |
|
|
Sep 01 11:18:31 PM UTC 24 |
Sep 01 11:18:50 PM UTC 24 |
634636520 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.2076858486 |
|
|
Sep 01 11:18:40 PM UTC 24 |
Sep 01 11:18:52 PM UTC 24 |
2504007009 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.645501829 |
|
|
Sep 01 11:18:48 PM UTC 24 |
Sep 01 11:18:53 PM UTC 24 |
58627156 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.3818218354 |
|
|
Sep 01 11:18:29 PM UTC 24 |
Sep 01 11:18:55 PM UTC 24 |
996079206 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.1809222665 |
|
|
Sep 01 11:18:17 PM UTC 24 |
Sep 01 11:18:55 PM UTC 24 |
234208633 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2938605672 |
|
|
Sep 01 11:18:41 PM UTC 24 |
Sep 01 11:18:56 PM UTC 24 |
1983386371 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.414818530 |
|
|
Sep 01 11:18:48 PM UTC 24 |
Sep 01 11:18:58 PM UTC 24 |
54260921 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.3679464360 |
|
|
Sep 01 11:18:42 PM UTC 24 |
Sep 01 11:18:58 PM UTC 24 |
232658469 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.1626817013 |
|
|
Sep 01 11:18:42 PM UTC 24 |
Sep 01 11:18:58 PM UTC 24 |
257002402 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.4014338621 |
|
|
Sep 01 11:18:01 PM UTC 24 |
Sep 01 11:18:58 PM UTC 24 |
3572478840 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.1654973953 |
|
|
Sep 01 11:18:56 PM UTC 24 |
Sep 01 11:18:58 PM UTC 24 |
67782350 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.3130867205 |
|
|
Sep 01 11:17:50 PM UTC 24 |
Sep 01 11:18:59 PM UTC 24 |
677956825 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.985778830 |
|
|
Sep 01 11:19:07 PM UTC 24 |
Sep 01 11:19:46 PM UTC 24 |
768802901 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.4119365968 |
|
|
Sep 01 11:18:50 PM UTC 24 |
Sep 01 11:18:59 PM UTC 24 |
279472330 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.4251446245 |
|
|
Sep 01 11:18:57 PM UTC 24 |
Sep 01 11:18:59 PM UTC 24 |
83484460 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.933272490 |
|
|
Sep 01 11:18:38 PM UTC 24 |
Sep 01 11:19:01 PM UTC 24 |
210039389 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.1411321191 |
|
|
Sep 01 11:18:42 PM UTC 24 |
Sep 01 11:19:01 PM UTC 24 |
389364586 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.1481378307 |
|
|
Sep 01 11:18:40 PM UTC 24 |
Sep 01 11:19:01 PM UTC 24 |
5572938842 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1550060301 |
|
|
Sep 01 11:18:56 PM UTC 24 |
Sep 01 11:19:02 PM UTC 24 |
80534318 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.2873168043 |
|
|
Sep 01 11:18:59 PM UTC 24 |
Sep 01 11:19:04 PM UTC 24 |
119483669 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.2815280049 |
|
|
Sep 01 11:19:00 PM UTC 24 |
Sep 01 11:19:05 PM UTC 24 |
345388952 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.2111743026 |
|
|
Sep 01 11:19:04 PM UTC 24 |
Sep 01 11:19:06 PM UTC 24 |
26128418 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.2608282389 |
|
|
Sep 01 11:18:51 PM UTC 24 |
Sep 01 11:19:08 PM UTC 24 |
1560198017 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.1327072248 |
|
|
Sep 01 11:19:05 PM UTC 24 |
Sep 01 11:19:08 PM UTC 24 |
540666290 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1020563644 |
|
|
Sep 01 11:19:06 PM UTC 24 |
Sep 01 11:19:08 PM UTC 24 |
63936865 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.2751094747 |
|
|
Sep 01 11:15:55 PM UTC 24 |
Sep 01 11:19:09 PM UTC 24 |
17604696615 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.105404500 |
|
|
Sep 01 11:18:49 PM UTC 24 |
Sep 01 11:19:10 PM UTC 24 |
1976212667 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.1804085930 |
|
|
Sep 01 11:18:23 PM UTC 24 |
Sep 01 11:19:10 PM UTC 24 |
2140205329 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.391820631 |
|
|
Sep 01 11:17:41 PM UTC 24 |
Sep 01 11:19:11 PM UTC 24 |
2505871608 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.1760494749 |
|
|
Sep 01 11:18:48 PM UTC 24 |
Sep 01 11:19:12 PM UTC 24 |
455663703 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1284194694 |
|
|
Sep 01 11:18:50 PM UTC 24 |
Sep 01 11:19:12 PM UTC 24 |
439395913 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.2675051619 |
|
|
Sep 01 11:18:26 PM UTC 24 |
Sep 01 11:19:12 PM UTC 24 |
321743296 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.2608775478 |
|
|
Sep 01 11:19:08 PM UTC 24 |
Sep 01 11:19:13 PM UTC 24 |
67505677 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.2650046851 |
|
|
Sep 01 11:19:01 PM UTC 24 |
Sep 01 11:19:14 PM UTC 24 |
961411244 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.2723709303 |
|
|
Sep 01 11:19:02 PM UTC 24 |
Sep 01 11:19:15 PM UTC 24 |
249754965 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.927642422 |
|
|
Sep 01 11:19:14 PM UTC 24 |
Sep 01 11:19:16 PM UTC 24 |
19707589 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.985090377 |
|
|
Sep 01 11:19:00 PM UTC 24 |
Sep 01 11:19:16 PM UTC 24 |
340295020 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.1664156167 |
|
|
Sep 01 11:19:00 PM UTC 24 |
Sep 01 11:19:17 PM UTC 24 |
2293801295 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1997100211 |
|
|
Sep 01 11:19:15 PM UTC 24 |
Sep 01 11:19:17 PM UTC 24 |
27827747 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.2532005719 |
|
|
Sep 01 11:19:08 PM UTC 24 |
Sep 01 11:19:18 PM UTC 24 |
162105735 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.453546254 |
|
|
Sep 01 11:18:51 PM UTC 24 |
Sep 01 11:19:19 PM UTC 24 |
3226328718 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.1745134667 |
|
|
Sep 01 11:19:15 PM UTC 24 |
Sep 01 11:19:19 PM UTC 24 |
80465648 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.341068596 |
|
|
Sep 01 11:19:01 PM UTC 24 |
Sep 01 11:19:19 PM UTC 24 |
1994848773 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.3303096315 |
|
|
Sep 01 11:19:09 PM UTC 24 |
Sep 01 11:19:20 PM UTC 24 |
257369665 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.2889422224 |
|
|
Sep 01 11:19:00 PM UTC 24 |
Sep 01 11:19:20 PM UTC 24 |
987607323 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.1887566356 |
|
|
Sep 01 11:19:11 PM UTC 24 |
Sep 01 11:19:22 PM UTC 24 |
799710088 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.2356884652 |
|
|
Sep 01 11:19:11 PM UTC 24 |
Sep 01 11:19:22 PM UTC 24 |
1595816610 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.2655224564 |
|
|
Sep 01 11:19:17 PM UTC 24 |
Sep 01 11:19:23 PM UTC 24 |
250002888 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.1557496712 |
|
|
Sep 01 11:19:12 PM UTC 24 |
Sep 01 11:19:23 PM UTC 24 |
308677816 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.5827969 |
|
|
Sep 01 11:19:09 PM UTC 24 |
Sep 01 11:19:24 PM UTC 24 |
341478813 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.3513957255 |
|
|
Sep 01 11:19:22 PM UTC 24 |
Sep 01 11:19:25 PM UTC 24 |
119097614 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.885755847 |
|
|
Sep 01 11:19:24 PM UTC 24 |
Sep 01 11:19:26 PM UTC 24 |
23962479 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.455204568 |
|
|
Sep 01 11:19:22 PM UTC 24 |
Sep 01 11:19:26 PM UTC 24 |
84169929 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1380761340 |
|
|
Sep 01 11:18:08 PM UTC 24 |
Sep 01 11:19:27 PM UTC 24 |
1717165981 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.3459264429 |
|
|
Sep 01 11:19:17 PM UTC 24 |
Sep 01 11:19:28 PM UTC 24 |
248890679 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.1583286304 |
|
|
Sep 01 11:17:38 PM UTC 24 |
Sep 01 11:19:29 PM UTC 24 |
2593330343 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.3087811897 |
|
|
Sep 01 11:15:15 PM UTC 24 |
Sep 01 11:19:29 PM UTC 24 |
30275625695 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.1500861663 |
|
|
Sep 01 11:18:46 PM UTC 24 |
Sep 01 11:19:30 PM UTC 24 |
486267519 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.879017494 |
|
|
Sep 01 11:19:26 PM UTC 24 |
Sep 01 11:19:31 PM UTC 24 |
92998766 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.418644728 |
|
|
Sep 01 11:19:20 PM UTC 24 |
Sep 01 11:19:32 PM UTC 24 |
1401872731 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.2444001332 |
|
|
Sep 01 11:19:11 PM UTC 24 |
Sep 01 11:19:33 PM UTC 24 |
573569695 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.205381749 |
|
|
Sep 01 11:19:28 PM UTC 24 |
Sep 01 11:19:33 PM UTC 24 |
72383394 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.3154643861 |
|
|
Sep 01 11:19:21 PM UTC 24 |
Sep 01 11:19:34 PM UTC 24 |
300087895 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.1782847990 |
|
|
Sep 01 11:19:21 PM UTC 24 |
Sep 01 11:19:35 PM UTC 24 |
435824122 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.2401134418 |
|
|
Sep 01 11:19:34 PM UTC 24 |
Sep 01 11:19:36 PM UTC 24 |
101472949 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1892588203 |
|
|
Sep 01 11:19:18 PM UTC 24 |
Sep 01 11:19:36 PM UTC 24 |
354163422 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2686942096 |
|
|
Sep 01 11:19:34 PM UTC 24 |
Sep 01 11:19:36 PM UTC 24 |
86694344 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2938567618 |
|
|
Sep 01 11:18:15 PM UTC 24 |
Sep 01 11:19:37 PM UTC 24 |
2411729881 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.2495239115 |
|
|
Sep 01 11:19:18 PM UTC 24 |
Sep 01 11:19:38 PM UTC 24 |
615768888 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.1702006098 |
|
|
Sep 01 11:19:34 PM UTC 24 |
Sep 01 11:19:38 PM UTC 24 |
90885704 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.2647259235 |
|
|
Sep 01 11:19:27 PM UTC 24 |
Sep 01 11:19:46 PM UTC 24 |
746082040 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.2944311426 |
|
|
Sep 01 11:19:21 PM UTC 24 |
Sep 01 11:19:38 PM UTC 24 |
1450191537 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.780869599 |
|
|
Sep 01 11:19:36 PM UTC 24 |
Sep 01 11:19:41 PM UTC 24 |
88111294 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.1626157623 |
|
|
Sep 01 11:19:37 PM UTC 24 |
Sep 01 11:19:41 PM UTC 24 |
169598404 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.4262516761 |
|
|
Sep 01 11:15:31 PM UTC 24 |
Sep 01 11:19:41 PM UTC 24 |
44053530275 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.4125198102 |
|
|
Sep 01 11:18:53 PM UTC 24 |
Sep 01 11:19:43 PM UTC 24 |
686667812 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.3343266914 |
|
|
Sep 01 11:19:30 PM UTC 24 |
Sep 01 11:19:43 PM UTC 24 |
655369717 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.1587274589 |
|
|
Sep 01 11:19:25 PM UTC 24 |
Sep 01 11:19:43 PM UTC 24 |
100742500 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.1011820741 |
|
|
Sep 01 11:19:27 PM UTC 24 |
Sep 01 11:19:44 PM UTC 24 |
414001317 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.1031631847 |
|
|
Sep 01 11:19:42 PM UTC 24 |
Sep 01 11:19:45 PM UTC 24 |
12109458 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.3483302933 |
|
|
Sep 01 11:19:30 PM UTC 24 |
Sep 01 11:19:45 PM UTC 24 |
1188517165 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.884269467 |
|
|
Sep 01 11:18:53 PM UTC 24 |
Sep 01 11:19:46 PM UTC 24 |
1471651631 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1200514527 |
|
|
Sep 01 11:19:44 PM UTC 24 |
Sep 01 11:19:46 PM UTC 24 |
26922510 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.1583241849 |
|
|
Sep 01 11:19:39 PM UTC 24 |
Sep 01 11:19:46 PM UTC 24 |
856179607 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.3421236968 |
|
|
Sep 01 11:19:44 PM UTC 24 |
Sep 01 11:19:47 PM UTC 24 |
32963124 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.3838590173 |
|
|
Sep 01 11:19:30 PM UTC 24 |
Sep 01 11:19:47 PM UTC 24 |
1409232275 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.2328195700 |
|
|
Sep 01 11:14:58 PM UTC 24 |
Sep 01 11:19:49 PM UTC 24 |
33315186502 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.1117141144 |
|
|
Sep 01 11:19:48 PM UTC 24 |
Sep 01 11:19:50 PM UTC 24 |
71108793 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.1325597398 |
|
|
Sep 01 11:18:58 PM UTC 24 |
Sep 01 11:19:51 PM UTC 24 |
640345571 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.2262787127 |
|
|
Sep 01 11:20:06 PM UTC 24 |
Sep 01 11:20:55 PM UTC 24 |
972602877 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.1873148812 |
|
|
Sep 01 11:18:00 PM UTC 24 |
Sep 01 11:19:51 PM UTC 24 |
2228440452 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.1515207617 |
|
|
Sep 01 11:19:46 PM UTC 24 |
Sep 01 11:19:51 PM UTC 24 |
116011049 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.351127363 |
|
|
Sep 01 11:19:37 PM UTC 24 |
Sep 01 11:19:52 PM UTC 24 |
337317955 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.3538680753 |
|
|
Sep 01 11:19:39 PM UTC 24 |
Sep 01 11:19:53 PM UTC 24 |
1878584898 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2535033416 |
|
|
Sep 01 11:19:39 PM UTC 24 |
Sep 01 11:19:54 PM UTC 24 |
294440006 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.261930383 |
|
|
Sep 01 11:19:52 PM UTC 24 |
Sep 01 11:19:54 PM UTC 24 |
15768161 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.165800947 |
|
|
Sep 01 11:19:39 PM UTC 24 |
Sep 01 11:19:55 PM UTC 24 |
259280737 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.3679407650 |
|
|
Sep 01 11:19:50 PM UTC 24 |
Sep 01 11:19:56 PM UTC 24 |
108464809 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.3202764870 |
|
|
Sep 01 11:19:46 PM UTC 24 |
Sep 01 11:19:56 PM UTC 24 |
563714625 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.848648853 |
|
|
Sep 01 11:19:52 PM UTC 24 |
Sep 01 11:19:56 PM UTC 24 |
54314939 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.1296751601 |
|
|
Sep 01 11:19:54 PM UTC 24 |
Sep 01 11:19:57 PM UTC 24 |
212884260 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.418731627 |
|
|
Sep 01 11:20:14 PM UTC 24 |
Sep 01 11:20:58 PM UTC 24 |
530715201 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.2784387544 |
|
|
Sep 01 11:19:52 PM UTC 24 |
Sep 01 11:19:57 PM UTC 24 |
482164633 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.4253039736 |
|
|
Sep 01 11:19:45 PM UTC 24 |
Sep 01 11:19:58 PM UTC 24 |
285140628 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.3496014994 |
|
|
Sep 01 11:19:47 PM UTC 24 |
Sep 01 11:19:58 PM UTC 24 |
763274905 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.3132428183 |
|
|
Sep 01 11:19:25 PM UTC 24 |
Sep 01 11:19:59 PM UTC 24 |
199559410 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3531426259 |
|
|
Sep 01 11:19:57 PM UTC 24 |
Sep 01 11:19:59 PM UTC 24 |
47172988 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.2541559461 |
|
|
Sep 01 11:19:57 PM UTC 24 |
Sep 01 11:20:00 PM UTC 24 |
28375099 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.3106828057 |
|
|
Sep 01 11:19:46 PM UTC 24 |
Sep 01 11:20:01 PM UTC 24 |
304726692 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.4251458394 |
|
|
Sep 01 11:19:48 PM UTC 24 |
Sep 01 11:20:03 PM UTC 24 |
1283115282 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.4220467234 |
|
|
Sep 01 11:19:47 PM UTC 24 |
Sep 01 11:20:03 PM UTC 24 |
412337005 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.663044587 |
|
|
Sep 01 11:19:59 PM UTC 24 |
Sep 01 11:20:03 PM UTC 24 |
50728337 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.3159035013 |
|
|
Sep 01 11:19:37 PM UTC 24 |
Sep 01 11:20:04 PM UTC 24 |
2674620406 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.1891324647 |
|
|
Sep 01 11:19:54 PM UTC 24 |
Sep 01 11:20:04 PM UTC 24 |
475644679 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.3001026318 |
|
|
Sep 01 11:19:16 PM UTC 24 |
Sep 01 11:20:04 PM UTC 24 |
1402027247 ps |