| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.95 | 98.04 | 95.77 | 93.40 | 97.67 | 98.76 | 98.76 | 96.29 |
| T1001 | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1825533781 | Sep 01 11:21:11 PM UTC 24 | Sep 01 11:21:19 PM UTC 24 | 1052724071 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.4226760930 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 286429763 ps |
| CPU time | 3.62 seconds |
| Started | Sep 01 11:07:57 PM UTC 24 |
| Finished | Sep 01 11:08:01 PM UTC 24 |
| Peak memory | 225544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226760930 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.4226760930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.1748913334 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 896566436 ps |
| CPU time | 37.35 seconds |
| Started | Sep 01 11:08:03 PM UTC 24 |
| Finished | Sep 01 11:08:41 PM UTC 24 |
| Peak memory | 262516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748913334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ ctrl_jtag_state_post_trans.1748913334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.856215533 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 352661245 ps |
| CPU time | 16.01 seconds |
| Started | Sep 01 11:07:59 PM UTC 24 |
| Finished | Sep 01 11:08:16 PM UTC 24 |
| Peak memory | 232028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856215533 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.856215533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.3082570447 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 430016736 ps |
| CPU time | 14.15 seconds |
| Started | Sep 01 11:09:58 PM UTC 24 |
| Finished | Sep 01 11:10:13 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082570447 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3082570447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3584334132 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1403659392 ps |
| CPU time | 16.14 seconds |
| Started | Sep 01 11:08:11 PM UTC 24 |
| Finished | Sep 01 11:08:29 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584334132 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3584334132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3151261099 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 24947737869 ps |
| CPU time | 69.33 seconds |
| Started | Sep 01 11:08:17 PM UTC 24 |
| Finished | Sep 01 11:09:28 PM UTC 24 |
| Peak memory | 287128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3151261099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.lc_ctrl_stress_all.3151261099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2726713996 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1470903091 ps |
| CPU time | 8.32 seconds |
| Started | Sep 01 11:08:52 PM UTC 24 |
| Finished | Sep 01 11:09:02 PM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726713996 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2726713996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.305148900 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 581551944 ps |
| CPU time | 4.05 seconds |
| Started | Sep 01 11:20:26 PM UTC 24 |
| Finished | Sep 01 11:20:31 PM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305148900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_ena bled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.305148900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.3296423398 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 654685159 ps |
| CPU time | 70.89 seconds |
| Started | Sep 01 11:09:11 PM UTC 24 |
| Finished | Sep 01 11:10:24 PM UTC 24 |
| Peak memory | 298300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296423398 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.3296423398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1741764349 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 43453410 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 11:10:27 PM UTC 24 |
| Finished | Sep 01 11:10:29 PM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741764349 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4. lc_ctrl_volatile_unlock_smoke.1741764349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.427857984 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2082487690 ps |
| CPU time | 96.96 seconds |
| Started | Sep 01 11:09:09 PM UTC 24 |
| Finished | Sep 01 11:10:48 PM UTC 24 |
| Peak memory | 281484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427857984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.427857984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1238794107 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 109760290 ps |
| CPU time | 2.94 seconds |
| Started | Sep 01 11:20:26 PM UTC 24 |
| Finished | Sep 01 11:20:30 PM UTC 24 |
| Peak memory | 233924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238794107 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_ intg_err.1238794107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.3857880868 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 205479538 ps |
| CPU time | 8.51 seconds |
| Started | Sep 01 11:08:13 PM UTC 24 |
| Finished | Sep 01 11:08:23 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857880868 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_ mux.3857880868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1877407412 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 21001821551 ps |
| CPU time | 137.85 seconds |
| Started | Sep 01 11:11:06 PM UTC 24 |
| Finished | Sep 01 11:13:26 PM UTC 24 |
| Peak memory | 280996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877407412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr l_jtag_state_failure.1877407412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.1970869502 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3030640823 ps |
| CPU time | 112.51 seconds |
| Started | Sep 01 11:19:14 PM UTC 24 |
| Finished | Sep 01 11:21:08 PM UTC 24 |
| Peak memory | 281516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970869502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.1970869502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.771454318 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 17606201561 ps |
| CPU time | 118.43 seconds |
| Started | Sep 01 11:09:08 PM UTC 24 |
| Finished | Sep 01 11:11:08 PM UTC 24 |
| Peak memory | 262556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=771454318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.lc_ctrl_stress_all.771454318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2282702253 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 19749316 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 11:20:28 PM UTC 24 |
| Finished | Sep 01 11:20:31 PM UTC 24 |
| Peak memory | 219548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282702253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_al iasing.2282702253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2225661820 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 122311684 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 11:08:21 PM UTC 24 |
| Finished | Sep 01 11:08:24 PM UTC 24 |
| Peak memory | 218528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225661820 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2225661820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.902362603 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1328057205 ps |
| CPU time | 43.62 seconds |
| Started | Sep 01 11:09:16 PM UTC 24 |
| Finished | Sep 01 11:10:01 PM UTC 24 |
| Peak memory | 260452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902362603 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.902362603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1113627159 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 106818503 ps |
| CPU time | 2.91 seconds |
| Started | Sep 01 11:20:36 PM UTC 24 |
| Finished | Sep 01 11:20:40 PM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113627159 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1113627159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2451592750 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1030010540 ps |
| CPU time | 11.49 seconds |
| Started | Sep 01 11:08:35 PM UTC 24 |
| Finished | Sep 01 11:08:48 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451592750 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2451592750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3942962095 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1624878163 ps |
| CPU time | 5.24 seconds |
| Started | Sep 01 11:20:31 PM UTC 24 |
| Finished | Sep 01 11:20:38 PM UTC 24 |
| Peak memory | 230220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942962095 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_ intg_err.3942962095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2187931446 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 253226782 ps |
| CPU time | 9.89 seconds |
| Started | Sep 01 11:08:05 PM UTC 24 |
| Finished | Sep 01 11:08:16 PM UTC 24 |
| Peak memory | 236236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187931446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl _jtag_prog_failure.2187931446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.781843252 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1136827772 ps |
| CPU time | 4.66 seconds |
| Started | Sep 01 11:21:03 PM UTC 24 |
| Finished | Sep 01 11:21:09 PM UTC 24 |
| Peak memory | 235900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781843252 -asse rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_ intg_err.781843252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.4105765916 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 195936485 ps |
| CPU time | 18.97 seconds |
| Started | Sep 01 11:10:57 PM UTC 24 |
| Finished | Sep 01 11:11:17 PM UTC 24 |
| Peak memory | 260796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105765916 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.4105765916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2126554945 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 173303808 ps |
| CPU time | 2.03 seconds |
| Started | Sep 01 11:20:23 PM UTC 24 |
| Finished | Sep 01 11:20:26 PM UTC 24 |
| Peak memory | 221640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2126554945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2126554945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2353757732 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8725668077 ps |
| CPU time | 68.82 seconds |
| Started | Sep 01 11:08:06 PM UTC 24 |
| Finished | Sep 01 11:09:16 PM UTC 24 |
| Peak memory | 231948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353757732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jt ag_errors.2353757732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2191326723 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 5556635531 ps |
| CPU time | 112.15 seconds |
| Started | Sep 01 11:13:20 PM UTC 24 |
| Finished | Sep 01 11:15:14 PM UTC 24 |
| Peak memory | 262704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191326723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.2191326723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3179799964 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 788804782 ps |
| CPU time | 3.42 seconds |
| Started | Sep 01 11:20:22 PM UTC 24 |
| Finished | Sep 01 11:20:27 PM UTC 24 |
| Peak memory | 219792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3179799964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 0.lc_ctrl_jtag_csr_rw.3179799964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.450449290 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 75007277 ps |
| CPU time | 3.26 seconds |
| Started | Sep 01 11:20:31 PM UTC 24 |
| Finished | Sep 01 11:20:36 PM UTC 24 |
| Peak memory | 231820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450449290 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.450449290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1492560554 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 71465548 ps |
| CPU time | 3.72 seconds |
| Started | Sep 01 11:21:07 PM UTC 24 |
| Finished | Sep 01 11:21:12 PM UTC 24 |
| Peak memory | 235864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492560554 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl _intg_err.1492560554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1349246584 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 116598388 ps |
| CPU time | 6.05 seconds |
| Started | Sep 01 11:20:36 PM UTC 24 |
| Finished | Sep 01 11:20:44 PM UTC 24 |
| Peak memory | 229792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349246584 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_ intg_err.1349246584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.97554828 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 237113832 ps |
| CPU time | 15.62 seconds |
| Started | Sep 01 11:08:58 PM UTC 24 |
| Finished | Sep 01 11:09:15 PM UTC 24 |
| Peak memory | 237656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97554828 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.97554828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.1952529077 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 27801001 ps |
| CPU time | 3.19 seconds |
| Started | Sep 01 11:13:23 PM UTC 24 |
| Finished | Sep 01 11:13:27 PM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952529077 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1952529077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.3760207490 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 34045251 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 11:08:42 PM UTC 24 |
| Finished | Sep 01 11:08:44 PM UTC 24 |
| Peak memory | 218768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760207490 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3760207490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.903152974 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 105579582 ps |
| CPU time | 2.97 seconds |
| Started | Sep 01 11:21:11 PM UTC 24 |
| Finished | Sep 01 11:21:15 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903152974 -asse rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_ intg_err.903152974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3283082373 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 104542517 ps |
| CPU time | 4.88 seconds |
| Started | Sep 01 11:20:45 PM UTC 24 |
| Finished | Sep 01 11:20:51 PM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283082373 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_ intg_err.3283082373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.4226652047 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 40379291 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 11:08:01 PM UTC 24 |
| Finished | Sep 01 11:08:04 PM UTC 24 |
| Peak memory | 218708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226652047 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.4226652047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.1510973544 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 13573041 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 11:10:33 PM UTC 24 |
| Finished | Sep 01 11:10:35 PM UTC 24 |
| Peak memory | 218252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510973544 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1510973544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.2676528865 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 10842264 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 11:11:04 PM UTC 24 |
| Finished | Sep 01 11:11:07 PM UTC 24 |
| Peak memory | 218772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676528865 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2676528865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.4028001719 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1066779157 ps |
| CPU time | 49.28 seconds |
| Started | Sep 01 11:08:44 PM UTC 24 |
| Finished | Sep 01 11:09:35 PM UTC 24 |
| Peak memory | 262568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028001719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr l_jtag_state_failure.4028001719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3235140211 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 915375968 ps |
| CPU time | 2.3 seconds |
| Started | Sep 01 11:21:05 PM UTC 24 |
| Finished | Sep 01 11:21:08 PM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235140211 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl _intg_err.3235140211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3934791656 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 103440820 ps |
| CPU time | 4.42 seconds |
| Started | Sep 01 11:20:52 PM UTC 24 |
| Finished | Sep 01 11:20:58 PM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934791656 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_ intg_err.3934791656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3650477210 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 48586034 ps |
| CPU time | 3.32 seconds |
| Started | Sep 01 11:20:55 PM UTC 24 |
| Finished | Sep 01 11:21:00 PM UTC 24 |
| Peak memory | 223952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650477210 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_ intg_err.3650477210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2459500681 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 426007167 ps |
| CPU time | 5.87 seconds |
| Started | Sep 01 11:20:58 PM UTC 24 |
| Finished | Sep 01 11:21:05 PM UTC 24 |
| Peak memory | 230032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459500681 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_ intg_err.2459500681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2110745028 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 172419269 ps |
| CPU time | 3.56 seconds |
| Started | Sep 01 11:21:01 PM UTC 24 |
| Finished | Sep 01 11:21:05 PM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110745028 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_ intg_err.2110745028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3821663264 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7141255926 ps |
| CPU time | 28.68 seconds |
| Started | Sep 01 11:08:10 PM UTC 24 |
| Finished | Sep 01 11:08:40 PM UTC 24 |
| Peak memory | 229636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821663264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ ctrl_jtag_regwen_during_op.3821663264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2257442582 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 355561464 ps |
| CPU time | 5.06 seconds |
| Started | Sep 01 11:20:28 PM UTC 24 |
| Finished | Sep 01 11:20:34 PM UTC 24 |
| Peak memory | 219796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257442582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bi t_bash.2257442582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1934620367 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 38668272 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 11:20:26 PM UTC 24 |
| Finished | Sep 01 11:20:28 PM UTC 24 |
| Peak memory | 220208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934620367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw _reset.1934620367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4228274072 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 59301085 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 11:20:28 PM UTC 24 |
| Finished | Sep 01 11:20:31 PM UTC 24 |
| Peak memory | 236236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4228274072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.4228274072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3315116629 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 13683009 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 11:20:28 PM UTC 24 |
| Finished | Sep 01 11:20:30 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315116629 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3315116629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1832791896 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 153469212 ps |
| CPU time | 3.17 seconds |
| Started | Sep 01 11:20:26 PM UTC 24 |
| Finished | Sep 01 11:20:30 PM UTC 24 |
| Peak memory | 219648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1832791896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1832791896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.888659118 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 299998127 ps |
| CPU time | 7.98 seconds |
| Started | Sep 01 11:20:22 PM UTC 24 |
| Finished | Sep 01 11:20:32 PM UTC 24 |
| Peak memory | 219012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=888659118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.888659118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2513526055 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 558741521 ps |
| CPU time | 9.24 seconds |
| Started | Sep 01 11:20:22 PM UTC 24 |
| Finished | Sep 01 11:20:33 PM UTC 24 |
| Peak memory | 219264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2513526055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2513526055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.25708901 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 73638514 ps |
| CPU time | 3.41 seconds |
| Started | Sep 01 11:20:22 PM UTC 24 |
| Finished | Sep 01 11:20:27 PM UTC 24 |
| Peak memory | 221444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=25708901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.25708901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4075921624 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 84437703 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 11:20:28 PM UTC 24 |
| Finished | Sep 01 11:20:31 PM UTC 24 |
| Peak memory | 218652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407592 1624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc _ctrl_same_csr_outstanding.4075921624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2655477208 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 150437124 ps |
| CPU time | 2.8 seconds |
| Started | Sep 01 11:20:26 PM UTC 24 |
| Finished | Sep 01 11:20:30 PM UTC 24 |
| Peak memory | 229700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655477208 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2655477208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.684771313 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 104057952 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 11:20:33 PM UTC 24 |
| Finished | Sep 01 11:20:36 PM UTC 24 |
| Peak memory | 218412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684771313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_ali asing.684771313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1875350199 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 41716139 ps |
| CPU time | 2 seconds |
| Started | Sep 01 11:20:33 PM UTC 24 |
| Finished | Sep 01 11:20:36 PM UTC 24 |
| Peak memory | 218996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875350199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bi t_bash.1875350199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2608463406 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 32775886 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 11:20:33 PM UTC 24 |
| Finished | Sep 01 11:20:35 PM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608463406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw _reset.2608463406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.927365153 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 112821284 ps |
| CPU time | 1.95 seconds |
| Started | Sep 01 11:20:34 PM UTC 24 |
| Finished | Sep 01 11:20:38 PM UTC 24 |
| Peak memory | 228468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=927365153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.927365153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1053742426 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 64513081 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 11:20:33 PM UTC 24 |
| Finished | Sep 01 11:20:35 PM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053742426 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1053742426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2989764418 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 20835506 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 11:20:31 PM UTC 24 |
| Finished | Sep 01 11:20:34 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2989764418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2989764418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.98158594 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 1155309213 ps |
| CPU time | 8.7 seconds |
| Started | Sep 01 11:20:30 PM UTC 24 |
| Finished | Sep 01 11:20:40 PM UTC 24 |
| Peak memory | 219396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=98158594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.98158594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3887832924 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2147839855 ps |
| CPU time | 8.11 seconds |
| Started | Sep 01 11:20:29 PM UTC 24 |
| Finished | Sep 01 11:20:38 PM UTC 24 |
| Peak memory | 219248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3887832924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3887832924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.435005694 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 93939654 ps |
| CPU time | 2.67 seconds |
| Started | Sep 01 11:20:28 PM UTC 24 |
| Finished | Sep 01 11:20:32 PM UTC 24 |
| Peak memory | 221508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=435005694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.435005694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.512529972 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 89020790 ps |
| CPU time | 4.21 seconds |
| Started | Sep 01 11:20:31 PM UTC 24 |
| Finished | Sep 01 11:20:37 PM UTC 24 |
| Peak memory | 231660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512529972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_ena bled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.512529972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3625167601 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 218231626 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 11:20:29 PM UTC 24 |
| Finished | Sep 01 11:20:32 PM UTC 24 |
| Peak memory | 218696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3625167601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 1.lc_ctrl_jtag_csr_rw.3625167601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1554675445 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 265609346 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 11:20:31 PM UTC 24 |
| Finished | Sep 01 11:20:34 PM UTC 24 |
| Peak memory | 228604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1554675445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1554675445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1453648674 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 30697510 ps |
| CPU time | 1.9 seconds |
| Started | Sep 01 11:20:33 PM UTC 24 |
| Finished | Sep 01 11:20:36 PM UTC 24 |
| Peak memory | 218712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145364 8674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc _ctrl_same_csr_outstanding.1453648674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.992325969 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 16501254 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 11:21:03 PM UTC 24 |
| Finished | Sep 01 11:21:06 PM UTC 24 |
| Peak memory | 228468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=992325969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.992325969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.806906531 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 33021840 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 11:21:03 PM UTC 24 |
| Finished | Sep 01 11:21:05 PM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806906531 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.806906531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2205275596 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 69193893 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 11:21:03 PM UTC 24 |
| Finished | Sep 01 11:21:06 PM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220527 5596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.l c_ctrl_same_csr_outstanding.2205275596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1611899059 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 372823777 ps |
| CPU time | 3.33 seconds |
| Started | Sep 01 11:21:03 PM UTC 24 |
| Finished | Sep 01 11:21:07 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611899059 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1611899059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1157748438 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 113957930 ps |
| CPU time | 1.9 seconds |
| Started | Sep 01 11:21:05 PM UTC 24 |
| Finished | Sep 01 11:21:08 PM UTC 24 |
| Peak memory | 235116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1157748438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1157748438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.213350635 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 15492169 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 11:21:03 PM UTC 24 |
| Finished | Sep 01 11:21:06 PM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213350635 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.213350635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.318882915 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 160722002 ps |
| CPU time | 2.62 seconds |
| Started | Sep 01 11:21:03 PM UTC 24 |
| Finished | Sep 01 11:21:07 PM UTC 24 |
| Peak memory | 219292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318882 915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc _ctrl_same_csr_outstanding.318882915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3815518371 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 219562938 ps |
| CPU time | 4.9 seconds |
| Started | Sep 01 11:21:03 PM UTC 24 |
| Finished | Sep 01 11:21:09 PM UTC 24 |
| Peak memory | 229844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815518371 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3815518371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2123925813 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 224134996 ps |
| CPU time | 2.54 seconds |
| Started | Sep 01 11:21:03 PM UTC 24 |
| Finished | Sep 01 11:21:07 PM UTC 24 |
| Peak memory | 230040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123925813 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl _intg_err.2123925813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1232822372 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 47101968 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 11:21:05 PM UTC 24 |
| Finished | Sep 01 11:21:08 PM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1232822372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1232822372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2231836876 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 19034584 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 11:21:05 PM UTC 24 |
| Finished | Sep 01 11:21:07 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231836876 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2231836876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1984630542 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 30137371 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 11:21:05 PM UTC 24 |
| Finished | Sep 01 11:21:07 PM UTC 24 |
| Peak memory | 218292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198463 0542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.l c_ctrl_same_csr_outstanding.1984630542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1530891444 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 68699229 ps |
| CPU time | 3.78 seconds |
| Started | Sep 01 11:21:05 PM UTC 24 |
| Finished | Sep 01 11:21:10 PM UTC 24 |
| Peak memory | 231824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530891444 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1530891444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2860549216 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 58209912 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 11:21:07 PM UTC 24 |
| Finished | Sep 01 11:21:10 PM UTC 24 |
| Peak memory | 234612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2860549216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2860549216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1462461522 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 35290353 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 11:21:07 PM UTC 24 |
| Finished | Sep 01 11:21:10 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462461522 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1462461522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2021067957 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 156927022 ps |
| CPU time | 2.75 seconds |
| Started | Sep 01 11:21:07 PM UTC 24 |
| Finished | Sep 01 11:21:11 PM UTC 24 |
| Peak memory | 219464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202106 7957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.l c_ctrl_same_csr_outstanding.2021067957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.703677979 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 141646090 ps |
| CPU time | 3.27 seconds |
| Started | Sep 01 11:21:07 PM UTC 24 |
| Finished | Sep 01 11:21:12 PM UTC 24 |
| Peak memory | 229792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703677979 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.703677979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2945564847 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 175863779 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 11:21:08 PM UTC 24 |
| Finished | Sep 01 11:21:10 PM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2945564847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2945564847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1598134750 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 32006144 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 11:21:08 PM UTC 24 |
| Finished | Sep 01 11:21:10 PM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598134750 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1598134750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1324748886 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 108481395 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 11:21:08 PM UTC 24 |
| Finished | Sep 01 11:21:10 PM UTC 24 |
| Peak memory | 220340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132474 8886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.l c_ctrl_same_csr_outstanding.1324748886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3286276812 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 363303602 ps |
| CPU time | 3.54 seconds |
| Started | Sep 01 11:21:07 PM UTC 24 |
| Finished | Sep 01 11:21:12 PM UTC 24 |
| Peak memory | 229696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286276812 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3286276812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1108438270 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1198118535 ps |
| CPU time | 5.2 seconds |
| Started | Sep 01 11:21:07 PM UTC 24 |
| Finished | Sep 01 11:21:14 PM UTC 24 |
| Peak memory | 229784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108438270 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl _intg_err.1108438270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3083200831 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 27256328 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 11:21:11 PM UTC 24 |
| Finished | Sep 01 11:21:14 PM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3083200831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3083200831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1129878111 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 15323633 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 11:21:11 PM UTC 24 |
| Finished | Sep 01 11:21:13 PM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129878111 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1129878111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2170657835 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 113537842 ps |
| CPU time | 2.2 seconds |
| Started | Sep 01 11:21:11 PM UTC 24 |
| Finished | Sep 01 11:21:14 PM UTC 24 |
| Peak memory | 221908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217065 7835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.l c_ctrl_same_csr_outstanding.2170657835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2818038906 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 136300926 ps |
| CPU time | 4.83 seconds |
| Started | Sep 01 11:21:08 PM UTC 24 |
| Finished | Sep 01 11:21:14 PM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818038906 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2818038906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2422337518 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 66970951 ps |
| CPU time | 2.77 seconds |
| Started | Sep 01 11:21:11 PM UTC 24 |
| Finished | Sep 01 11:21:15 PM UTC 24 |
| Peak memory | 230040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422337518 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl _intg_err.2422337518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2824918407 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 38852090 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 11:21:11 PM UTC 24 |
| Finished | Sep 01 11:21:14 PM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2824918407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2824918407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2900291925 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 208745492 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 11:21:11 PM UTC 24 |
| Finished | Sep 01 11:21:14 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900291925 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2900291925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3051513683 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 23364639 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 11:21:11 PM UTC 24 |
| Finished | Sep 01 11:21:14 PM UTC 24 |
| Peak memory | 229040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305151 3683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.l c_ctrl_same_csr_outstanding.3051513683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1825533781 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 1052724071 ps |
| CPU time | 6.9 seconds |
| Started | Sep 01 11:21:11 PM UTC 24 |
| Finished | Sep 01 11:21:19 PM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825533781 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1825533781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3645865021 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 21503052 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 11:21:12 PM UTC 24 |
| Finished | Sep 01 11:21:14 PM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3645865021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3645865021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4122036135 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 48036989 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 11:21:12 PM UTC 24 |
| Finished | Sep 01 11:21:14 PM UTC 24 |
| Peak memory | 218732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122036135 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.4122036135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1543186793 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 73842162 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 11:21:12 PM UTC 24 |
| Finished | Sep 01 11:21:14 PM UTC 24 |
| Peak memory | 220280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154318 6793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.l c_ctrl_same_csr_outstanding.1543186793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3827458147 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 255146719 ps |
| CPU time | 4.79 seconds |
| Started | Sep 01 11:21:12 PM UTC 24 |
| Finished | Sep 01 11:21:17 PM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827458147 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3827458147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4174897716 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 61013678 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 11:21:12 PM UTC 24 |
| Finished | Sep 01 11:21:15 PM UTC 24 |
| Peak memory | 229352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174897716 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl _intg_err.4174897716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1674142839 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 79731409 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 11:21:12 PM UTC 24 |
| Finished | Sep 01 11:21:15 PM UTC 24 |
| Peak memory | 228472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1674142839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1674142839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2976541725 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 105446898 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 11:21:12 PM UTC 24 |
| Finished | Sep 01 11:21:14 PM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976541725 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2976541725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1093626318 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 28668406 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 11:21:12 PM UTC 24 |
| Finished | Sep 01 11:21:14 PM UTC 24 |
| Peak memory | 218708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109362 6318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.l c_ctrl_same_csr_outstanding.1093626318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3009881738 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 61787875 ps |
| CPU time | 3.44 seconds |
| Started | Sep 01 11:21:12 PM UTC 24 |
| Finished | Sep 01 11:21:16 PM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009881738 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3009881738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2353510584 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 315890931 ps |
| CPU time | 3.72 seconds |
| Started | Sep 01 11:21:12 PM UTC 24 |
| Finished | Sep 01 11:21:17 PM UTC 24 |
| Peak memory | 229784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353510584 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl _intg_err.2353510584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.394550083 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 20363967 ps |
| CPU time | 2.11 seconds |
| Started | Sep 01 11:21:14 PM UTC 24 |
| Finished | Sep 01 11:21:17 PM UTC 24 |
| Peak memory | 231808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=394550083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.394550083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3125602638 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 18253344 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 11:21:14 PM UTC 24 |
| Finished | Sep 01 11:21:16 PM UTC 24 |
| Peak memory | 217512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125602638 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3125602638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1054748004 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 154332151 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 11:21:14 PM UTC 24 |
| Finished | Sep 01 11:21:16 PM UTC 24 |
| Peak memory | 220756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105474 8004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.l c_ctrl_same_csr_outstanding.1054748004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2323541318 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 288014222 ps |
| CPU time | 3.71 seconds |
| Started | Sep 01 11:21:14 PM UTC 24 |
| Finished | Sep 01 11:21:19 PM UTC 24 |
| Peak memory | 229712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323541318 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2323541318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.4143052303 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 194570671 ps |
| CPU time | 4.36 seconds |
| Started | Sep 01 11:21:14 PM UTC 24 |
| Finished | Sep 01 11:21:19 PM UTC 24 |
| Peak memory | 235848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143052303 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl _intg_err.4143052303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3532410053 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 48589919 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 11:20:37 PM UTC 24 |
| Finished | Sep 01 11:20:40 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532410053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_al iasing.3532410053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3240879082 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 152656430 ps |
| CPU time | 2.2 seconds |
| Started | Sep 01 11:20:37 PM UTC 24 |
| Finished | Sep 01 11:20:41 PM UTC 24 |
| Peak memory | 218616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240879082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bi t_bash.3240879082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3629387455 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 37799174 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 11:20:37 PM UTC 24 |
| Finished | Sep 01 11:20:40 PM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629387455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw _reset.3629387455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2288588981 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 16377529 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 11:20:39 PM UTC 24 |
| Finished | Sep 01 11:20:41 PM UTC 24 |
| Peak memory | 230508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2288588981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2288588981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1135375155 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 116170741 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 11:20:37 PM UTC 24 |
| Finished | Sep 01 11:20:40 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135375155 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1135375155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3426951613 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 24767604 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 11:20:36 PM UTC 24 |
| Finished | Sep 01 11:20:39 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3426951613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3426951613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.520358964 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 10025819811 ps |
| CPU time | 12.67 seconds |
| Started | Sep 01 11:20:34 PM UTC 24 |
| Finished | Sep 01 11:20:48 PM UTC 24 |
| Peak memory | 219404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=520358964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.520358964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3069639338 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 1105969521 ps |
| CPU time | 22.57 seconds |
| Started | Sep 01 11:20:34 PM UTC 24 |
| Finished | Sep 01 11:20:58 PM UTC 24 |
| Peak memory | 219768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3069639338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3069639338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2954084353 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 590481484 ps |
| CPU time | 3.24 seconds |
| Started | Sep 01 11:20:34 PM UTC 24 |
| Finished | Sep 01 11:20:39 PM UTC 24 |
| Peak memory | 221376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2954084353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2954084353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2043228326 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 292376297 ps |
| CPU time | 1.95 seconds |
| Started | Sep 01 11:20:36 PM UTC 24 |
| Finished | Sep 01 11:20:39 PM UTC 24 |
| Peak memory | 230516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043228326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2043228326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.813959632 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 290399210 ps |
| CPU time | 2.32 seconds |
| Started | Sep 01 11:20:34 PM UTC 24 |
| Finished | Sep 01 11:20:38 PM UTC 24 |
| Peak memory | 219464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=813959632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.lc_ctrl_jtag_csr_rw.813959632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4218121439 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 182758285 ps |
| CPU time | 2.48 seconds |
| Started | Sep 01 11:20:36 PM UTC 24 |
| Finished | Sep 01 11:20:40 PM UTC 24 |
| Peak memory | 219456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4218121439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4218121439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4005153294 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 75361491 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 11:20:37 PM UTC 24 |
| Finished | Sep 01 11:20:40 PM UTC 24 |
| Peak memory | 220284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400515 3294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc _ctrl_same_csr_outstanding.4005153294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.363970500 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 29782056 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 11:20:42 PM UTC 24 |
| Finished | Sep 01 11:20:44 PM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363970500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_ali asing.363970500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4195908771 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 104633440 ps |
| CPU time | 2.18 seconds |
| Started | Sep 01 11:20:42 PM UTC 24 |
| Finished | Sep 01 11:20:45 PM UTC 24 |
| Peak memory | 219424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195908771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bi t_bash.4195908771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2226219955 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 33347729 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 11:20:40 PM UTC 24 |
| Finished | Sep 01 11:20:43 PM UTC 24 |
| Peak memory | 220276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226219955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw _reset.2226219955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.825980376 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 24388333 ps |
| CPU time | 2.09 seconds |
| Started | Sep 01 11:20:42 PM UTC 24 |
| Finished | Sep 01 11:20:45 PM UTC 24 |
| Peak memory | 233936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=825980376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.825980376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3305888801 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 37396764 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 11:20:42 PM UTC 24 |
| Finished | Sep 01 11:20:44 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305888801 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3305888801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3600577226 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 87374789 ps |
| CPU time | 3.61 seconds |
| Started | Sep 01 11:20:40 PM UTC 24 |
| Finished | Sep 01 11:20:45 PM UTC 24 |
| Peak memory | 219068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3600577226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3600577226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2570313491 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2188211837 ps |
| CPU time | 5.1 seconds |
| Started | Sep 01 11:20:39 PM UTC 24 |
| Finished | Sep 01 11:20:45 PM UTC 24 |
| Peak memory | 218736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2570313491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2570313491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3385731318 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 5107853864 ps |
| CPU time | 16.13 seconds |
| Started | Sep 01 11:20:39 PM UTC 24 |
| Finished | Sep 01 11:20:56 PM UTC 24 |
| Peak memory | 219536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3385731318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3385731318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3206842739 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 252708023 ps |
| CPU time | 2.44 seconds |
| Started | Sep 01 11:20:39 PM UTC 24 |
| Finished | Sep 01 11:20:42 PM UTC 24 |
| Peak memory | 221772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3206842739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3206842739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.18563510 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 89661311 ps |
| CPU time | 5.28 seconds |
| Started | Sep 01 11:20:40 PM UTC 24 |
| Finished | Sep 01 11:20:46 PM UTC 24 |
| Peak memory | 235920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18563510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enab led-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.18563510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2265755223 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 67674443 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 11:20:39 PM UTC 24 |
| Finished | Sep 01 11:20:42 PM UTC 24 |
| Peak memory | 218856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2265755223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 3.lc_ctrl_jtag_csr_rw.2265755223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3421564110 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 23076005 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 11:20:40 PM UTC 24 |
| Finished | Sep 01 11:20:42 PM UTC 24 |
| Peak memory | 218284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3421564110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3421564110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2733332729 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 85175282 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 11:20:42 PM UTC 24 |
| Finished | Sep 01 11:20:45 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273333 2729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc _ctrl_same_csr_outstanding.2733332729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2434097395 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 493909947 ps |
| CPU time | 4.12 seconds |
| Started | Sep 01 11:20:40 PM UTC 24 |
| Finished | Sep 01 11:20:45 PM UTC 24 |
| Peak memory | 230040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434097395 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2434097395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2470685205 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 114267558 ps |
| CPU time | 3.01 seconds |
| Started | Sep 01 11:20:40 PM UTC 24 |
| Finished | Sep 01 11:20:44 PM UTC 24 |
| Peak memory | 235848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470685205 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_ intg_err.2470685205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2558903485 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 54759287 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 11:20:46 PM UTC 24 |
| Finished | Sep 01 11:20:49 PM UTC 24 |
| Peak memory | 218584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558903485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_al iasing.2558903485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.710675560 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 463164182 ps |
| CPU time | 3.45 seconds |
| Started | Sep 01 11:20:45 PM UTC 24 |
| Finished | Sep 01 11:20:49 PM UTC 24 |
| Peak memory | 219664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710675560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit _bash.710675560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.935710042 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 21261589 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 11:20:45 PM UTC 24 |
| Finished | Sep 01 11:20:47 PM UTC 24 |
| Peak memory | 220276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935710042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_ reset.935710042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3421942324 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 71130452 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 11:20:46 PM UTC 24 |
| Finished | Sep 01 11:20:49 PM UTC 24 |
| Peak memory | 230516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3421942324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3421942324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2389542571 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 14539156 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 11:20:45 PM UTC 24 |
| Finished | Sep 01 11:20:47 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389542571 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2389542571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3508804239 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 157392952 ps |
| CPU time | 2.08 seconds |
| Started | Sep 01 11:20:44 PM UTC 24 |
| Finished | Sep 01 11:20:47 PM UTC 24 |
| Peak memory | 219316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3508804239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3508804239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1123566303 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 268543916 ps |
| CPU time | 8.06 seconds |
| Started | Sep 01 11:20:42 PM UTC 24 |
| Finished | Sep 01 11:20:51 PM UTC 24 |
| Peak memory | 218824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1123566303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1123566303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4218097373 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 1737836262 ps |
| CPU time | 11.19 seconds |
| Started | Sep 01 11:20:42 PM UTC 24 |
| Finished | Sep 01 11:20:55 PM UTC 24 |
| Peak memory | 219396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4218097373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.4218097373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3112835141 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 628046158 ps |
| CPU time | 5.12 seconds |
| Started | Sep 01 11:20:42 PM UTC 24 |
| Finished | Sep 01 11:20:48 PM UTC 24 |
| Peak memory | 221704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3112835141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3112835141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1935934665 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 1410087925 ps |
| CPU time | 6 seconds |
| Started | Sep 01 11:20:44 PM UTC 24 |
| Finished | Sep 01 11:20:51 PM UTC 24 |
| Peak memory | 231828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935934665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1935934665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1552418956 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 32577499 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 11:20:42 PM UTC 24 |
| Finished | Sep 01 11:20:45 PM UTC 24 |
| Peak memory | 218584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1552418956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.lc_ctrl_jtag_csr_rw.1552418956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.381373608 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 301202947 ps |
| CPU time | 2.18 seconds |
| Started | Sep 01 11:20:43 PM UTC 24 |
| Finished | Sep 01 11:20:47 PM UTC 24 |
| Peak memory | 221860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=381373608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.381373608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1676932473 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 729595033 ps |
| CPU time | 2.32 seconds |
| Started | Sep 01 11:20:46 PM UTC 24 |
| Finished | Sep 01 11:20:50 PM UTC 24 |
| Peak memory | 221528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167693 2473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc _ctrl_same_csr_outstanding.1676932473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2369850890 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 43988310 ps |
| CPU time | 4.11 seconds |
| Started | Sep 01 11:20:44 PM UTC 24 |
| Finished | Sep 01 11:20:49 PM UTC 24 |
| Peak memory | 230040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369850890 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2369850890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.406488851 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 67456085 ps |
| CPU time | 1.92 seconds |
| Started | Sep 01 11:20:49 PM UTC 24 |
| Finished | Sep 01 11:20:52 PM UTC 24 |
| Peak memory | 228468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=406488851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.406488851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3083716159 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 28327888 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 11:20:48 PM UTC 24 |
| Finished | Sep 01 11:20:50 PM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083716159 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3083716159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.921286110 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 69161214 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 11:20:48 PM UTC 24 |
| Finished | Sep 01 11:20:51 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=921286110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.lc_ctrl_jtag_alert_test.921286110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1323539218 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 1950814235 ps |
| CPU time | 11.3 seconds |
| Started | Sep 01 11:20:47 PM UTC 24 |
| Finished | Sep 01 11:20:59 PM UTC 24 |
| Peak memory | 218768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1323539218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1323539218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.849983858 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 697986199 ps |
| CPU time | 13.46 seconds |
| Started | Sep 01 11:20:47 PM UTC 24 |
| Finished | Sep 01 11:21:01 PM UTC 24 |
| Peak memory | 218684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=849983858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.849983858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4068294430 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 52693992 ps |
| CPU time | 2.3 seconds |
| Started | Sep 01 11:20:46 PM UTC 24 |
| Finished | Sep 01 11:20:50 PM UTC 24 |
| Peak memory | 221440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4068294430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.4068294430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2470305818 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 125688356 ps |
| CPU time | 3.23 seconds |
| Started | Sep 01 11:20:48 PM UTC 24 |
| Finished | Sep 01 11:20:52 PM UTC 24 |
| Peak memory | 230180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470305818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2470305818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2817027668 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 250375432 ps |
| CPU time | 2.86 seconds |
| Started | Sep 01 11:20:47 PM UTC 24 |
| Finished | Sep 01 11:20:50 PM UTC 24 |
| Peak memory | 219312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2817027668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 5.lc_ctrl_jtag_csr_rw.2817027668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.417861897 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 19177704 ps |
| CPU time | 1.9 seconds |
| Started | Sep 01 11:20:48 PM UTC 24 |
| Finished | Sep 01 11:20:51 PM UTC 24 |
| Peak memory | 218696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=417861897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.417861897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3499519270 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 161883084 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 11:20:49 PM UTC 24 |
| Finished | Sep 01 11:20:52 PM UTC 24 |
| Peak memory | 218652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349951 9270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc _ctrl_same_csr_outstanding.3499519270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2301776678 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 467051246 ps |
| CPU time | 5.86 seconds |
| Started | Sep 01 11:20:48 PM UTC 24 |
| Finished | Sep 01 11:20:55 PM UTC 24 |
| Peak memory | 229712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301776678 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2301776678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3461832276 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 59239745 ps |
| CPU time | 2.96 seconds |
| Started | Sep 01 11:20:48 PM UTC 24 |
| Finished | Sep 01 11:20:52 PM UTC 24 |
| Peak memory | 233800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461832276 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_ intg_err.3461832276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2096884202 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 32886221 ps |
| CPU time | 2.6 seconds |
| Started | Sep 01 11:20:52 PM UTC 24 |
| Finished | Sep 01 11:20:56 PM UTC 24 |
| Peak memory | 229700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2096884202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2096884202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1276070289 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 31757059 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 11:20:52 PM UTC 24 |
| Finished | Sep 01 11:20:55 PM UTC 24 |
| Peak memory | 218428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276070289 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1276070289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1489424463 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 97883946 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 11:20:51 PM UTC 24 |
| Finished | Sep 01 11:20:54 PM UTC 24 |
| Peak memory | 218788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1489424463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1489424463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1531231265 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 585835370 ps |
| CPU time | 5.98 seconds |
| Started | Sep 01 11:20:51 PM UTC 24 |
| Finished | Sep 01 11:20:58 PM UTC 24 |
| Peak memory | 219228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1531231265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1531231265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1102067918 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 427448169 ps |
| CPU time | 12.57 seconds |
| Started | Sep 01 11:20:51 PM UTC 24 |
| Finished | Sep 01 11:21:04 PM UTC 24 |
| Peak memory | 219472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1102067918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1102067918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1665434715 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 54417217 ps |
| CPU time | 2.36 seconds |
| Started | Sep 01 11:20:49 PM UTC 24 |
| Finished | Sep 01 11:20:53 PM UTC 24 |
| Peak memory | 221832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1665434715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1665434715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1143971896 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 388044324 ps |
| CPU time | 4.35 seconds |
| Started | Sep 01 11:20:51 PM UTC 24 |
| Finished | Sep 01 11:20:56 PM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143971896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1143971896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.414369119 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 64662881 ps |
| CPU time | 1.98 seconds |
| Started | Sep 01 11:20:50 PM UTC 24 |
| Finished | Sep 01 11:20:53 PM UTC 24 |
| Peak memory | 218644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=414369119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.lc_ctrl_jtag_csr_rw.414369119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1245582887 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 70770271 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 11:20:51 PM UTC 24 |
| Finished | Sep 01 11:20:53 PM UTC 24 |
| Peak memory | 218700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1245582887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1245582887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3312489508 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 45437773 ps |
| CPU time | 2.43 seconds |
| Started | Sep 01 11:20:52 PM UTC 24 |
| Finished | Sep 01 11:20:56 PM UTC 24 |
| Peak memory | 219912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331248 9508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc _ctrl_same_csr_outstanding.3312489508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.852615981 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 449736613 ps |
| CPU time | 5.03 seconds |
| Started | Sep 01 11:20:51 PM UTC 24 |
| Finished | Sep 01 11:20:57 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852615981 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.852615981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.663858946 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 20345363 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 11:20:56 PM UTC 24 |
| Finished | Sep 01 11:20:58 PM UTC 24 |
| Peak memory | 228468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=663858946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.663858946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1722595956 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 15855077 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 11:20:56 PM UTC 24 |
| Finished | Sep 01 11:20:58 PM UTC 24 |
| Peak memory | 218672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722595956 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1722595956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2669289393 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 652358310 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 11:20:54 PM UTC 24 |
| Finished | Sep 01 11:20:56 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2669289393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2669289393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2086331637 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 225312935 ps |
| CPU time | 8.86 seconds |
| Started | Sep 01 11:20:54 PM UTC 24 |
| Finished | Sep 01 11:21:04 PM UTC 24 |
| Peak memory | 218344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2086331637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2086331637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.871252458 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 1316633718 ps |
| CPU time | 6.77 seconds |
| Started | Sep 01 11:20:54 PM UTC 24 |
| Finished | Sep 01 11:21:02 PM UTC 24 |
| Peak memory | 219268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=871252458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.871252458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.4211772120 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 444948322 ps |
| CPU time | 4.48 seconds |
| Started | Sep 01 11:20:53 PM UTC 24 |
| Finished | Sep 01 11:20:58 PM UTC 24 |
| Peak memory | 221768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4211772120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.4211772120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3931264758 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 206129642 ps |
| CPU time | 3.34 seconds |
| Started | Sep 01 11:20:54 PM UTC 24 |
| Finished | Sep 01 11:20:58 PM UTC 24 |
| Peak memory | 235916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931264758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3931264758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1145459456 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 342874645 ps |
| CPU time | 3.09 seconds |
| Started | Sep 01 11:20:54 PM UTC 24 |
| Finished | Sep 01 11:20:58 PM UTC 24 |
| Peak memory | 219308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1145459456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 7.lc_ctrl_jtag_csr_rw.1145459456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.799829895 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 30723579 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 11:20:54 PM UTC 24 |
| Finished | Sep 01 11:20:57 PM UTC 24 |
| Peak memory | 218708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=799829895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.799829895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2571997152 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 25756857 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 11:20:56 PM UTC 24 |
| Finished | Sep 01 11:20:58 PM UTC 24 |
| Peak memory | 218296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257199 7152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc _ctrl_same_csr_outstanding.2571997152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3339717096 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 52543532 ps |
| CPU time | 2.6 seconds |
| Started | Sep 01 11:20:54 PM UTC 24 |
| Finished | Sep 01 11:20:58 PM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339717096 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3339717096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4256719128 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 43553651 ps |
| CPU time | 2.48 seconds |
| Started | Sep 01 11:20:59 PM UTC 24 |
| Finished | Sep 01 11:21:02 PM UTC 24 |
| Peak memory | 229768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4256719128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.4256719128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.276054926 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 105504349 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 11:20:59 PM UTC 24 |
| Finished | Sep 01 11:21:01 PM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276054926 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.276054926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.818466611 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 15907780 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 11:20:58 PM UTC 24 |
| Finished | Sep 01 11:21:01 PM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=818466611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.lc_ctrl_jtag_alert_test.818466611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1419179071 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 378675198 ps |
| CPU time | 7.12 seconds |
| Started | Sep 01 11:20:57 PM UTC 24 |
| Finished | Sep 01 11:21:05 PM UTC 24 |
| Peak memory | 219296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1419179071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1419179071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1592691084 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 13594675237 ps |
| CPU time | 16.23 seconds |
| Started | Sep 01 11:20:57 PM UTC 24 |
| Finished | Sep 01 11:21:14 PM UTC 24 |
| Peak memory | 219820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1592691084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1592691084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2508050004 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 191296511 ps |
| CPU time | 3.35 seconds |
| Started | Sep 01 11:20:56 PM UTC 24 |
| Finished | Sep 01 11:21:00 PM UTC 24 |
| Peak memory | 221832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2508050004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2508050004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1773676966 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 200793028 ps |
| CPU time | 2.92 seconds |
| Started | Sep 01 11:20:57 PM UTC 24 |
| Finished | Sep 01 11:21:01 PM UTC 24 |
| Peak memory | 231708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773676966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1773676966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3265548816 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 64285626 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 11:20:57 PM UTC 24 |
| Finished | Sep 01 11:21:00 PM UTC 24 |
| Peak memory | 218876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3265548816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 8.lc_ctrl_jtag_csr_rw.3265548816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4092221286 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 272102839 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 11:20:57 PM UTC 24 |
| Finished | Sep 01 11:21:00 PM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4092221286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.4092221286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3866393992 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 193297797 ps |
| CPU time | 2.01 seconds |
| Started | Sep 01 11:20:59 PM UTC 24 |
| Finished | Sep 01 11:21:02 PM UTC 24 |
| Peak memory | 220404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386639 3992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc _ctrl_same_csr_outstanding.3866393992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3135406632 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 129392623 ps |
| CPU time | 8.18 seconds |
| Started | Sep 01 11:20:58 PM UTC 24 |
| Finished | Sep 01 11:21:08 PM UTC 24 |
| Peak memory | 229788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135406632 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3135406632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1266606132 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 32183663 ps |
| CPU time | 2.01 seconds |
| Started | Sep 01 11:21:03 PM UTC 24 |
| Finished | Sep 01 11:21:06 PM UTC 24 |
| Peak memory | 229840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1266606132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1266606132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3864353054 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 30085730 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 11:21:01 PM UTC 24 |
| Finished | Sep 01 11:21:03 PM UTC 24 |
| Peak memory | 228892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864353054 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3864353054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2688269476 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 60202130 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 11:21:01 PM UTC 24 |
| Finished | Sep 01 11:21:03 PM UTC 24 |
| Peak memory | 218736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2688269476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2688269476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2256773561 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 2483842776 ps |
| CPU time | 15.89 seconds |
| Started | Sep 01 11:21:01 PM UTC 24 |
| Finished | Sep 01 11:21:18 PM UTC 24 |
| Peak memory | 219080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2256773561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2256773561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.262862578 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 694151132 ps |
| CPU time | 9.58 seconds |
| Started | Sep 01 11:21:00 PM UTC 24 |
| Finished | Sep 01 11:21:11 PM UTC 24 |
| Peak memory | 219344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=262862578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.262862578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3792862941 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 83035443 ps |
| CPU time | 3.04 seconds |
| Started | Sep 01 11:20:59 PM UTC 24 |
| Finished | Sep 01 11:21:03 PM UTC 24 |
| Peak memory | 221440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3792862941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3792862941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1485601322 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 103534819 ps |
| CPU time | 2.61 seconds |
| Started | Sep 01 11:21:01 PM UTC 24 |
| Finished | Sep 01 11:21:04 PM UTC 24 |
| Peak memory | 229844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485601322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1485601322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1470684917 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 80053574 ps |
| CPU time | 2.38 seconds |
| Started | Sep 01 11:20:59 PM UTC 24 |
| Finished | Sep 01 11:21:02 PM UTC 24 |
| Peak memory | 219744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1470684917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 9.lc_ctrl_jtag_csr_rw.1470684917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3572318502 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 58003615 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 11:21:01 PM UTC 24 |
| Finished | Sep 01 11:21:03 PM UTC 24 |
| Peak memory | 218284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3572318502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3572318502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3271095153 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 112325380 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 11:21:01 PM UTC 24 |
| Finished | Sep 01 11:21:03 PM UTC 24 |
| Peak memory | 218712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327109 5153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc _ctrl_same_csr_outstanding.3271095153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3182202725 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 153070928 ps |
| CPU time | 3.05 seconds |
| Started | Sep 01 11:21:01 PM UTC 24 |
| Finished | Sep 01 11:21:05 PM UTC 24 |
| Peak memory | 231760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182202725 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3182202725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3702277046 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 150539908 ps |
| CPU time | 5.78 seconds |
| Started | Sep 01 11:08:07 PM UTC 24 |
| Finished | Sep 01 11:08:14 PM UTC 24 |
| Peak memory | 229952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702277046 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3702277046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3874010304 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 269155151 ps |
| CPU time | 5.44 seconds |
| Started | Sep 01 11:08:09 PM UTC 24 |
| Finished | Sep 01 11:08:16 PM UTC 24 |
| Peak memory | 229660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874010304 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_prior ity.3874010304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.927564308 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1299233787 ps |
| CPU time | 7.4 seconds |
| Started | Sep 01 11:08:02 PM UTC 24 |
| Finished | Sep 01 11:08:10 PM UTC 24 |
| Peak memory | 229484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927564308 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_sm oke.927564308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.1182342572 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 25224518425 ps |
| CPU time | 63.81 seconds |
| Started | Sep 01 11:08:02 PM UTC 24 |
| Finished | Sep 01 11:09:07 PM UTC 24 |
| Peak memory | 281124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182342572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr l_jtag_state_failure.1182342572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1471341040 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 235713301 ps |
| CPU time | 5.15 seconds |
| Started | Sep 01 11:07:59 PM UTC 24 |
| Finished | Sep 01 11:08:05 PM UTC 24 |
| Peak memory | 236044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471341040 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1471341040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.2730011344 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 987858847 ps |
| CPU time | 7.42 seconds |
| Started | Sep 01 11:08:01 PM UTC 24 |
| Finished | Sep 01 11:08:10 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730011344 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2730011344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.42636551 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 398307740 ps |
| CPU time | 36.71 seconds |
| Started | Sep 01 11:08:17 PM UTC 24 |
| Finished | Sep 01 11:08:55 PM UTC 24 |
| Peak memory | 289996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42636551 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.42636551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.3530878273 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2066544239 ps |
| CPU time | 26.97 seconds |
| Started | Sep 01 11:08:15 PM UTC 24 |
| Finished | Sep 01 11:08:43 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530878273 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_tok en_digest.3530878273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1905302074 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 1407221388 ps |
| CPU time | 17.59 seconds |
| Started | Sep 01 11:08:01 PM UTC 24 |
| Finished | Sep 01 11:08:20 PM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905302074 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1905302074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.2073002124 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 467322473 ps |
| CPU time | 34.17 seconds |
| Started | Sep 01 11:07:59 PM UTC 24 |
| Finished | Sep 01 11:08:34 PM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073002124 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2073002124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.3694379250 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 91281805 ps |
| CPU time | 8.71 seconds |
| Started | Sep 01 11:07:59 PM UTC 24 |
| Finished | Sep 01 11:08:08 PM UTC 24 |
| Peak memory | 262508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694379250 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3694379250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.981016413 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 89122208 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 11:07:57 PM UTC 24 |
| Finished | Sep 01 11:07:59 PM UTC 24 |
| Peak memory | 222892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981016413 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.l c_ctrl_volatile_unlock_smoke.981016413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.1302179998 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 44385703 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 11:09:13 PM UTC 24 |
| Finished | Sep 01 11:09:16 PM UTC 24 |
| Peak memory | 218584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302179998 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1302179998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.1786223828 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 981457426 ps |
| CPU time | 30.83 seconds |
| Started | Sep 01 11:08:35 PM UTC 24 |
| Finished | Sep 01 11:09:08 PM UTC 24 |
| Peak memory | 237592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786223828 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1786223828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.841028525 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1891818789 ps |
| CPU time | 60.38 seconds |
| Started | Sep 01 11:08:51 PM UTC 24 |
| Finished | Sep 01 11:09:53 PM UTC 24 |
| Peak memory | 237524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841028525 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta g_errors.841028525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.2138833918 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 434702947 ps |
| CPU time | 2.9 seconds |
| Started | Sep 01 11:08:53 PM UTC 24 |
| Finished | Sep 01 11:08:57 PM UTC 24 |
| Peak memory | 230024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138833918 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_prior ity.2138833918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.3527471954 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 492392229 ps |
| CPU time | 19.17 seconds |
| Started | Sep 01 11:08:50 PM UTC 24 |
| Finished | Sep 01 11:09:10 PM UTC 24 |
| Peak memory | 236332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527471954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl _jtag_prog_failure.3527471954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2546709139 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2539438767 ps |
| CPU time | 25.89 seconds |
| Started | Sep 01 11:08:56 PM UTC 24 |
| Finished | Sep 01 11:09:23 PM UTC 24 |
| Peak memory | 229636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546709139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ ctrl_jtag_regwen_during_op.2546709139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.1602823808 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1644788826 ps |
| CPU time | 6.8 seconds |
| Started | Sep 01 11:08:43 PM UTC 24 |
| Finished | Sep 01 11:08:51 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602823808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_s moke.1602823808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3976193159 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3330641477 ps |
| CPU time | 29.15 seconds |
| Started | Sep 01 11:08:45 PM UTC 24 |
| Finished | Sep 01 11:09:16 PM UTC 24 |
| Peak memory | 262576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976193159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ ctrl_jtag_state_post_trans.3976193159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.309327046 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 102591948 ps |
| CPU time | 2.35 seconds |
| Started | Sep 01 11:08:31 PM UTC 24 |
| Finished | Sep 01 11:08:34 PM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309327046 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.309327046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.2934595171 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 220396544 ps |
| CPU time | 10.16 seconds |
| Started | Sep 01 11:08:41 PM UTC 24 |
| Finished | Sep 01 11:08:52 PM UTC 24 |
| Peak memory | 229640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934595171 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2934595171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.3658090462 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 469948397 ps |
| CPU time | 12.3 seconds |
| Started | Sep 01 11:09:02 PM UTC 24 |
| Finished | Sep 01 11:09:16 PM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658090462 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_tok en_digest.3658090462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.825053159 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 386224120 ps |
| CPU time | 11.27 seconds |
| Started | Sep 01 11:09:01 PM UTC 24 |
| Finished | Sep 01 11:09:14 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825053159 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.825053159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.3182767950 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 62042716 ps |
| CPU time | 4.41 seconds |
| Started | Sep 01 11:08:24 PM UTC 24 |
| Finished | Sep 01 11:08:30 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182767950 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3182767950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.814420135 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 584207191 ps |
| CPU time | 31.71 seconds |
| Started | Sep 01 11:08:27 PM UTC 24 |
| Finished | Sep 01 11:09:01 PM UTC 24 |
| Peak memory | 262504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814420135 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.814420135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.1306989710 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 318777762 ps |
| CPU time | 10.73 seconds |
| Started | Sep 01 11:08:30 PM UTC 24 |
| Finished | Sep 01 11:08:42 PM UTC 24 |
| Peak memory | 260372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306989710 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1306989710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2763290773 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 33808587 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 11:08:24 PM UTC 24 |
| Finished | Sep 01 11:08:27 PM UTC 24 |
| Peak memory | 222384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763290773 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. lc_ctrl_volatile_unlock_smoke.2763290773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.3816483111 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 33776238 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 11:13:04 PM UTC 24 |
| Finished | Sep 01 11:13:07 PM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816483111 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3816483111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.1963457990 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 625432583 ps |
| CPU time | 25.9 seconds |
| Started | Sep 01 11:12:50 PM UTC 24 |
| Finished | Sep 01 11:13:17 PM UTC 24 |
| Peak memory | 237672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963457990 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1963457990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.3290342355 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1117977092 ps |
| CPU time | 23.96 seconds |
| Started | Sep 01 11:12:59 PM UTC 24 |
| Finished | Sep 01 11:13:25 PM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290342355 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3290342355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.2356554114 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 8553139784 ps |
| CPU time | 47.61 seconds |
| Started | Sep 01 11:12:56 PM UTC 24 |
| Finished | Sep 01 11:13:45 PM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356554114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_j tag_errors.2356554114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.4104410483 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4408014562 ps |
| CPU time | 8.07 seconds |
| Started | Sep 01 11:12:56 PM UTC 24 |
| Finished | Sep 01 11:13:05 PM UTC 24 |
| Peak memory | 231992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104410483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctr l_jtag_prog_failure.4104410483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3375039253 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2481411567 ps |
| CPU time | 12.43 seconds |
| Started | Sep 01 11:12:52 PM UTC 24 |
| Finished | Sep 01 11:13:05 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375039253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_ smoke.3375039253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.3438864906 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 2079864262 ps |
| CPU time | 42.81 seconds |
| Started | Sep 01 11:12:53 PM UTC 24 |
| Finished | Sep 01 11:13:37 PM UTC 24 |
| Peak memory | 262512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438864906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct rl_jtag_state_failure.3438864906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.4253020013 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 988640065 ps |
| CPU time | 34.42 seconds |
| Started | Sep 01 11:12:55 PM UTC 24 |
| Finished | Sep 01 11:13:31 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253020013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc _ctrl_jtag_state_post_trans.4253020013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.2173055036 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 102846992 ps |
| CPU time | 2.68 seconds |
| Started | Sep 01 11:12:48 PM UTC 24 |
| Finished | Sep 01 11:12:52 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173055036 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2173055036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3632088498 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 189519103 ps |
| CPU time | 13.35 seconds |
| Started | Sep 01 11:13:01 PM UTC 24 |
| Finished | Sep 01 11:13:15 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632088498 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3632088498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3269961287 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1720664104 ps |
| CPU time | 13.27 seconds |
| Started | Sep 01 11:13:02 PM UTC 24 |
| Finished | Sep 01 11:13:16 PM UTC 24 |
| Peak memory | 237512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269961287 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_to ken_digest.3269961287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.2455241918 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 912074082 ps |
| CPU time | 12.39 seconds |
| Started | Sep 01 11:13:02 PM UTC 24 |
| Finished | Sep 01 11:13:15 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455241918 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token _mux.2455241918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.2311465039 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 159246686 ps |
| CPU time | 8.66 seconds |
| Started | Sep 01 11:12:51 PM UTC 24 |
| Finished | Sep 01 11:13:00 PM UTC 24 |
| Peak memory | 231964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311465039 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2311465039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.1898921356 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 35361490 ps |
| CPU time | 2.76 seconds |
| Started | Sep 01 11:12:45 PM UTC 24 |
| Finished | Sep 01 11:12:49 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898921356 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1898921356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.297831403 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 932634436 ps |
| CPU time | 27.73 seconds |
| Started | Sep 01 11:12:47 PM UTC 24 |
| Finished | Sep 01 11:13:16 PM UTC 24 |
| Peak memory | 262504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297831403 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.297831403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.314827994 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 78969560 ps |
| CPU time | 13.49 seconds |
| Started | Sep 01 11:12:48 PM UTC 24 |
| Finished | Sep 01 11:13:03 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314827994 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.314827994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.1858807983 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 9501930157 ps |
| CPU time | 284.12 seconds |
| Started | Sep 01 11:13:02 PM UTC 24 |
| Finished | Sep 01 11:17:50 PM UTC 24 |
| Peak memory | 289120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1858807983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 10.lc_ctrl_stress_all.1858807983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3106212905 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 12369870 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 11:12:45 PM UTC 24 |
| Finished | Sep 01 11:12:47 PM UTC 24 |
| Peak memory | 218532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106212905 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10 .lc_ctrl_volatile_unlock_smoke.3106212905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.725437877 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 31990465 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 11:13:22 PM UTC 24 |
| Finished | Sep 01 11:13:24 PM UTC 24 |
| Peak memory | 217372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725437877 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.725437877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.1481839950 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1060824663 ps |
| CPU time | 18.16 seconds |
| Started | Sep 01 11:13:10 PM UTC 24 |
| Finished | Sep 01 11:13:29 PM UTC 24 |
| Peak memory | 232084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481839950 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1481839950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.1669110997 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 67917014 ps |
| CPU time | 2.58 seconds |
| Started | Sep 01 11:13:18 PM UTC 24 |
| Finished | Sep 01 11:13:22 PM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669110997 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1669110997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.2479259088 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 6308763746 ps |
| CPU time | 42.35 seconds |
| Started | Sep 01 11:13:17 PM UTC 24 |
| Finished | Sep 01 11:14:01 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479259088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_j tag_errors.2479259088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.3292653975 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 793892690 ps |
| CPU time | 23.37 seconds |
| Started | Sep 01 11:13:17 PM UTC 24 |
| Finished | Sep 01 11:13:41 PM UTC 24 |
| Peak memory | 236292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292653975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctr l_jtag_prog_failure.3292653975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.3140262004 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1346666014 ps |
| CPU time | 5.75 seconds |
| Started | Sep 01 11:13:14 PM UTC 24 |
| Finished | Sep 01 11:13:21 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140262004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_ smoke.3140262004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.2069719279 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1892320180 ps |
| CPU time | 92.68 seconds |
| Started | Sep 01 11:13:17 PM UTC 24 |
| Finished | Sep 01 11:14:51 PM UTC 24 |
| Peak memory | 291232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069719279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct rl_jtag_state_failure.2069719279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.2057527788 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 350120275 ps |
| CPU time | 20.03 seconds |
| Started | Sep 01 11:13:17 PM UTC 24 |
| Finished | Sep 01 11:13:38 PM UTC 24 |
| Peak memory | 260636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057527788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc _ctrl_jtag_state_post_trans.2057527788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1736739626 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 651686407 ps |
| CPU time | 4.37 seconds |
| Started | Sep 01 11:13:10 PM UTC 24 |
| Finished | Sep 01 11:13:15 PM UTC 24 |
| Peak memory | 231968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736739626 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1736739626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.4232578884 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 509250189 ps |
| CPU time | 13.71 seconds |
| Started | Sep 01 11:13:18 PM UTC 24 |
| Finished | Sep 01 11:13:33 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232578884 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.4232578884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.665829425 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 717582300 ps |
| CPU time | 26.35 seconds |
| Started | Sep 01 11:13:18 PM UTC 24 |
| Finished | Sep 01 11:13:46 PM UTC 24 |
| Peak memory | 237516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665829425 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_tok en_digest.665829425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.2555311010 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 305394424 ps |
| CPU time | 17.3 seconds |
| Started | Sep 01 11:13:18 PM UTC 24 |
| Finished | Sep 01 11:13:37 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555311010 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token _mux.2555311010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.4014280777 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 412257794 ps |
| CPU time | 10.23 seconds |
| Started | Sep 01 11:13:10 PM UTC 24 |
| Finished | Sep 01 11:13:21 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014280777 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.4014280777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.2337762837 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 104758189 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 11:13:06 PM UTC 24 |
| Finished | Sep 01 11:13:09 PM UTC 24 |
| Peak memory | 228620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337762837 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2337762837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.3623011442 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 228568504 ps |
| CPU time | 27.27 seconds |
| Started | Sep 01 11:13:08 PM UTC 24 |
| Finished | Sep 01 11:13:36 PM UTC 24 |
| Peak memory | 258408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623011442 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3623011442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.291065233 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 74913223 ps |
| CPU time | 7.8 seconds |
| Started | Sep 01 11:13:09 PM UTC 24 |
| Finished | Sep 01 11:13:18 PM UTC 24 |
| Peak memory | 260440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291065233 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.291065233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.2360481784 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 12129114854 ps |
| CPU time | 89.08 seconds |
| Started | Sep 01 11:13:18 PM UTC 24 |
| Finished | Sep 01 11:14:50 PM UTC 24 |
| Peak memory | 237980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2360481784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 11.lc_ctrl_stress_all.2360481784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3714475044 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 19673725 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 11:13:06 PM UTC 24 |
| Finished | Sep 01 11:13:09 PM UTC 24 |
| Peak memory | 228712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714475044 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11 .lc_ctrl_volatile_unlock_smoke.3714475044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.3426533446 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 60582814 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 11:13:40 PM UTC 24 |
| Finished | Sep 01 11:13:42 PM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426533446 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3426533446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.1414914771 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1504769338 ps |
| CPU time | 17.53 seconds |
| Started | Sep 01 11:13:27 PM UTC 24 |
| Finished | Sep 01 11:13:46 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414914771 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1414914771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.1389013908 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 325003645 ps |
| CPU time | 3.57 seconds |
| Started | Sep 01 11:13:34 PM UTC 24 |
| Finished | Sep 01 11:13:39 PM UTC 24 |
| Peak memory | 229948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389013908 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1389013908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.35885946 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3209875023 ps |
| CPU time | 41.56 seconds |
| Started | Sep 01 11:13:32 PM UTC 24 |
| Finished | Sep 01 11:14:15 PM UTC 24 |
| Peak memory | 231900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35885946 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta g_errors.35885946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.2892845832 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 196146361 ps |
| CPU time | 8.75 seconds |
| Started | Sep 01 11:13:32 PM UTC 24 |
| Finished | Sep 01 11:13:42 PM UTC 24 |
| Peak memory | 231328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892845832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctr l_jtag_prog_failure.2892845832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.414870151 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 58396851 ps |
| CPU time | 3.2 seconds |
| Started | Sep 01 11:13:29 PM UTC 24 |
| Finished | Sep 01 11:13:33 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414870151 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_s moke.414870151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.426513662 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1279710213 ps |
| CPU time | 53.18 seconds |
| Started | Sep 01 11:13:31 PM UTC 24 |
| Finished | Sep 01 11:14:26 PM UTC 24 |
| Peak memory | 282936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426513662 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctr l_jtag_state_failure.426513662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.116796389 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 367356802 ps |
| CPU time | 16.99 seconds |
| Started | Sep 01 11:13:32 PM UTC 24 |
| Finished | Sep 01 11:13:50 PM UTC 24 |
| Peak memory | 262560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116796389 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ ctrl_jtag_state_post_trans.116796389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.2683999296 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 137244405 ps |
| CPU time | 3.69 seconds |
| Started | Sep 01 11:13:26 PM UTC 24 |
| Finished | Sep 01 11:13:31 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683999296 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2683999296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.2239758038 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 1557245540 ps |
| CPU time | 18.08 seconds |
| Started | Sep 01 11:13:34 PM UTC 24 |
| Finished | Sep 01 11:13:53 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239758038 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2239758038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.1655521964 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1997236962 ps |
| CPU time | 17.91 seconds |
| Started | Sep 01 11:13:38 PM UTC 24 |
| Finished | Sep 01 11:13:57 PM UTC 24 |
| Peak memory | 231816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655521964 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_to ken_digest.1655521964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.2278675299 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 722137697 ps |
| CPU time | 10.68 seconds |
| Started | Sep 01 11:13:37 PM UTC 24 |
| Finished | Sep 01 11:13:49 PM UTC 24 |
| Peak memory | 237912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278675299 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token _mux.2278675299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.847496755 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 559144323 ps |
| CPU time | 12.16 seconds |
| Started | Sep 01 11:13:27 PM UTC 24 |
| Finished | Sep 01 11:13:41 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847496755 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.847496755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.3879845613 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 953808211 ps |
| CPU time | 42.49 seconds |
| Started | Sep 01 11:13:25 PM UTC 24 |
| Finished | Sep 01 11:14:09 PM UTC 24 |
| Peak memory | 260452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879845613 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3879845613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.704806686 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 52042339 ps |
| CPU time | 4.78 seconds |
| Started | Sep 01 11:13:25 PM UTC 24 |
| Finished | Sep 01 11:13:31 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704806686 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.704806686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.1835741953 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 4269738934 ps |
| CPU time | 181.91 seconds |
| Started | Sep 01 11:13:39 PM UTC 24 |
| Finished | Sep 01 11:16:44 PM UTC 24 |
| Peak memory | 262640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1835741953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 12.lc_ctrl_stress_all.1835741953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.1152241889 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 9430153929 ps |
| CPU time | 128.35 seconds |
| Started | Sep 01 11:13:39 PM UTC 24 |
| Finished | Sep 01 11:15:49 PM UTC 24 |
| Peak memory | 279152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152241889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.1152241889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1657923392 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 42057366 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 11:13:23 PM UTC 24 |
| Finished | Sep 01 11:13:25 PM UTC 24 |
| Peak memory | 218356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657923392 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12 .lc_ctrl_volatile_unlock_smoke.1657923392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.1069451682 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 140920780 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 11:13:58 PM UTC 24 |
| Finished | Sep 01 11:14:01 PM UTC 24 |
| Peak memory | 219060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069451682 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1069451682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.1146252438 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 500856120 ps |
| CPU time | 27.34 seconds |
| Started | Sep 01 11:13:46 PM UTC 24 |
| Finished | Sep 01 11:14:14 PM UTC 24 |
| Peak memory | 232280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146252438 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1146252438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.4113070011 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 808391504 ps |
| CPU time | 9.64 seconds |
| Started | Sep 01 11:13:51 PM UTC 24 |
| Finished | Sep 01 11:14:01 PM UTC 24 |
| Peak memory | 229528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113070011 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.4113070011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.2865029437 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2375165483 ps |
| CPU time | 42.42 seconds |
| Started | Sep 01 11:13:50 PM UTC 24 |
| Finished | Sep 01 11:14:34 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865029437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_j tag_errors.2865029437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.3697087713 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 672579401 ps |
| CPU time | 7.62 seconds |
| Started | Sep 01 11:13:49 PM UTC 24 |
| Finished | Sep 01 11:13:58 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697087713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctr l_jtag_prog_failure.3697087713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.2345900358 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 604451714 ps |
| CPU time | 8.32 seconds |
| Started | Sep 01 11:13:47 PM UTC 24 |
| Finished | Sep 01 11:13:56 PM UTC 24 |
| Peak memory | 229484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345900358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_ smoke.2345900358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.43100233 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 5932460741 ps |
| CPU time | 58.2 seconds |
| Started | Sep 01 11:13:47 PM UTC 24 |
| Finished | Sep 01 11:14:47 PM UTC 24 |
| Peak memory | 280928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43100233 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl _jtag_state_failure.43100233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.1446801790 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 778587480 ps |
| CPU time | 34.9 seconds |
| Started | Sep 01 11:13:47 PM UTC 24 |
| Finished | Sep 01 11:14:23 PM UTC 24 |
| Peak memory | 262444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446801790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc _ctrl_jtag_state_post_trans.1446801790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.3287928448 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 102663639 ps |
| CPU time | 2.92 seconds |
| Started | Sep 01 11:13:45 PM UTC 24 |
| Finished | Sep 01 11:13:49 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287928448 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3287928448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.30257131 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 859965037 ps |
| CPU time | 13.37 seconds |
| Started | Sep 01 11:13:52 PM UTC 24 |
| Finished | Sep 01 11:14:06 PM UTC 24 |
| Peak memory | 232320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30257131 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.30257131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.181637610 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1653687879 ps |
| CPU time | 10.98 seconds |
| Started | Sep 01 11:13:55 PM UTC 24 |
| Finished | Sep 01 11:14:07 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181637610 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_tok en_digest.181637610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.3474738141 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 4494699965 ps |
| CPU time | 13.91 seconds |
| Started | Sep 01 11:13:55 PM UTC 24 |
| Finished | Sep 01 11:14:10 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474738141 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token _mux.3474738141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.3146752301 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 293355832 ps |
| CPU time | 12.47 seconds |
| Started | Sep 01 11:13:46 PM UTC 24 |
| Finished | Sep 01 11:13:59 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146752301 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3146752301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.1097673687 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 46048722 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 11:13:42 PM UTC 24 |
| Finished | Sep 01 11:13:45 PM UTC 24 |
| Peak memory | 228692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097673687 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1097673687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.1319045000 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 339247365 ps |
| CPU time | 46.53 seconds |
| Started | Sep 01 11:13:43 PM UTC 24 |
| Finished | Sep 01 11:14:32 PM UTC 24 |
| Peak memory | 260452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319045000 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1319045000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.1025114785 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 579354344 ps |
| CPU time | 13.84 seconds |
| Started | Sep 01 11:13:43 PM UTC 24 |
| Finished | Sep 01 11:13:58 PM UTC 24 |
| Peak memory | 262832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025114785 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1025114785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.1101642602 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 16504664627 ps |
| CPU time | 546.49 seconds |
| Started | Sep 01 11:13:57 PM UTC 24 |
| Finished | Sep 01 11:23:11 PM UTC 24 |
| Peak memory | 272884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1101642602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 13.lc_ctrl_stress_all.1101642602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2309239871 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 18002229 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 11:13:42 PM UTC 24 |
| Finished | Sep 01 11:13:45 PM UTC 24 |
| Peak memory | 228752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309239871 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13 .lc_ctrl_volatile_unlock_smoke.2309239871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.4194333706 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 65201498 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 11:14:15 PM UTC 24 |
| Finished | Sep 01 11:14:17 PM UTC 24 |
| Peak memory | 218448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194333706 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.4194333706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_errors.701334504 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 5094673909 ps |
| CPU time | 18.81 seconds |
| Started | Sep 01 11:14:02 PM UTC 24 |
| Finished | Sep 01 11:14:23 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701334504 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.701334504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.1898223385 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 679711582 ps |
| CPU time | 11.77 seconds |
| Started | Sep 01 11:14:08 PM UTC 24 |
| Finished | Sep 01 11:14:21 PM UTC 24 |
| Peak memory | 229316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898223385 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1898223385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.3834479478 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2785345741 ps |
| CPU time | 59.47 seconds |
| Started | Sep 01 11:14:08 PM UTC 24 |
| Finished | Sep 01 11:15:09 PM UTC 24 |
| Peak memory | 237904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834479478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_j tag_errors.3834479478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.1698901278 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 236774341 ps |
| CPU time | 6.04 seconds |
| Started | Sep 01 11:14:07 PM UTC 24 |
| Finished | Sep 01 11:14:14 PM UTC 24 |
| Peak memory | 232148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698901278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctr l_jtag_prog_failure.1698901278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.3302044433 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 614274750 ps |
| CPU time | 6.41 seconds |
| Started | Sep 01 11:14:04 PM UTC 24 |
| Finished | Sep 01 11:14:12 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302044433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_ smoke.3302044433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.2902109166 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 4768735046 ps |
| CPU time | 61.18 seconds |
| Started | Sep 01 11:14:05 PM UTC 24 |
| Finished | Sep 01 11:15:09 PM UTC 24 |
| Peak memory | 262564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902109166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct rl_jtag_state_failure.2902109166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.1538957514 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1193738968 ps |
| CPU time | 19.28 seconds |
| Started | Sep 01 11:14:07 PM UTC 24 |
| Finished | Sep 01 11:14:28 PM UTC 24 |
| Peak memory | 236640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538957514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc _ctrl_jtag_state_post_trans.1538957514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.2152934501 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 32633934 ps |
| CPU time | 3.1 seconds |
| Started | Sep 01 11:14:02 PM UTC 24 |
| Finished | Sep 01 11:14:07 PM UTC 24 |
| Peak memory | 231724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152934501 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2152934501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.375815199 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 352249818 ps |
| CPU time | 13.32 seconds |
| Started | Sep 01 11:14:08 PM UTC 24 |
| Finished | Sep 01 11:14:23 PM UTC 24 |
| Peak memory | 237912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375815199 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.375815199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.151938528 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 257184617 ps |
| CPU time | 11.24 seconds |
| Started | Sep 01 11:14:11 PM UTC 24 |
| Finished | Sep 01 11:14:24 PM UTC 24 |
| Peak memory | 237844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151938528 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_tok en_digest.151938528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.577819802 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 732125041 ps |
| CPU time | 11.2 seconds |
| Started | Sep 01 11:14:10 PM UTC 24 |
| Finished | Sep 01 11:14:23 PM UTC 24 |
| Peak memory | 237804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577819802 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_ mux.577819802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.140792005 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 380101993 ps |
| CPU time | 18.4 seconds |
| Started | Sep 01 11:14:04 PM UTC 24 |
| Finished | Sep 01 11:14:24 PM UTC 24 |
| Peak memory | 237596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140792005 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.140792005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.3759149875 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 128815044 ps |
| CPU time | 5.86 seconds |
| Started | Sep 01 11:14:00 PM UTC 24 |
| Finished | Sep 01 11:14:07 PM UTC 24 |
| Peak memory | 229964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759149875 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3759149875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.2716205389 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 218845193 ps |
| CPU time | 30.07 seconds |
| Started | Sep 01 11:14:00 PM UTC 24 |
| Finished | Sep 01 11:14:31 PM UTC 24 |
| Peak memory | 262836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716205389 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2716205389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.3797267274 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 266052536 ps |
| CPU time | 11.13 seconds |
| Started | Sep 01 11:14:01 PM UTC 24 |
| Finished | Sep 01 11:14:13 PM UTC 24 |
| Peak memory | 262768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797267274 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3797267274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.468842960 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3270118446 ps |
| CPU time | 33.16 seconds |
| Started | Sep 01 11:14:13 PM UTC 24 |
| Finished | Sep 01 11:14:47 PM UTC 24 |
| Peak memory | 232468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=468842960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 14.lc_ctrl_stress_all.468842960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3000720305 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 120092489 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 11:14:00 PM UTC 24 |
| Finished | Sep 01 11:14:03 PM UTC 24 |
| Peak memory | 228712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000720305 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14 .lc_ctrl_volatile_unlock_smoke.3000720305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.4121590747 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 28254496 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 11:14:30 PM UTC 24 |
| Finished | Sep 01 11:14:32 PM UTC 24 |
| Peak memory | 218584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121590747 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.4121590747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.4274925255 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 809702349 ps |
| CPU time | 22.61 seconds |
| Started | Sep 01 11:14:22 PM UTC 24 |
| Finished | Sep 01 11:14:46 PM UTC 24 |
| Peak memory | 237672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274925255 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.4274925255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.3041165971 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 951347266 ps |
| CPU time | 3.39 seconds |
| Started | Sep 01 11:14:25 PM UTC 24 |
| Finished | Sep 01 11:14:29 PM UTC 24 |
| Peak memory | 229432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041165971 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3041165971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.248798003 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 35258329236 ps |
| CPU time | 60.05 seconds |
| Started | Sep 01 11:14:25 PM UTC 24 |
| Finished | Sep 01 11:15:26 PM UTC 24 |
| Peak memory | 232060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248798003 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt ag_errors.248798003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.639020826 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 10451841097 ps |
| CPU time | 10.3 seconds |
| Started | Sep 01 11:14:24 PM UTC 24 |
| Finished | Sep 01 11:14:36 PM UTC 24 |
| Peak memory | 232024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639020826 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl _jtag_prog_failure.639020826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.3974668511 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 448188689 ps |
| CPU time | 12.86 seconds |
| Started | Sep 01 11:14:24 PM UTC 24 |
| Finished | Sep 01 11:14:38 PM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974668511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_ smoke.3974668511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.2050384978 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 5503615845 ps |
| CPU time | 62.18 seconds |
| Started | Sep 01 11:14:24 PM UTC 24 |
| Finished | Sep 01 11:15:28 PM UTC 24 |
| Peak memory | 260448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050384978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct rl_jtag_state_failure.2050384978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.596974605 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 2539985818 ps |
| CPU time | 29.57 seconds |
| Started | Sep 01 11:14:24 PM UTC 24 |
| Finished | Sep 01 11:14:55 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596974605 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ ctrl_jtag_state_post_trans.596974605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.2709209695 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 210398867 ps |
| CPU time | 4.01 seconds |
| Started | Sep 01 11:14:19 PM UTC 24 |
| Finished | Sep 01 11:14:25 PM UTC 24 |
| Peak memory | 236308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709209695 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2709209695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.4036827069 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 517210890 ps |
| CPU time | 20.6 seconds |
| Started | Sep 01 11:14:26 PM UTC 24 |
| Finished | Sep 01 11:14:48 PM UTC 24 |
| Peak memory | 237920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036827069 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.4036827069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.650383616 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 2324733838 ps |
| CPU time | 22.32 seconds |
| Started | Sep 01 11:14:27 PM UTC 24 |
| Finished | Sep 01 11:14:51 PM UTC 24 |
| Peak memory | 237580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650383616 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_tok en_digest.650383616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.3818365629 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 303204841 ps |
| CPU time | 16.04 seconds |
| Started | Sep 01 11:14:26 PM UTC 24 |
| Finished | Sep 01 11:14:43 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818365629 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token _mux.3818365629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.3281912373 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1108026919 ps |
| CPU time | 14.22 seconds |
| Started | Sep 01 11:14:23 PM UTC 24 |
| Finished | Sep 01 11:14:38 PM UTC 24 |
| Peak memory | 237932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281912373 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3281912373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.2329327503 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 168512354 ps |
| CPU time | 5.09 seconds |
| Started | Sep 01 11:14:15 PM UTC 24 |
| Finished | Sep 01 11:14:21 PM UTC 24 |
| Peak memory | 225760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329327503 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2329327503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.826497093 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 698553171 ps |
| CPU time | 47.61 seconds |
| Started | Sep 01 11:14:16 PM UTC 24 |
| Finished | Sep 01 11:15:05 PM UTC 24 |
| Peak memory | 258740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826497093 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.826497093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.1108740721 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 60996659 ps |
| CPU time | 9.55 seconds |
| Started | Sep 01 11:14:18 PM UTC 24 |
| Finished | Sep 01 11:14:29 PM UTC 24 |
| Peak memory | 260436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108740721 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1108740721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.3212489141 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 9952199152 ps |
| CPU time | 222.26 seconds |
| Started | Sep 01 11:14:27 PM UTC 24 |
| Finished | Sep 01 11:18:13 PM UTC 24 |
| Peak memory | 281124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3212489141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 15.lc_ctrl_stress_all.3212489141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2531250044 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 126786480 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 11:14:16 PM UTC 24 |
| Finished | Sep 01 11:14:19 PM UTC 24 |
| Peak memory | 218560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531250044 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15 .lc_ctrl_volatile_unlock_smoke.2531250044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.4246759470 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 60713883 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 11:14:48 PM UTC 24 |
| Finished | Sep 01 11:14:51 PM UTC 24 |
| Peak memory | 218464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246759470 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.4246759470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.1515920574 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2498482809 ps |
| CPU time | 9.84 seconds |
| Started | Sep 01 11:14:35 PM UTC 24 |
| Finished | Sep 01 11:14:47 PM UTC 24 |
| Peak memory | 232276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515920574 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1515920574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.4039914654 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 92715801 ps |
| CPU time | 4.4 seconds |
| Started | Sep 01 11:14:39 PM UTC 24 |
| Finished | Sep 01 11:14:45 PM UTC 24 |
| Peak memory | 229512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039914654 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.4039914654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.629596600 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 3685295465 ps |
| CPU time | 66.28 seconds |
| Started | Sep 01 11:14:39 PM UTC 24 |
| Finished | Sep 01 11:15:47 PM UTC 24 |
| Peak memory | 237592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629596600 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt ag_errors.629596600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.1463860634 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 325678236 ps |
| CPU time | 7.82 seconds |
| Started | Sep 01 11:14:39 PM UTC 24 |
| Finished | Sep 01 11:14:48 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463860634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctr l_jtag_prog_failure.1463860634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.3031705242 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 218378233 ps |
| CPU time | 8.34 seconds |
| Started | Sep 01 11:14:36 PM UTC 24 |
| Finished | Sep 01 11:14:45 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031705242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_ smoke.3031705242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.727545199 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1730207999 ps |
| CPU time | 76.03 seconds |
| Started | Sep 01 11:14:37 PM UTC 24 |
| Finished | Sep 01 11:15:55 PM UTC 24 |
| Peak memory | 284948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727545199 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctr l_jtag_state_failure.727545199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.128289061 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2688158314 ps |
| CPU time | 12.71 seconds |
| Started | Sep 01 11:14:37 PM UTC 24 |
| Finished | Sep 01 11:14:51 PM UTC 24 |
| Peak memory | 236308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128289061 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ ctrl_jtag_state_post_trans.128289061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.447552747 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 192386177 ps |
| CPU time | 3.42 seconds |
| Started | Sep 01 11:14:34 PM UTC 24 |
| Finished | Sep 01 11:14:39 PM UTC 24 |
| Peak memory | 236060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447552747 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.447552747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.1814791284 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 178871188 ps |
| CPU time | 11.19 seconds |
| Started | Sep 01 11:14:42 PM UTC 24 |
| Finished | Sep 01 11:14:55 PM UTC 24 |
| Peak memory | 237924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814791284 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1814791284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.2964375932 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 496238063 ps |
| CPU time | 10.88 seconds |
| Started | Sep 01 11:14:46 PM UTC 24 |
| Finished | Sep 01 11:14:58 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964375932 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_to ken_digest.2964375932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.223002057 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 328590992 ps |
| CPU time | 8.84 seconds |
| Started | Sep 01 11:14:44 PM UTC 24 |
| Finished | Sep 01 11:14:54 PM UTC 24 |
| Peak memory | 231888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223002057 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_ mux.223002057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.942167894 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 341820511 ps |
| CPU time | 12.11 seconds |
| Started | Sep 01 11:14:36 PM UTC 24 |
| Finished | Sep 01 11:14:49 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942167894 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.942167894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.1377976177 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 76244322 ps |
| CPU time | 4.18 seconds |
| Started | Sep 01 11:14:30 PM UTC 24 |
| Finished | Sep 01 11:14:35 PM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377976177 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1377976177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.409994438 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 272552131 ps |
| CPU time | 38.06 seconds |
| Started | Sep 01 11:14:33 PM UTC 24 |
| Finished | Sep 01 11:15:12 PM UTC 24 |
| Peak memory | 258744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409994438 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.409994438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.3083145182 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 86443848 ps |
| CPU time | 7.77 seconds |
| Started | Sep 01 11:14:33 PM UTC 24 |
| Finished | Sep 01 11:14:42 PM UTC 24 |
| Peak memory | 260528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083145182 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3083145182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.2251931699 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 61159787472 ps |
| CPU time | 524.77 seconds |
| Started | Sep 01 11:14:46 PM UTC 24 |
| Finished | Sep 01 11:23:38 PM UTC 24 |
| Peak memory | 285488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2251931699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 16.lc_ctrl_stress_all.2251931699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3113155218 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 40381243 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 11:14:32 PM UTC 24 |
| Finished | Sep 01 11:14:34 PM UTC 24 |
| Peak memory | 222388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113155218 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16 .lc_ctrl_volatile_unlock_smoke.3113155218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.2067834644 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 27884208 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 11:15:01 PM UTC 24 |
| Finished | Sep 01 11:15:04 PM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067834644 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2067834644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.3915351845 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1168279173 ps |
| CPU time | 21.18 seconds |
| Started | Sep 01 11:14:51 PM UTC 24 |
| Finished | Sep 01 11:15:13 PM UTC 24 |
| Peak memory | 237464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915351845 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3915351845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.2661343582 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 593357278 ps |
| CPU time | 5.95 seconds |
| Started | Sep 01 11:14:56 PM UTC 24 |
| Finished | Sep 01 11:15:03 PM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661343582 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2661343582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.3709164264 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1596765120 ps |
| CPU time | 33.56 seconds |
| Started | Sep 01 11:14:54 PM UTC 24 |
| Finished | Sep 01 11:15:29 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709164264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_j tag_errors.3709164264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.805637845 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1039765790 ps |
| CPU time | 10.77 seconds |
| Started | Sep 01 11:14:52 PM UTC 24 |
| Finished | Sep 01 11:15:04 PM UTC 24 |
| Peak memory | 236032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805637845 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl _jtag_prog_failure.805637845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.4164458140 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 116469933 ps |
| CPU time | 3.9 seconds |
| Started | Sep 01 11:14:52 PM UTC 24 |
| Finished | Sep 01 11:14:57 PM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164458140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_ smoke.4164458140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.575505878 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 5071176981 ps |
| CPU time | 47.89 seconds |
| Started | Sep 01 11:14:52 PM UTC 24 |
| Finished | Sep 01 11:15:41 PM UTC 24 |
| Peak memory | 285108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575505878 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctr l_jtag_state_failure.575505878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.2736334273 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1655348825 ps |
| CPU time | 24.95 seconds |
| Started | Sep 01 11:14:52 PM UTC 24 |
| Finished | Sep 01 11:15:18 PM UTC 24 |
| Peak memory | 262420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736334273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc _ctrl_jtag_state_post_trans.2736334273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.1466184287 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 84073087 ps |
| CPU time | 2.67 seconds |
| Started | Sep 01 11:14:50 PM UTC 24 |
| Finished | Sep 01 11:14:53 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466184287 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1466184287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.4076762623 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 1202153786 ps |
| CPU time | 18.33 seconds |
| Started | Sep 01 11:14:56 PM UTC 24 |
| Finished | Sep 01 11:15:15 PM UTC 24 |
| Peak memory | 237664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076762623 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.4076762623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.1723606391 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1291810356 ps |
| CPU time | 18.32 seconds |
| Started | Sep 01 11:14:58 PM UTC 24 |
| Finished | Sep 01 11:15:17 PM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723606391 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_to ken_digest.1723606391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.352720419 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2939974237 ps |
| CPU time | 14.08 seconds |
| Started | Sep 01 11:14:57 PM UTC 24 |
| Finished | Sep 01 11:15:12 PM UTC 24 |
| Peak memory | 237740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352720419 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_ mux.352720419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.49683926 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 350879260 ps |
| CPU time | 13.21 seconds |
| Started | Sep 01 11:14:51 PM UTC 24 |
| Finished | Sep 01 11:15:05 PM UTC 24 |
| Peak memory | 231772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49683926 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.49683926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.2906800709 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 347108040 ps |
| CPU time | 7.51 seconds |
| Started | Sep 01 11:14:48 PM UTC 24 |
| Finished | Sep 01 11:14:57 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906800709 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2906800709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.1406382077 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1671536816 ps |
| CPU time | 32.87 seconds |
| Started | Sep 01 11:14:49 PM UTC 24 |
| Finished | Sep 01 11:15:24 PM UTC 24 |
| Peak memory | 262504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406382077 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1406382077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.555174469 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 86623692 ps |
| CPU time | 9.2 seconds |
| Started | Sep 01 11:14:49 PM UTC 24 |
| Finished | Sep 01 11:15:00 PM UTC 24 |
| Peak memory | 260360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555174469 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.555174469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.2328195700 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 33315186502 ps |
| CPU time | 287.54 seconds |
| Started | Sep 01 11:14:58 PM UTC 24 |
| Finished | Sep 01 11:19:49 PM UTC 24 |
| Peak memory | 293484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2328195700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 17.lc_ctrl_stress_all.2328195700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3142189020 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 13360582 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 11:14:48 PM UTC 24 |
| Finished | Sep 01 11:14:50 PM UTC 24 |
| Peak memory | 218412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142189020 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17 .lc_ctrl_volatile_unlock_smoke.3142189020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.2470249471 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 17338503 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 11:15:19 PM UTC 24 |
| Finished | Sep 01 11:15:21 PM UTC 24 |
| Peak memory | 217372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470249471 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2470249471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.3956433357 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1597022935 ps |
| CPU time | 19.72 seconds |
| Started | Sep 01 11:15:08 PM UTC 24 |
| Finished | Sep 01 11:15:29 PM UTC 24 |
| Peak memory | 237596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956433357 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3956433357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.3347270654 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 167240468 ps |
| CPU time | 2.56 seconds |
| Started | Sep 01 11:15:14 PM UTC 24 |
| Finished | Sep 01 11:15:17 PM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347270654 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3347270654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.713650515 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 80909450996 ps |
| CPU time | 121.57 seconds |
| Started | Sep 01 11:15:13 PM UTC 24 |
| Finished | Sep 01 11:17:17 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713650515 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt ag_errors.713650515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.2230625007 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1740557589 ps |
| CPU time | 8.55 seconds |
| Started | Sep 01 11:15:10 PM UTC 24 |
| Finished | Sep 01 11:15:20 PM UTC 24 |
| Peak memory | 235904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230625007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctr l_jtag_prog_failure.2230625007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.3352351151 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1574587190 ps |
| CPU time | 8.29 seconds |
| Started | Sep 01 11:15:08 PM UTC 24 |
| Finished | Sep 01 11:15:17 PM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352351151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_ smoke.3352351151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.2973856504 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 5139283897 ps |
| CPU time | 69.18 seconds |
| Started | Sep 01 11:15:08 PM UTC 24 |
| Finished | Sep 01 11:16:19 PM UTC 24 |
| Peak memory | 295320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973856504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct rl_jtag_state_failure.2973856504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.2821063126 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 899169386 ps |
| CPU time | 44.79 seconds |
| Started | Sep 01 11:15:10 PM UTC 24 |
| Finished | Sep 01 11:15:57 PM UTC 24 |
| Peak memory | 262440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821063126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc _ctrl_jtag_state_post_trans.2821063126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.4268105117 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 315942485 ps |
| CPU time | 5.38 seconds |
| Started | Sep 01 11:15:07 PM UTC 24 |
| Finished | Sep 01 11:15:13 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268105117 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.4268105117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.3590608400 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 7222957992 ps |
| CPU time | 19.29 seconds |
| Started | Sep 01 11:15:14 PM UTC 24 |
| Finished | Sep 01 11:15:34 PM UTC 24 |
| Peak memory | 237644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590608400 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3590608400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.1259315587 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1016771927 ps |
| CPU time | 12.66 seconds |
| Started | Sep 01 11:15:15 PM UTC 24 |
| Finished | Sep 01 11:15:29 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259315587 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_to ken_digest.1259315587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.580000978 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 361718412 ps |
| CPU time | 13.03 seconds |
| Started | Sep 01 11:15:14 PM UTC 24 |
| Finished | Sep 01 11:15:28 PM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580000978 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_ mux.580000978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3119109872 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 526089663 ps |
| CPU time | 15.63 seconds |
| Started | Sep 01 11:15:08 PM UTC 24 |
| Finished | Sep 01 11:15:25 PM UTC 24 |
| Peak memory | 231892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119109872 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3119109872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.4147029004 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 570709918 ps |
| CPU time | 2.7 seconds |
| Started | Sep 01 11:15:03 PM UTC 24 |
| Finished | Sep 01 11:15:07 PM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147029004 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.4147029004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.1177712587 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 206231949 ps |
| CPU time | 40.44 seconds |
| Started | Sep 01 11:15:05 PM UTC 24 |
| Finished | Sep 01 11:15:47 PM UTC 24 |
| Peak memory | 262580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177712587 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1177712587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.1056844040 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 184902000 ps |
| CPU time | 6.03 seconds |
| Started | Sep 01 11:15:07 PM UTC 24 |
| Finished | Sep 01 11:15:14 PM UTC 24 |
| Peak memory | 235968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056844040 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1056844040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.3087811897 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 30275625695 ps |
| CPU time | 249.85 seconds |
| Started | Sep 01 11:15:15 PM UTC 24 |
| Finished | Sep 01 11:19:29 PM UTC 24 |
| Peak memory | 281328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3087811897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 18.lc_ctrl_stress_all.3087811897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1158104309 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 39193212018 ps |
| CPU time | 68.22 seconds |
| Started | Sep 01 11:15:17 PM UTC 24 |
| Finished | Sep 01 11:16:27 PM UTC 24 |
| Peak memory | 285420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158104309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.1158104309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3796041323 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 11013846 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 11:15:04 PM UTC 24 |
| Finished | Sep 01 11:15:06 PM UTC 24 |
| Peak memory | 218652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796041323 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18 .lc_ctrl_volatile_unlock_smoke.3796041323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.3493560216 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 19080536 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 11:15:35 PM UTC 24 |
| Finished | Sep 01 11:15:38 PM UTC 24 |
| Peak memory | 218476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493560216 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3493560216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.1040665458 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 256232409 ps |
| CPU time | 16.76 seconds |
| Started | Sep 01 11:15:22 PM UTC 24 |
| Finished | Sep 01 11:15:40 PM UTC 24 |
| Peak memory | 237924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040665458 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1040665458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.1791170475 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2148344245 ps |
| CPU time | 10.75 seconds |
| Started | Sep 01 11:15:29 PM UTC 24 |
| Finished | Sep 01 11:15:41 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791170475 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1791170475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.2198448493 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1711301647 ps |
| CPU time | 53.99 seconds |
| Started | Sep 01 11:15:28 PM UTC 24 |
| Finished | Sep 01 11:16:24 PM UTC 24 |
| Peak memory | 237112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198448493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_j tag_errors.2198448493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.140847835 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 476227191 ps |
| CPU time | 5.75 seconds |
| Started | Sep 01 11:15:28 PM UTC 24 |
| Finished | Sep 01 11:15:35 PM UTC 24 |
| Peak memory | 231812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140847835 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl _jtag_prog_failure.140847835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.487339419 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 86026467 ps |
| CPU time | 2.59 seconds |
| Started | Sep 01 11:15:26 PM UTC 24 |
| Finished | Sep 01 11:15:29 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487339419 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_s moke.487339419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.1767260008 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 10962884321 ps |
| CPU time | 79.57 seconds |
| Started | Sep 01 11:15:26 PM UTC 24 |
| Finished | Sep 01 11:16:47 PM UTC 24 |
| Peak memory | 282984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767260008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct rl_jtag_state_failure.1767260008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.3715572254 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2034509057 ps |
| CPU time | 19.09 seconds |
| Started | Sep 01 11:15:26 PM UTC 24 |
| Finished | Sep 01 11:15:46 PM UTC 24 |
| Peak memory | 260372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715572254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc _ctrl_jtag_state_post_trans.3715572254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.4208902908 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 221211584 ps |
| CPU time | 3.49 seconds |
| Started | Sep 01 11:15:22 PM UTC 24 |
| Finished | Sep 01 11:15:27 PM UTC 24 |
| Peak memory | 232188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208902908 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4208902908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.2738989761 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 510711965 ps |
| CPU time | 11.38 seconds |
| Started | Sep 01 11:15:29 PM UTC 24 |
| Finished | Sep 01 11:15:42 PM UTC 24 |
| Peak memory | 237856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738989761 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2738989761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.1114035064 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 380005845 ps |
| CPU time | 14.5 seconds |
| Started | Sep 01 11:15:31 PM UTC 24 |
| Finished | Sep 01 11:15:47 PM UTC 24 |
| Peak memory | 231804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114035064 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_to ken_digest.1114035064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.1438688739 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 784602717 ps |
| CPU time | 18.19 seconds |
| Started | Sep 01 11:15:29 PM UTC 24 |
| Finished | Sep 01 11:15:49 PM UTC 24 |
| Peak memory | 237656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438688739 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token _mux.1438688739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.1324996512 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 228007204 ps |
| CPU time | 11.54 seconds |
| Started | Sep 01 11:15:24 PM UTC 24 |
| Finished | Sep 01 11:15:37 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324996512 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1324996512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.3652410546 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 75314373 ps |
| CPU time | 4.43 seconds |
| Started | Sep 01 11:15:19 PM UTC 24 |
| Finished | Sep 01 11:15:24 PM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652410546 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3652410546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.1392840683 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 327369090 ps |
| CPU time | 32.38 seconds |
| Started | Sep 01 11:15:20 PM UTC 24 |
| Finished | Sep 01 11:15:54 PM UTC 24 |
| Peak memory | 258868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392840683 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1392840683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.3384945345 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 105942217 ps |
| CPU time | 11.78 seconds |
| Started | Sep 01 11:15:21 PM UTC 24 |
| Finished | Sep 01 11:15:34 PM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384945345 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3384945345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.4262516761 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 44053530275 ps |
| CPU time | 246.35 seconds |
| Started | Sep 01 11:15:31 PM UTC 24 |
| Finished | Sep 01 11:19:41 PM UTC 24 |
| Peak memory | 281072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4262516761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 19.lc_ctrl_stress_all.4262516761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2574242811 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 12859359 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 11:15:19 PM UTC 24 |
| Finished | Sep 01 11:15:21 PM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574242811 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19 .lc_ctrl_volatile_unlock_smoke.2574242811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.3304389163 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 13814673 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 11:09:50 PM UTC 24 |
| Finished | Sep 01 11:09:53 PM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304389163 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3304389163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.1584795779 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 17435712 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 11:09:20 PM UTC 24 |
| Finished | Sep 01 11:09:22 PM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584795779 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1584795779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1228170304 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 596051563 ps |
| CPU time | 29.39 seconds |
| Started | Sep 01 11:09:17 PM UTC 24 |
| Finished | Sep 01 11:09:48 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228170304 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1228170304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.457609365 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 438934424 ps |
| CPU time | 15.43 seconds |
| Started | Sep 01 11:09:32 PM UTC 24 |
| Finished | Sep 01 11:09:49 PM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457609365 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.457609365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.3943660532 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2209318389 ps |
| CPU time | 38.83 seconds |
| Started | Sep 01 11:09:29 PM UTC 24 |
| Finished | Sep 01 11:10:09 PM UTC 24 |
| Peak memory | 237592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943660532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jt ag_errors.3943660532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.2598238028 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1347076169 ps |
| CPU time | 10.22 seconds |
| Started | Sep 01 11:09:33 PM UTC 24 |
| Finished | Sep 01 11:09:45 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598238028 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_prior ity.2598238028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.223152787 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 360857706 ps |
| CPU time | 11.27 seconds |
| Started | Sep 01 11:09:27 PM UTC 24 |
| Finished | Sep 01 11:09:39 PM UTC 24 |
| Peak memory | 235912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223152787 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_prog_failure.223152787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1193290262 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1079767213 ps |
| CPU time | 35.72 seconds |
| Started | Sep 01 11:09:33 PM UTC 24 |
| Finished | Sep 01 11:10:11 PM UTC 24 |
| Peak memory | 229496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193290262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ ctrl_jtag_regwen_during_op.1193290262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.528567965 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 170283486 ps |
| CPU time | 2.35 seconds |
| Started | Sep 01 11:09:22 PM UTC 24 |
| Finished | Sep 01 11:09:26 PM UTC 24 |
| Peak memory | 229484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528567965 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_sm oke.528567965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.2940933650 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 7269250736 ps |
| CPU time | 47.35 seconds |
| Started | Sep 01 11:09:23 PM UTC 24 |
| Finished | Sep 01 11:10:12 PM UTC 24 |
| Peak memory | 280936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940933650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr l_jtag_state_failure.2940933650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1723781963 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 675436680 ps |
| CPU time | 10.2 seconds |
| Started | Sep 01 11:09:25 PM UTC 24 |
| Finished | Sep 01 11:09:36 PM UTC 24 |
| Peak memory | 236320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723781963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ ctrl_jtag_state_post_trans.1723781963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.687160376 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 156588573 ps |
| CPU time | 3.28 seconds |
| Started | Sep 01 11:09:17 PM UTC 24 |
| Finished | Sep 01 11:09:21 PM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687160376 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.687160376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.366924854 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 344631603 ps |
| CPU time | 23.3 seconds |
| Started | Sep 01 11:09:18 PM UTC 24 |
| Finished | Sep 01 11:09:43 PM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366924854 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.366924854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.425065886 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 419010307 ps |
| CPU time | 43.42 seconds |
| Started | Sep 01 11:09:49 PM UTC 24 |
| Finished | Sep 01 11:10:34 PM UTC 24 |
| Peak memory | 290080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425065886 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.425065886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.1140596036 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 760699718 ps |
| CPU time | 18.51 seconds |
| Started | Sep 01 11:09:37 PM UTC 24 |
| Finished | Sep 01 11:09:56 PM UTC 24 |
| Peak memory | 237992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140596036 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1140596036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3261875710 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 287475641 ps |
| CPU time | 13.19 seconds |
| Started | Sep 01 11:09:40 PM UTC 24 |
| Finished | Sep 01 11:09:54 PM UTC 24 |
| Peak memory | 229828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261875710 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_tok en_digest.3261875710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.963311329 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 971090323 ps |
| CPU time | 16.02 seconds |
| Started | Sep 01 11:09:37 PM UTC 24 |
| Finished | Sep 01 11:09:54 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963311329 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.963311329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1790257880 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 222618816 ps |
| CPU time | 13.99 seconds |
| Started | Sep 01 11:09:17 PM UTC 24 |
| Finished | Sep 01 11:09:32 PM UTC 24 |
| Peak memory | 237704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790257880 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1790257880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.2220896418 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 355883911 ps |
| CPU time | 4.35 seconds |
| Started | Sep 01 11:09:14 PM UTC 24 |
| Finished | Sep 01 11:09:20 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220896418 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2220896418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.3412487334 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 88355026 ps |
| CPU time | 14 seconds |
| Started | Sep 01 11:09:17 PM UTC 24 |
| Finished | Sep 01 11:09:32 PM UTC 24 |
| Peak memory | 262588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412487334 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3412487334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.511484279 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 7085917649 ps |
| CPU time | 209.06 seconds |
| Started | Sep 01 11:09:44 PM UTC 24 |
| Finished | Sep 01 11:13:16 PM UTC 24 |
| Peak memory | 289248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=511484279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 2.lc_ctrl_stress_all.511484279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.675733351 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14585698 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 11:09:15 PM UTC 24 |
| Finished | Sep 01 11:09:17 PM UTC 24 |
| Peak memory | 222380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675733351 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.l c_ctrl_volatile_unlock_smoke.675733351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.4007160498 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 294968158 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 11:15:48 PM UTC 24 |
| Finished | Sep 01 11:15:51 PM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007160498 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.4007160498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.2002039422 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 451753572 ps |
| CPU time | 16.14 seconds |
| Started | Sep 01 11:15:41 PM UTC 24 |
| Finished | Sep 01 11:15:58 PM UTC 24 |
| Peak memory | 232216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002039422 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2002039422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.1847054766 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1687841913 ps |
| CPU time | 7.37 seconds |
| Started | Sep 01 11:15:42 PM UTC 24 |
| Finished | Sep 01 11:15:51 PM UTC 24 |
| Peak memory | 229616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847054766 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1847054766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.3570486491 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 65054947 ps |
| CPU time | 2.29 seconds |
| Started | Sep 01 11:15:39 PM UTC 24 |
| Finished | Sep 01 11:15:43 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570486491 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3570486491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.2510851562 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 1489276240 ps |
| CPU time | 18.69 seconds |
| Started | Sep 01 11:15:42 PM UTC 24 |
| Finished | Sep 01 11:16:02 PM UTC 24 |
| Peak memory | 232208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510851562 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2510851562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.2819479684 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 824370007 ps |
| CPU time | 12.38 seconds |
| Started | Sep 01 11:15:43 PM UTC 24 |
| Finished | Sep 01 11:15:57 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819479684 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_to ken_digest.2819479684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.1736421842 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 219812455 ps |
| CPU time | 12.99 seconds |
| Started | Sep 01 11:15:42 PM UTC 24 |
| Finished | Sep 01 11:15:57 PM UTC 24 |
| Peak memory | 237768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736421842 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token _mux.1736421842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.2211940319 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3205734515 ps |
| CPU time | 10.67 seconds |
| Started | Sep 01 11:15:41 PM UTC 24 |
| Finished | Sep 01 11:15:53 PM UTC 24 |
| Peak memory | 232348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211940319 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2211940319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.3770113039 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 197352921 ps |
| CPU time | 2.88 seconds |
| Started | Sep 01 11:15:35 PM UTC 24 |
| Finished | Sep 01 11:15:40 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770113039 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3770113039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.2074238335 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 217808516 ps |
| CPU time | 32.62 seconds |
| Started | Sep 01 11:15:38 PM UTC 24 |
| Finished | Sep 01 11:16:12 PM UTC 24 |
| Peak memory | 262644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074238335 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2074238335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.2495070955 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 128275085 ps |
| CPU time | 12.3 seconds |
| Started | Sep 01 11:15:39 PM UTC 24 |
| Finished | Sep 01 11:15:53 PM UTC 24 |
| Peak memory | 262832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495070955 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2495070955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.619743763 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 9156001267 ps |
| CPU time | 342.61 seconds |
| Started | Sep 01 11:15:44 PM UTC 24 |
| Finished | Sep 01 11:21:32 PM UTC 24 |
| Peak memory | 289388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=619743763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 20.lc_ctrl_stress_all.619743763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.405109950 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 13450146 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 11:15:36 PM UTC 24 |
| Finished | Sep 01 11:15:39 PM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405109950 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20. lc_ctrl_volatile_unlock_smoke.405109950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.227938114 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 22664702 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 11:15:55 PM UTC 24 |
| Finished | Sep 01 11:15:57 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227938114 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.227938114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.554417770 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 618956716 ps |
| CPU time | 13.89 seconds |
| Started | Sep 01 11:15:51 PM UTC 24 |
| Finished | Sep 01 11:16:06 PM UTC 24 |
| Peak memory | 237724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554417770 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.554417770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.1989439835 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1129626855 ps |
| CPU time | 26.87 seconds |
| Started | Sep 01 11:15:52 PM UTC 24 |
| Finished | Sep 01 11:16:21 PM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989439835 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1989439835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.1920606905 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 68797706 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 11:15:50 PM UTC 24 |
| Finished | Sep 01 11:15:53 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920606905 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1920606905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.3985295332 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1726167331 ps |
| CPU time | 13.45 seconds |
| Started | Sep 01 11:15:52 PM UTC 24 |
| Finished | Sep 01 11:16:07 PM UTC 24 |
| Peak memory | 232272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985295332 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3985295332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.2584201984 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 721074803 ps |
| CPU time | 20.2 seconds |
| Started | Sep 01 11:15:55 PM UTC 24 |
| Finished | Sep 01 11:16:16 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584201984 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_to ken_digest.2584201984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.2491404950 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1306602103 ps |
| CPU time | 15.11 seconds |
| Started | Sep 01 11:15:53 PM UTC 24 |
| Finished | Sep 01 11:16:10 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491404950 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token _mux.2491404950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.3567378927 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 968173643 ps |
| CPU time | 8.9 seconds |
| Started | Sep 01 11:15:51 PM UTC 24 |
| Finished | Sep 01 11:16:01 PM UTC 24 |
| Peak memory | 237932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567378927 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3567378927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.3146682556 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 214228019 ps |
| CPU time | 6.92 seconds |
| Started | Sep 01 11:15:48 PM UTC 24 |
| Finished | Sep 01 11:15:56 PM UTC 24 |
| Peak memory | 229564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146682556 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3146682556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.3515788306 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1101648365 ps |
| CPU time | 28.34 seconds |
| Started | Sep 01 11:15:49 PM UTC 24 |
| Finished | Sep 01 11:16:18 PM UTC 24 |
| Peak memory | 262196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515788306 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3515788306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.3386909354 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 582434231 ps |
| CPU time | 4.01 seconds |
| Started | Sep 01 11:15:49 PM UTC 24 |
| Finished | Sep 01 11:15:54 PM UTC 24 |
| Peak memory | 234280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386909354 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3386909354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.2751094747 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 17604696615 ps |
| CPU time | 191.55 seconds |
| Started | Sep 01 11:15:55 PM UTC 24 |
| Finished | Sep 01 11:19:09 PM UTC 24 |
| Peak memory | 432876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2751094747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 21.lc_ctrl_stress_all.2751094747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.12651185 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 9944039882 ps |
| CPU time | 128.44 seconds |
| Started | Sep 01 11:15:55 PM UTC 24 |
| Finished | Sep 01 11:18:06 PM UTC 24 |
| Peak memory | 283192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12651185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SE Q=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unl ock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.12651185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1995383438 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 32610352 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 11:15:48 PM UTC 24 |
| Finished | Sep 01 11:15:51 PM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995383438 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21 .lc_ctrl_volatile_unlock_smoke.1995383438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.503795343 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 43450867 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 11:16:08 PM UTC 24 |
| Finished | Sep 01 11:16:10 PM UTC 24 |
| Peak memory | 216656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503795343 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.503795343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.2193090740 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 333744560 ps |
| CPU time | 14.01 seconds |
| Started | Sep 01 11:15:59 PM UTC 24 |
| Finished | Sep 01 11:16:14 PM UTC 24 |
| Peak memory | 231892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193090740 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2193090740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.1054551226 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 133897467 ps |
| CPU time | 5.82 seconds |
| Started | Sep 01 11:16:01 PM UTC 24 |
| Finished | Sep 01 11:16:08 PM UTC 24 |
| Peak memory | 229504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054551226 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1054551226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.50691109 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 27039806 ps |
| CPU time | 2.63 seconds |
| Started | Sep 01 11:15:58 PM UTC 24 |
| Finished | Sep 01 11:16:01 PM UTC 24 |
| Peak memory | 232088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50691109 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.50691109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.3243050316 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 263973662 ps |
| CPU time | 17.63 seconds |
| Started | Sep 01 11:16:02 PM UTC 24 |
| Finished | Sep 01 11:16:21 PM UTC 24 |
| Peak memory | 237588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243050316 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3243050316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.2184190240 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 261329977 ps |
| CPU time | 14.53 seconds |
| Started | Sep 01 11:16:02 PM UTC 24 |
| Finished | Sep 01 11:16:18 PM UTC 24 |
| Peak memory | 231816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184190240 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_to ken_digest.2184190240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.4119974077 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 671798580 ps |
| CPU time | 15.38 seconds |
| Started | Sep 01 11:16:02 PM UTC 24 |
| Finished | Sep 01 11:16:19 PM UTC 24 |
| Peak memory | 232024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119974077 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token _mux.4119974077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.3240652568 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 347357238 ps |
| CPU time | 11.23 seconds |
| Started | Sep 01 11:16:00 PM UTC 24 |
| Finished | Sep 01 11:16:12 PM UTC 24 |
| Peak memory | 231888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240652568 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3240652568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.3362505857 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 326321258 ps |
| CPU time | 3.73 seconds |
| Started | Sep 01 11:15:56 PM UTC 24 |
| Finished | Sep 01 11:16:01 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362505857 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3362505857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.1722223193 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1293740585 ps |
| CPU time | 34.62 seconds |
| Started | Sep 01 11:15:57 PM UTC 24 |
| Finished | Sep 01 11:16:34 PM UTC 24 |
| Peak memory | 262720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722223193 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1722223193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.1624420402 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 220603992 ps |
| CPU time | 12.98 seconds |
| Started | Sep 01 11:15:57 PM UTC 24 |
| Finished | Sep 01 11:16:12 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624420402 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1624420402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.1853868323 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 2794780699 ps |
| CPU time | 89.9 seconds |
| Started | Sep 01 11:16:03 PM UTC 24 |
| Finished | Sep 01 11:17:35 PM UTC 24 |
| Peak memory | 262568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1853868323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 22.lc_ctrl_stress_all.1853868323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1513833238 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 16240862625 ps |
| CPU time | 112.54 seconds |
| Started | Sep 01 11:16:08 PM UTC 24 |
| Finished | Sep 01 11:18:02 PM UTC 24 |
| Peak memory | 272924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513833238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.1513833238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2836894965 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 42556350 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 11:15:57 PM UTC 24 |
| Finished | Sep 01 11:16:00 PM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836894965 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22 .lc_ctrl_volatile_unlock_smoke.2836894965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.3795082621 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 23775018 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 11:16:19 PM UTC 24 |
| Finished | Sep 01 11:16:22 PM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795082621 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3795082621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.3084651899 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 756691471 ps |
| CPU time | 13.49 seconds |
| Started | Sep 01 11:16:13 PM UTC 24 |
| Finished | Sep 01 11:16:28 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084651899 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3084651899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.1310417121 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 290283850 ps |
| CPU time | 2.84 seconds |
| Started | Sep 01 11:16:15 PM UTC 24 |
| Finished | Sep 01 11:16:18 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310417121 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1310417121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.3310352622 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 369139384 ps |
| CPU time | 5.76 seconds |
| Started | Sep 01 11:16:13 PM UTC 24 |
| Finished | Sep 01 11:16:20 PM UTC 24 |
| Peak memory | 232276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310352622 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3310352622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.951294549 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 658566935 ps |
| CPU time | 19.52 seconds |
| Started | Sep 01 11:16:15 PM UTC 24 |
| Finished | Sep 01 11:16:35 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951294549 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.951294549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.1710533358 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 970685416 ps |
| CPU time | 13.69 seconds |
| Started | Sep 01 11:16:19 PM UTC 24 |
| Finished | Sep 01 11:16:34 PM UTC 24 |
| Peak memory | 237848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710533358 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_to ken_digest.1710533358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.2724990559 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 615925003 ps |
| CPU time | 14.86 seconds |
| Started | Sep 01 11:16:17 PM UTC 24 |
| Finished | Sep 01 11:16:33 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724990559 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token _mux.2724990559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.3179304452 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1003552679 ps |
| CPU time | 7.61 seconds |
| Started | Sep 01 11:16:13 PM UTC 24 |
| Finished | Sep 01 11:16:22 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179304452 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3179304452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.440992252 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 14926548 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 11:16:09 PM UTC 24 |
| Finished | Sep 01 11:16:11 PM UTC 24 |
| Peak memory | 218612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440992252 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.440992252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.2334712419 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1058321139 ps |
| CPU time | 37.56 seconds |
| Started | Sep 01 11:16:11 PM UTC 24 |
| Finished | Sep 01 11:16:50 PM UTC 24 |
| Peak memory | 258796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334712419 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2334712419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.2777170683 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 127286058 ps |
| CPU time | 13.6 seconds |
| Started | Sep 01 11:16:12 PM UTC 24 |
| Finished | Sep 01 11:16:27 PM UTC 24 |
| Peak memory | 262588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777170683 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2777170683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.3547136377 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 13833771269 ps |
| CPU time | 144.6 seconds |
| Started | Sep 01 11:16:19 PM UTC 24 |
| Finished | Sep 01 11:18:46 PM UTC 24 |
| Peak memory | 281328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3547136377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 23.lc_ctrl_stress_all.3547136377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1207318589 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 15089385 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 11:16:11 PM UTC 24 |
| Finished | Sep 01 11:16:14 PM UTC 24 |
| Peak memory | 222384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207318589 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23 .lc_ctrl_volatile_unlock_smoke.1207318589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.3664643872 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 16734922 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 11:16:28 PM UTC 24 |
| Finished | Sep 01 11:16:31 PM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664643872 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3664643872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.112881570 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 5189054855 ps |
| CPU time | 11.29 seconds |
| Started | Sep 01 11:16:23 PM UTC 24 |
| Finished | Sep 01 11:16:36 PM UTC 24 |
| Peak memory | 237740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112881570 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.112881570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.1730459809 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 400754145 ps |
| CPU time | 4.81 seconds |
| Started | Sep 01 11:16:23 PM UTC 24 |
| Finished | Sep 01 11:16:29 PM UTC 24 |
| Peak memory | 229824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730459809 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1730459809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.3099954067 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 94568843 ps |
| CPU time | 3.31 seconds |
| Started | Sep 01 11:16:22 PM UTC 24 |
| Finished | Sep 01 11:16:26 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099954067 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3099954067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.763330251 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 296733430 ps |
| CPU time | 17.91 seconds |
| Started | Sep 01 11:16:25 PM UTC 24 |
| Finished | Sep 01 11:16:44 PM UTC 24 |
| Peak memory | 237656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763330251 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.763330251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.1650165840 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2641099450 ps |
| CPU time | 23.57 seconds |
| Started | Sep 01 11:16:27 PM UTC 24 |
| Finished | Sep 01 11:16:52 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650165840 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_to ken_digest.1650165840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.2373291272 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 163274297 ps |
| CPU time | 8.73 seconds |
| Started | Sep 01 11:16:26 PM UTC 24 |
| Finished | Sep 01 11:16:36 PM UTC 24 |
| Peak memory | 237160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373291272 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token _mux.2373291272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.4211984209 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1420557180 ps |
| CPU time | 13.05 seconds |
| Started | Sep 01 11:16:23 PM UTC 24 |
| Finished | Sep 01 11:16:38 PM UTC 24 |
| Peak memory | 236980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211984209 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.4211984209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.3255309242 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 53695818 ps |
| CPU time | 4.05 seconds |
| Started | Sep 01 11:16:21 PM UTC 24 |
| Finished | Sep 01 11:16:26 PM UTC 24 |
| Peak memory | 225276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255309242 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3255309242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.1358747384 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1455438180 ps |
| CPU time | 23.23 seconds |
| Started | Sep 01 11:16:21 PM UTC 24 |
| Finished | Sep 01 11:16:45 PM UTC 24 |
| Peak memory | 262512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358747384 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1358747384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.2468013400 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 60050307 ps |
| CPU time | 15.02 seconds |
| Started | Sep 01 11:16:22 PM UTC 24 |
| Finished | Sep 01 11:16:38 PM UTC 24 |
| Peak memory | 262576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468013400 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2468013400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.660929588 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 10290349390 ps |
| CPU time | 355.64 seconds |
| Started | Sep 01 11:16:27 PM UTC 24 |
| Finished | Sep 01 11:22:28 PM UTC 24 |
| Peak memory | 289260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=660929588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 24.lc_ctrl_stress_all.660929588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3054050010 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 7095822814 ps |
| CPU time | 73.04 seconds |
| Started | Sep 01 11:16:28 PM UTC 24 |
| Finished | Sep 01 11:17:43 PM UTC 24 |
| Peak memory | 262768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054050010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3054050010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.925993651 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 129725169 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 11:16:21 PM UTC 24 |
| Finished | Sep 01 11:16:23 PM UTC 24 |
| Peak memory | 218544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925993651 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24. lc_ctrl_volatile_unlock_smoke.925993651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.3525617787 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 24817130 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 11:16:37 PM UTC 24 |
| Finished | Sep 01 11:16:40 PM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525617787 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3525617787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.1035078361 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 255547352 ps |
| CPU time | 17.31 seconds |
| Started | Sep 01 11:16:33 PM UTC 24 |
| Finished | Sep 01 11:16:52 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035078361 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1035078361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.2512805914 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 426034196 ps |
| CPU time | 14.43 seconds |
| Started | Sep 01 11:16:33 PM UTC 24 |
| Finished | Sep 01 11:16:49 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512805914 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2512805914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.305176018 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 372341669 ps |
| CPU time | 6.11 seconds |
| Started | Sep 01 11:16:32 PM UTC 24 |
| Finished | Sep 01 11:16:39 PM UTC 24 |
| Peak memory | 235980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305176018 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.305176018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.3934516628 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 1588853515 ps |
| CPU time | 9.11 seconds |
| Started | Sep 01 11:16:35 PM UTC 24 |
| Finished | Sep 01 11:16:45 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934516628 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3934516628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.1805744977 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 364806603 ps |
| CPU time | 15.49 seconds |
| Started | Sep 01 11:16:36 PM UTC 24 |
| Finished | Sep 01 11:16:53 PM UTC 24 |
| Peak memory | 231812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805744977 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_to ken_digest.1805744977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.3894464276 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 316968320 ps |
| CPU time | 15.27 seconds |
| Started | Sep 01 11:16:35 PM UTC 24 |
| Finished | Sep 01 11:16:51 PM UTC 24 |
| Peak memory | 231948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894464276 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token _mux.3894464276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.3980515150 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 871031363 ps |
| CPU time | 14.87 seconds |
| Started | Sep 01 11:16:33 PM UTC 24 |
| Finished | Sep 01 11:16:49 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980515150 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.3980515150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.2690313526 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 122028337 ps |
| CPU time | 3.79 seconds |
| Started | Sep 01 11:16:28 PM UTC 24 |
| Finished | Sep 01 11:16:33 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690313526 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2690313526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.1882368186 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 763765084 ps |
| CPU time | 23.66 seconds |
| Started | Sep 01 11:16:31 PM UTC 24 |
| Finished | Sep 01 11:16:56 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882368186 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1882368186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.655682502 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 73164675 ps |
| CPU time | 9.09 seconds |
| Started | Sep 01 11:16:31 PM UTC 24 |
| Finished | Sep 01 11:16:41 PM UTC 24 |
| Peak memory | 262480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655682502 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.655682502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.4237478411 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 14590522224 ps |
| CPU time | 110.88 seconds |
| Started | Sep 01 11:16:36 PM UTC 24 |
| Finished | Sep 01 11:18:29 PM UTC 24 |
| Peak memory | 293280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4237478411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 25.lc_ctrl_stress_all.4237478411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3968217933 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 4489016293 ps |
| CPU time | 63.13 seconds |
| Started | Sep 01 11:16:36 PM UTC 24 |
| Finished | Sep 01 11:17:41 PM UTC 24 |
| Peak memory | 262688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968217933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.3968217933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1191155432 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 12985405 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 11:16:30 PM UTC 24 |
| Finished | Sep 01 11:16:32 PM UTC 24 |
| Peak memory | 218712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191155432 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25 .lc_ctrl_volatile_unlock_smoke.1191155432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.1498409844 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 39114735 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 11:16:48 PM UTC 24 |
| Finished | Sep 01 11:16:51 PM UTC 24 |
| Peak memory | 218464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498409844 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1498409844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.4011724086 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1023352359 ps |
| CPU time | 9.71 seconds |
| Started | Sep 01 11:16:42 PM UTC 24 |
| Finished | Sep 01 11:16:53 PM UTC 24 |
| Peak memory | 237668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011724086 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.4011724086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.1884117816 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 172632264 ps |
| CPU time | 4.22 seconds |
| Started | Sep 01 11:16:42 PM UTC 24 |
| Finished | Sep 01 11:16:47 PM UTC 24 |
| Peak memory | 229860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884117816 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1884117816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.4279574684 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 86902616 ps |
| CPU time | 2.86 seconds |
| Started | Sep 01 11:16:41 PM UTC 24 |
| Finished | Sep 01 11:16:45 PM UTC 24 |
| Peak memory | 234260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279574684 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.4279574684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.321591678 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 3117334074 ps |
| CPU time | 15.36 seconds |
| Started | Sep 01 11:16:45 PM UTC 24 |
| Finished | Sep 01 11:17:01 PM UTC 24 |
| Peak memory | 237648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321591678 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.321591678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.2403290847 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 260360364 ps |
| CPU time | 8.67 seconds |
| Started | Sep 01 11:16:46 PM UTC 24 |
| Finished | Sep 01 11:16:56 PM UTC 24 |
| Peak memory | 237588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403290847 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_to ken_digest.2403290847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.602494876 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 197430666 ps |
| CPU time | 10.38 seconds |
| Started | Sep 01 11:16:45 PM UTC 24 |
| Finished | Sep 01 11:16:56 PM UTC 24 |
| Peak memory | 237596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602494876 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_ mux.602494876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.1818619832 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 616236544 ps |
| CPU time | 14.04 seconds |
| Started | Sep 01 11:16:42 PM UTC 24 |
| Finished | Sep 01 11:16:57 PM UTC 24 |
| Peak memory | 231980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818619832 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1818619832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.3270748593 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 76284855 ps |
| CPU time | 2.57 seconds |
| Started | Sep 01 11:16:37 PM UTC 24 |
| Finished | Sep 01 11:16:41 PM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270748593 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3270748593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.1505995460 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 1007546880 ps |
| CPU time | 44.7 seconds |
| Started | Sep 01 11:16:40 PM UTC 24 |
| Finished | Sep 01 11:17:26 PM UTC 24 |
| Peak memory | 262496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505995460 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1505995460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.3286322560 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 224750105 ps |
| CPU time | 5.21 seconds |
| Started | Sep 01 11:16:41 PM UTC 24 |
| Finished | Sep 01 11:16:47 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286322560 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3286322560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.604562737 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 6159078555 ps |
| CPU time | 118.09 seconds |
| Started | Sep 01 11:16:46 PM UTC 24 |
| Finished | Sep 01 11:18:46 PM UTC 24 |
| Peak memory | 280988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=604562737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 26.lc_ctrl_stress_all.604562737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.644459740 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 12583893 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 11:16:38 PM UTC 24 |
| Finished | Sep 01 11:16:41 PM UTC 24 |
| Peak memory | 220328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644459740 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26. lc_ctrl_volatile_unlock_smoke.644459740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.2727844333 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 71099069 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 11:16:57 PM UTC 24 |
| Finished | Sep 01 11:17:00 PM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727844333 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2727844333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_errors.1618671275 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 196107286 ps |
| CPU time | 14.82 seconds |
| Started | Sep 01 11:16:52 PM UTC 24 |
| Finished | Sep 01 11:17:08 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618671275 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1618671275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.1027033889 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 1760041685 ps |
| CPU time | 8.05 seconds |
| Started | Sep 01 11:16:52 PM UTC 24 |
| Finished | Sep 01 11:17:01 PM UTC 24 |
| Peak memory | 229796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027033889 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1027033889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.4249420923 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 665432345 ps |
| CPU time | 4.76 seconds |
| Started | Sep 01 11:16:51 PM UTC 24 |
| Finished | Sep 01 11:16:57 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249420923 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.4249420923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.2799687888 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 182992944 ps |
| CPU time | 12.88 seconds |
| Started | Sep 01 11:16:54 PM UTC 24 |
| Finished | Sep 01 11:17:08 PM UTC 24 |
| Peak memory | 237384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799687888 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2799687888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.95356720 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1761751159 ps |
| CPU time | 16.04 seconds |
| Started | Sep 01 11:16:54 PM UTC 24 |
| Finished | Sep 01 11:17:11 PM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95356720 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_toke n_digest.95356720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.3513801878 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1172481423 ps |
| CPU time | 11.65 seconds |
| Started | Sep 01 11:16:54 PM UTC 24 |
| Finished | Sep 01 11:17:06 PM UTC 24 |
| Peak memory | 229612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513801878 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token _mux.3513801878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.3304492915 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 810217454 ps |
| CPU time | 19.13 seconds |
| Started | Sep 01 11:16:52 PM UTC 24 |
| Finished | Sep 01 11:17:12 PM UTC 24 |
| Peak memory | 237592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304492915 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3304492915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.1787236602 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 256034339 ps |
| CPU time | 3.9 seconds |
| Started | Sep 01 11:16:48 PM UTC 24 |
| Finished | Sep 01 11:16:53 PM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787236602 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1787236602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.2542207114 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 422468952 ps |
| CPU time | 33.72 seconds |
| Started | Sep 01 11:16:50 PM UTC 24 |
| Finished | Sep 01 11:17:25 PM UTC 24 |
| Peak memory | 262576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542207114 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2542207114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.2525891746 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 66611411 ps |
| CPU time | 19.27 seconds |
| Started | Sep 01 11:16:51 PM UTC 24 |
| Finished | Sep 01 11:17:11 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525891746 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2525891746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.2397609405 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 17416913845 ps |
| CPU time | 349.05 seconds |
| Started | Sep 01 11:16:54 PM UTC 24 |
| Finished | Sep 01 11:22:48 PM UTC 24 |
| Peak memory | 432880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2397609405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 27.lc_ctrl_stress_all.2397609405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3483909825 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 11440424 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 11:16:48 PM UTC 24 |
| Finished | Sep 01 11:16:51 PM UTC 24 |
| Peak memory | 218560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483909825 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27 .lc_ctrl_volatile_unlock_smoke.3483909825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.596767820 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 27726369 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 11:17:09 PM UTC 24 |
| Finished | Sep 01 11:17:11 PM UTC 24 |
| Peak memory | 218884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596767820 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.596767820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.4116561155 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1176928202 ps |
| CPU time | 15.88 seconds |
| Started | Sep 01 11:17:01 PM UTC 24 |
| Finished | Sep 01 11:17:18 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116561155 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.4116561155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.720333408 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1693882835 ps |
| CPU time | 9.59 seconds |
| Started | Sep 01 11:17:02 PM UTC 24 |
| Finished | Sep 01 11:17:13 PM UTC 24 |
| Peak memory | 229528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720333408 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.720333408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.3061802609 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 131343661 ps |
| CPU time | 4.25 seconds |
| Started | Sep 01 11:16:59 PM UTC 24 |
| Finished | Sep 01 11:17:04 PM UTC 24 |
| Peak memory | 236296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061802609 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3061802609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.3490633888 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 210247025 ps |
| CPU time | 12.55 seconds |
| Started | Sep 01 11:17:02 PM UTC 24 |
| Finished | Sep 01 11:17:16 PM UTC 24 |
| Peak memory | 237664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490633888 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3490633888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.3957544477 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 349458973 ps |
| CPU time | 17.11 seconds |
| Started | Sep 01 11:17:05 PM UTC 24 |
| Finished | Sep 01 11:17:24 PM UTC 24 |
| Peak memory | 232008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957544477 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_to ken_digest.3957544477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.3366141648 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 905048433 ps |
| CPU time | 18.02 seconds |
| Started | Sep 01 11:17:04 PM UTC 24 |
| Finished | Sep 01 11:17:23 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366141648 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token _mux.3366141648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.3254311209 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 3408792832 ps |
| CPU time | 11.36 seconds |
| Started | Sep 01 11:17:01 PM UTC 24 |
| Finished | Sep 01 11:17:13 PM UTC 24 |
| Peak memory | 232024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254311209 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3254311209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.2255140054 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 111802197 ps |
| CPU time | 5 seconds |
| Started | Sep 01 11:16:57 PM UTC 24 |
| Finished | Sep 01 11:17:03 PM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255140054 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2255140054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.3448915985 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 465202233 ps |
| CPU time | 32.21 seconds |
| Started | Sep 01 11:16:57 PM UTC 24 |
| Finished | Sep 01 11:17:31 PM UTC 24 |
| Peak memory | 258496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448915985 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3448915985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.1321172668 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 172188110 ps |
| CPU time | 12.49 seconds |
| Started | Sep 01 11:16:59 PM UTC 24 |
| Finished | Sep 01 11:17:12 PM UTC 24 |
| Peak memory | 256360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321172668 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1321172668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.3545693680 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 7228520459 ps |
| CPU time | 60.34 seconds |
| Started | Sep 01 11:17:07 PM UTC 24 |
| Finished | Sep 01 11:18:10 PM UTC 24 |
| Peak memory | 237712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3545693680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 28.lc_ctrl_stress_all.3545693680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.645870541 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 6686793112 ps |
| CPU time | 91.74 seconds |
| Started | Sep 01 11:17:09 PM UTC 24 |
| Finished | Sep 01 11:18:42 PM UTC 24 |
| Peak memory | 285248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645870541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.645870541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1861637274 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 45345640 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 11:16:57 PM UTC 24 |
| Finished | Sep 01 11:17:00 PM UTC 24 |
| Peak memory | 218356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861637274 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28 .lc_ctrl_volatile_unlock_smoke.1861637274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.3627601234 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 38335232 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 11:17:20 PM UTC 24 |
| Finished | Sep 01 11:17:23 PM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627601234 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3627601234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.1104694805 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 1188847547 ps |
| CPU time | 9.39 seconds |
| Started | Sep 01 11:17:14 PM UTC 24 |
| Finished | Sep 01 11:17:25 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104694805 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1104694805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.314364218 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 142568811 ps |
| CPU time | 3.06 seconds |
| Started | Sep 01 11:17:16 PM UTC 24 |
| Finished | Sep 01 11:17:20 PM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314364218 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.314364218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.4185634033 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 21481684 ps |
| CPU time | 2.56 seconds |
| Started | Sep 01 11:17:13 PM UTC 24 |
| Finished | Sep 01 11:17:17 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185634033 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.4185634033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.354102098 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 225140497 ps |
| CPU time | 12.6 seconds |
| Started | Sep 01 11:17:17 PM UTC 24 |
| Finished | Sep 01 11:17:31 PM UTC 24 |
| Peak memory | 237660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354102098 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.354102098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.3259967049 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 971245194 ps |
| CPU time | 15.13 seconds |
| Started | Sep 01 11:17:18 PM UTC 24 |
| Finished | Sep 01 11:17:34 PM UTC 24 |
| Peak memory | 237492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259967049 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_to ken_digest.3259967049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.2854547371 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 295481586 ps |
| CPU time | 10.21 seconds |
| Started | Sep 01 11:17:18 PM UTC 24 |
| Finished | Sep 01 11:17:29 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854547371 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token _mux.2854547371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.3019747193 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1607595497 ps |
| CPU time | 15.15 seconds |
| Started | Sep 01 11:17:15 PM UTC 24 |
| Finished | Sep 01 11:17:31 PM UTC 24 |
| Peak memory | 231964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019747193 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3019747193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.8421736 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 55744967 ps |
| CPU time | 4.22 seconds |
| Started | Sep 01 11:17:12 PM UTC 24 |
| Finished | Sep 01 11:17:18 PM UTC 24 |
| Peak memory | 229636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8421736 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.8421736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.1394743706 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 1030141460 ps |
| CPU time | 46.26 seconds |
| Started | Sep 01 11:17:12 PM UTC 24 |
| Finished | Sep 01 11:18:00 PM UTC 24 |
| Peak memory | 262832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394743706 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1394743706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.2395219991 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 899027897 ps |
| CPU time | 10.46 seconds |
| Started | Sep 01 11:17:13 PM UTC 24 |
| Finished | Sep 01 11:17:25 PM UTC 24 |
| Peak memory | 256356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395219991 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2395219991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.2664737100 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 11111843763 ps |
| CPU time | 177.33 seconds |
| Started | Sep 01 11:17:19 PM UTC 24 |
| Finished | Sep 01 11:20:19 PM UTC 24 |
| Peak memory | 281072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2664737100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 29.lc_ctrl_stress_all.2664737100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.940604307 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 18149302 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 11:17:12 PM UTC 24 |
| Finished | Sep 01 11:17:15 PM UTC 24 |
| Peak memory | 218404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940604307 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29. lc_ctrl_volatile_unlock_smoke.940604307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.529689201 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 76394313 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 11:10:25 PM UTC 24 |
| Finished | Sep 01 11:10:28 PM UTC 24 |
| Peak memory | 218528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529689201 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.529689201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.1048645594 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 29661702 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 11:10:01 PM UTC 24 |
| Finished | Sep 01 11:10:04 PM UTC 24 |
| Peak memory | 217020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048645594 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1048645594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.2008616405 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 262633820 ps |
| CPU time | 16.25 seconds |
| Started | Sep 01 11:09:58 PM UTC 24 |
| Finished | Sep 01 11:10:15 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008616405 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2008616405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.2197498525 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 626921669 ps |
| CPU time | 3.47 seconds |
| Started | Sep 01 11:10:12 PM UTC 24 |
| Finished | Sep 01 11:10:16 PM UTC 24 |
| Peak memory | 229876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197498525 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2197498525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.108161576 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1847935165 ps |
| CPU time | 52.12 seconds |
| Started | Sep 01 11:10:10 PM UTC 24 |
| Finished | Sep 01 11:11:04 PM UTC 24 |
| Peak memory | 237860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108161576 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta g_errors.108161576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2242253346 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 799634758 ps |
| CPU time | 4.63 seconds |
| Started | Sep 01 11:10:13 PM UTC 24 |
| Finished | Sep 01 11:10:19 PM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242253346 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_prior ity.2242253346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1836635794 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 397896935 ps |
| CPU time | 7.96 seconds |
| Started | Sep 01 11:10:05 PM UTC 24 |
| Finished | Sep 01 11:10:14 PM UTC 24 |
| Peak memory | 235912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836635794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl _jtag_prog_failure.1836635794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1300886295 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2514919088 ps |
| CPU time | 39.97 seconds |
| Started | Sep 01 11:10:14 PM UTC 24 |
| Finished | Sep 01 11:10:56 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300886295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ ctrl_jtag_regwen_during_op.1300886295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.2588013048 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1060251627 ps |
| CPU time | 10.8 seconds |
| Started | Sep 01 11:10:01 PM UTC 24 |
| Finished | Sep 01 11:10:13 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588013048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_s moke.2588013048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.4277966067 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 13874512892 ps |
| CPU time | 80.06 seconds |
| Started | Sep 01 11:10:02 PM UTC 24 |
| Finished | Sep 01 11:11:24 PM UTC 24 |
| Peak memory | 287072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277966067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr l_jtag_state_failure.4277966067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.3028857174 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 362551782 ps |
| CPU time | 17.45 seconds |
| Started | Sep 01 11:10:03 PM UTC 24 |
| Finished | Sep 01 11:10:22 PM UTC 24 |
| Peak memory | 262460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028857174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ ctrl_jtag_state_post_trans.3028857174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1875219307 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 52917301 ps |
| CPU time | 3.9 seconds |
| Started | Sep 01 11:09:58 PM UTC 24 |
| Finished | Sep 01 11:10:02 PM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875219307 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1875219307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.3296695774 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 585961617 ps |
| CPU time | 27.23 seconds |
| Started | Sep 01 11:09:58 PM UTC 24 |
| Finished | Sep 01 11:10:26 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296695774 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3296695774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.2535579282 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 240639388 ps |
| CPU time | 31.83 seconds |
| Started | Sep 01 11:10:23 PM UTC 24 |
| Finished | Sep 01 11:10:56 PM UTC 24 |
| Peak memory | 298156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535579282 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2535579282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.139259773 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 422537843 ps |
| CPU time | 15.96 seconds |
| Started | Sep 01 11:10:14 PM UTC 24 |
| Finished | Sep 01 11:10:31 PM UTC 24 |
| Peak memory | 231944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139259773 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.139259773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.3633563785 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 906031557 ps |
| CPU time | 14.13 seconds |
| Started | Sep 01 11:10:16 PM UTC 24 |
| Finished | Sep 01 11:10:32 PM UTC 24 |
| Peak memory | 237516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633563785 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_tok en_digest.3633563785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3447997541 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1206119413 ps |
| CPU time | 13.9 seconds |
| Started | Sep 01 11:10:14 PM UTC 24 |
| Finished | Sep 01 11:10:29 PM UTC 24 |
| Peak memory | 231964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447997541 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_ mux.3447997541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.3567498173 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 434738613 ps |
| CPU time | 2.69 seconds |
| Started | Sep 01 11:09:53 PM UTC 24 |
| Finished | Sep 01 11:09:57 PM UTC 24 |
| Peak memory | 225784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567498173 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3567498173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2070524480 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 276054988 ps |
| CPU time | 39.47 seconds |
| Started | Sep 01 11:09:55 PM UTC 24 |
| Finished | Sep 01 11:10:35 PM UTC 24 |
| Peak memory | 258404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070524480 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2070524480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3580485278 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 53232525 ps |
| CPU time | 4.78 seconds |
| Started | Sep 01 11:09:55 PM UTC 24 |
| Finished | Sep 01 11:10:01 PM UTC 24 |
| Peak memory | 234276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580485278 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3580485278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.2717832871 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 38783602805 ps |
| CPU time | 393.72 seconds |
| Started | Sep 01 11:10:17 PM UTC 24 |
| Finished | Sep 01 11:16:57 PM UTC 24 |
| Peak memory | 262636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2717832871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 3.lc_ctrl_stress_all.2717832871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2755835333 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 13117040 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 11:09:55 PM UTC 24 |
| Finished | Sep 01 11:09:57 PM UTC 24 |
| Peak memory | 222380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755835333 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3. lc_ctrl_volatile_unlock_smoke.2755835333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.4293261364 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 17967890 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 11:17:30 PM UTC 24 |
| Finished | Sep 01 11:17:33 PM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293261364 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.4293261364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_errors.1644330916 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 4423426654 ps |
| CPU time | 20.38 seconds |
| Started | Sep 01 11:17:26 PM UTC 24 |
| Finished | Sep 01 11:17:48 PM UTC 24 |
| Peak memory | 237656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644330916 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1644330916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.2212845424 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 4602944846 ps |
| CPU time | 28.55 seconds |
| Started | Sep 01 11:17:27 PM UTC 24 |
| Finished | Sep 01 11:17:57 PM UTC 24 |
| Peak memory | 229612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212845424 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2212845424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.1366509921 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 76197128 ps |
| CPU time | 2.19 seconds |
| Started | Sep 01 11:17:26 PM UTC 24 |
| Finished | Sep 01 11:17:30 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366509921 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1366509921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.2950417510 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 322100712 ps |
| CPU time | 16.46 seconds |
| Started | Sep 01 11:17:28 PM UTC 24 |
| Finished | Sep 01 11:17:45 PM UTC 24 |
| Peak memory | 237732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950417510 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2950417510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.3492611986 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1473272798 ps |
| CPU time | 14.75 seconds |
| Started | Sep 01 11:17:28 PM UTC 24 |
| Finished | Sep 01 11:17:44 PM UTC 24 |
| Peak memory | 232008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492611986 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_to ken_digest.3492611986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.3567367165 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1365630008 ps |
| CPU time | 11.68 seconds |
| Started | Sep 01 11:17:28 PM UTC 24 |
| Finished | Sep 01 11:17:41 PM UTC 24 |
| Peak memory | 237784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567367165 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token _mux.3567367165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.2047986515 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 341016113 ps |
| CPU time | 12.65 seconds |
| Started | Sep 01 11:17:26 PM UTC 24 |
| Finished | Sep 01 11:17:40 PM UTC 24 |
| Peak memory | 237596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047986515 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2047986515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.68445358 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 34716777 ps |
| CPU time | 3.69 seconds |
| Started | Sep 01 11:17:21 PM UTC 24 |
| Finished | Sep 01 11:17:26 PM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68445358 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.68445358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.791039530 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 207246130 ps |
| CPU time | 39.8 seconds |
| Started | Sep 01 11:17:25 PM UTC 24 |
| Finished | Sep 01 11:18:06 PM UTC 24 |
| Peak memory | 262836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791039530 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.791039530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.3479391343 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 64807106 ps |
| CPU time | 8.54 seconds |
| Started | Sep 01 11:17:25 PM UTC 24 |
| Finished | Sep 01 11:17:35 PM UTC 24 |
| Peak memory | 262448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479391343 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3479391343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.2099887091 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 1020397961 ps |
| CPU time | 52.57 seconds |
| Started | Sep 01 11:17:29 PM UTC 24 |
| Finished | Sep 01 11:18:23 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2099887091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 30.lc_ctrl_stress_all.2099887091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2427708944 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 10936973 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 11:17:24 PM UTC 24 |
| Finished | Sep 01 11:17:26 PM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427708944 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30 .lc_ctrl_volatile_unlock_smoke.2427708944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.2155427979 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 25236154 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 11:17:42 PM UTC 24 |
| Finished | Sep 01 11:17:45 PM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155427979 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2155427979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.3139500307 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 385047356 ps |
| CPU time | 17.93 seconds |
| Started | Sep 01 11:17:34 PM UTC 24 |
| Finished | Sep 01 11:17:53 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139500307 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3139500307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.371107964 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 585445924 ps |
| CPU time | 7.47 seconds |
| Started | Sep 01 11:17:35 PM UTC 24 |
| Finished | Sep 01 11:17:44 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371107964 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.371107964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.2791374054 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 873510890 ps |
| CPU time | 4.3 seconds |
| Started | Sep 01 11:17:32 PM UTC 24 |
| Finished | Sep 01 11:17:37 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791374054 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2791374054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.2857427066 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 545076255 ps |
| CPU time | 14.44 seconds |
| Started | Sep 01 11:17:35 PM UTC 24 |
| Finished | Sep 01 11:17:51 PM UTC 24 |
| Peak memory | 237984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857427066 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2857427066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.2671743818 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 480861365 ps |
| CPU time | 15.97 seconds |
| Started | Sep 01 11:17:37 PM UTC 24 |
| Finished | Sep 01 11:17:54 PM UTC 24 |
| Peak memory | 237520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671743818 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_to ken_digest.2671743818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.933936724 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 604190079 ps |
| CPU time | 12.02 seconds |
| Started | Sep 01 11:17:35 PM UTC 24 |
| Finished | Sep 01 11:17:49 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933936724 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_ mux.933936724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.1764137034 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 1449740789 ps |
| CPU time | 16.31 seconds |
| Started | Sep 01 11:17:34 PM UTC 24 |
| Finished | Sep 01 11:17:51 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764137034 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1764137034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.2037742894 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 89477712 ps |
| CPU time | 2.4 seconds |
| Started | Sep 01 11:17:30 PM UTC 24 |
| Finished | Sep 01 11:17:34 PM UTC 24 |
| Peak memory | 223408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037742894 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2037742894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.2100551695 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 930337304 ps |
| CPU time | 28.15 seconds |
| Started | Sep 01 11:17:32 PM UTC 24 |
| Finished | Sep 01 11:18:01 PM UTC 24 |
| Peak memory | 262576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100551695 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2100551695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.391069654 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 210417940 ps |
| CPU time | 11.48 seconds |
| Started | Sep 01 11:17:32 PM UTC 24 |
| Finished | Sep 01 11:17:45 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391069654 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.391069654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.1583286304 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 2593330343 ps |
| CPU time | 108.55 seconds |
| Started | Sep 01 11:17:38 PM UTC 24 |
| Finished | Sep 01 11:19:29 PM UTC 24 |
| Peak memory | 285088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1583286304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 31.lc_ctrl_stress_all.1583286304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.391820631 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 2505871608 ps |
| CPU time | 88.41 seconds |
| Started | Sep 01 11:17:41 PM UTC 24 |
| Finished | Sep 01 11:19:11 PM UTC 24 |
| Peak memory | 262792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391820631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.391820631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3889174008 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 13486168 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 11:17:30 PM UTC 24 |
| Finished | Sep 01 11:17:33 PM UTC 24 |
| Peak memory | 218492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889174008 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31 .lc_ctrl_volatile_unlock_smoke.3889174008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.2965474658 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 44841125 ps |
| CPU time | 2.55 seconds |
| Started | Sep 01 11:17:53 PM UTC 24 |
| Finished | Sep 01 11:17:56 PM UTC 24 |
| Peak memory | 218792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965474658 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2965474658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_errors.3997843602 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 495974475 ps |
| CPU time | 9.82 seconds |
| Started | Sep 01 11:17:46 PM UTC 24 |
| Finished | Sep 01 11:17:57 PM UTC 24 |
| Peak memory | 230164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997843602 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3997843602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.1269810174 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 973724821 ps |
| CPU time | 19.05 seconds |
| Started | Sep 01 11:17:47 PM UTC 24 |
| Finished | Sep 01 11:18:08 PM UTC 24 |
| Peak memory | 229096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269810174 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1269810174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.2885729060 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 217079813 ps |
| CPU time | 4.37 seconds |
| Started | Sep 01 11:17:46 PM UTC 24 |
| Finished | Sep 01 11:17:51 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885729060 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2885729060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.2231653352 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 371100811 ps |
| CPU time | 16.44 seconds |
| Started | Sep 01 11:17:47 PM UTC 24 |
| Finished | Sep 01 11:18:05 PM UTC 24 |
| Peak memory | 237176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231653352 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2231653352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.646775530 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 394619732 ps |
| CPU time | 17.61 seconds |
| Started | Sep 01 11:17:49 PM UTC 24 |
| Finished | Sep 01 11:18:07 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646775530 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_tok en_digest.646775530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.3187798000 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 234687909 ps |
| CPU time | 7.4 seconds |
| Started | Sep 01 11:17:47 PM UTC 24 |
| Finished | Sep 01 11:17:56 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187798000 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token _mux.3187798000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.3092664505 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 1016685756 ps |
| CPU time | 11.82 seconds |
| Started | Sep 01 11:17:46 PM UTC 24 |
| Finished | Sep 01 11:17:59 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092664505 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3092664505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.3559977016 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 105771642 ps |
| CPU time | 3.49 seconds |
| Started | Sep 01 11:17:42 PM UTC 24 |
| Finished | Sep 01 11:17:47 PM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559977016 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3559977016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.882202371 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 700449361 ps |
| CPU time | 25.78 seconds |
| Started | Sep 01 11:17:45 PM UTC 24 |
| Finished | Sep 01 11:18:12 PM UTC 24 |
| Peak memory | 262960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882202371 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.882202371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.4054681307 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 329228776 ps |
| CPU time | 5.86 seconds |
| Started | Sep 01 11:17:45 PM UTC 24 |
| Finished | Sep 01 11:17:52 PM UTC 24 |
| Peak memory | 236308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054681307 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.4054681307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.3130867205 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 677956825 ps |
| CPU time | 67.39 seconds |
| Started | Sep 01 11:17:50 PM UTC 24 |
| Finished | Sep 01 11:18:59 PM UTC 24 |
| Peak memory | 262592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3130867205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 32.lc_ctrl_stress_all.3130867205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3716320144 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 13497095 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 11:17:45 PM UTC 24 |
| Finished | Sep 01 11:17:47 PM UTC 24 |
| Peak memory | 218176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716320144 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32 .lc_ctrl_volatile_unlock_smoke.3716320144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.2198435850 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 15839572 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 11:18:01 PM UTC 24 |
| Finished | Sep 01 11:18:04 PM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198435850 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2198435850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.2725184302 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 2053689366 ps |
| CPU time | 16.64 seconds |
| Started | Sep 01 11:17:55 PM UTC 24 |
| Finished | Sep 01 11:18:13 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725184302 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2725184302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.2758547553 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 68020348 ps |
| CPU time | 2.46 seconds |
| Started | Sep 01 11:17:56 PM UTC 24 |
| Finished | Sep 01 11:18:00 PM UTC 24 |
| Peak memory | 229536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758547553 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2758547553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.2571201247 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 47548958 ps |
| CPU time | 3.92 seconds |
| Started | Sep 01 11:17:55 PM UTC 24 |
| Finished | Sep 01 11:18:00 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571201247 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2571201247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.1485860295 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 313744746 ps |
| CPU time | 13.08 seconds |
| Started | Sep 01 11:17:58 PM UTC 24 |
| Finished | Sep 01 11:18:12 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485860295 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1485860295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.1694614592 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2286582870 ps |
| CPU time | 12.61 seconds |
| Started | Sep 01 11:17:59 PM UTC 24 |
| Finished | Sep 01 11:18:13 PM UTC 24 |
| Peak memory | 231536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694614592 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_to ken_digest.1694614592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.2304344971 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 323672886 ps |
| CPU time | 10.68 seconds |
| Started | Sep 01 11:17:58 PM UTC 24 |
| Finished | Sep 01 11:18:09 PM UTC 24 |
| Peak memory | 232264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304344971 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token _mux.2304344971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.2732869051 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 395105744 ps |
| CPU time | 11.08 seconds |
| Started | Sep 01 11:17:56 PM UTC 24 |
| Finished | Sep 01 11:18:09 PM UTC 24 |
| Peak memory | 237672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732869051 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2732869051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.3619893385 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 207228685 ps |
| CPU time | 4.31 seconds |
| Started | Sep 01 11:17:53 PM UTC 24 |
| Finished | Sep 01 11:17:58 PM UTC 24 |
| Peak memory | 229428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619893385 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3619893385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.3088614408 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 221644938 ps |
| CPU time | 30.53 seconds |
| Started | Sep 01 11:17:53 PM UTC 24 |
| Finished | Sep 01 11:18:25 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088614408 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3088614408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.2354489498 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 135387308 ps |
| CPU time | 5.16 seconds |
| Started | Sep 01 11:17:54 PM UTC 24 |
| Finished | Sep 01 11:18:00 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354489498 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2354489498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.3739126883 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 82082815034 ps |
| CPU time | 740.85 seconds |
| Started | Sep 01 11:17:59 PM UTC 24 |
| Finished | Sep 01 11:30:29 PM UTC 24 |
| Peak memory | 291232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3739126883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 33.lc_ctrl_stress_all.3739126883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.1873148812 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2228440452 ps |
| CPU time | 108.54 seconds |
| Started | Sep 01 11:18:00 PM UTC 24 |
| Finished | Sep 01 11:19:51 PM UTC 24 |
| Peak memory | 273052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873148812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.1873148812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2790563139 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 23402406 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 11:17:53 PM UTC 24 |
| Finished | Sep 01 11:17:55 PM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790563139 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33 .lc_ctrl_volatile_unlock_smoke.2790563139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.610203264 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 45096686 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 11:18:08 PM UTC 24 |
| Finished | Sep 01 11:18:10 PM UTC 24 |
| Peak memory | 217376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610203264 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.610203264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.3168113917 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 608366905 ps |
| CPU time | 14.89 seconds |
| Started | Sep 01 11:18:04 PM UTC 24 |
| Finished | Sep 01 11:18:20 PM UTC 24 |
| Peak memory | 232040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168113917 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3168113917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.3122214035 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1412547331 ps |
| CPU time | 4.5 seconds |
| Started | Sep 01 11:18:04 PM UTC 24 |
| Finished | Sep 01 11:18:10 PM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122214035 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3122214035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3634709866 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 384101037 ps |
| CPU time | 6.59 seconds |
| Started | Sep 01 11:18:04 PM UTC 24 |
| Finished | Sep 01 11:18:12 PM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634709866 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3634709866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.3795726802 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 1627422409 ps |
| CPU time | 14.76 seconds |
| Started | Sep 01 11:18:06 PM UTC 24 |
| Finished | Sep 01 11:18:22 PM UTC 24 |
| Peak memory | 237664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795726802 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3795726802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.2882595733 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 205597258 ps |
| CPU time | 9.09 seconds |
| Started | Sep 01 11:18:07 PM UTC 24 |
| Finished | Sep 01 11:18:17 PM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882595733 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_to ken_digest.2882595733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.2301258886 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 1637439315 ps |
| CPU time | 11.87 seconds |
| Started | Sep 01 11:18:07 PM UTC 24 |
| Finished | Sep 01 11:18:20 PM UTC 24 |
| Peak memory | 229824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301258886 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token _mux.2301258886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.3467975620 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1619951261 ps |
| CPU time | 16.08 seconds |
| Started | Sep 01 11:18:04 PM UTC 24 |
| Finished | Sep 01 11:18:22 PM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467975620 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3467975620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.1958743342 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 64679686 ps |
| CPU time | 4.12 seconds |
| Started | Sep 01 11:18:01 PM UTC 24 |
| Finished | Sep 01 11:18:06 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958743342 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1958743342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.4014338621 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 3572478840 ps |
| CPU time | 54.9 seconds |
| Started | Sep 01 11:18:01 PM UTC 24 |
| Finished | Sep 01 11:18:58 PM UTC 24 |
| Peak memory | 262564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014338621 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.4014338621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.2756100041 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 80778816 ps |
| CPU time | 12.12 seconds |
| Started | Sep 01 11:18:03 PM UTC 24 |
| Finished | Sep 01 11:18:16 PM UTC 24 |
| Peak memory | 262684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756100041 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2756100041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.3692496791 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 7719497486 ps |
| CPU time | 122.99 seconds |
| Started | Sep 01 11:18:07 PM UTC 24 |
| Finished | Sep 01 11:20:12 PM UTC 24 |
| Peak memory | 295408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3692496791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 34.lc_ctrl_stress_all.3692496791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1380761340 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 1717165981 ps |
| CPU time | 76.69 seconds |
| Started | Sep 01 11:18:08 PM UTC 24 |
| Finished | Sep 01 11:19:27 PM UTC 24 |
| Peak memory | 264880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380761340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.1380761340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1499914547 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 12339517 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 11:18:01 PM UTC 24 |
| Finished | Sep 01 11:18:04 PM UTC 24 |
| Peak memory | 219036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499914547 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34 .lc_ctrl_volatile_unlock_smoke.1499914547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.1214862641 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 110602030 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 11:18:16 PM UTC 24 |
| Finished | Sep 01 11:18:19 PM UTC 24 |
| Peak memory | 218624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214862641 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1214862641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.1808060558 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 446478986 ps |
| CPU time | 17.14 seconds |
| Started | Sep 01 11:18:12 PM UTC 24 |
| Finished | Sep 01 11:18:30 PM UTC 24 |
| Peak memory | 231896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808060558 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1808060558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.1438825594 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 48785995 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 11:18:13 PM UTC 24 |
| Finished | Sep 01 11:18:16 PM UTC 24 |
| Peak memory | 229208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438825594 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1438825594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.2619689225 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 177759689 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 11:18:12 PM UTC 24 |
| Finished | Sep 01 11:18:15 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619689225 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2619689225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.607231742 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 815817051 ps |
| CPU time | 25.07 seconds |
| Started | Sep 01 11:18:13 PM UTC 24 |
| Finished | Sep 01 11:18:40 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607231742 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.607231742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.2404279802 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3805224731 ps |
| CPU time | 28.22 seconds |
| Started | Sep 01 11:18:14 PM UTC 24 |
| Finished | Sep 01 11:18:43 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404279802 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_to ken_digest.2404279802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.1957760878 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 729193755 ps |
| CPU time | 11.62 seconds |
| Started | Sep 01 11:18:14 PM UTC 24 |
| Finished | Sep 01 11:18:26 PM UTC 24 |
| Peak memory | 231944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957760878 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token _mux.1957760878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.2554940275 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 1368762387 ps |
| CPU time | 13.85 seconds |
| Started | Sep 01 11:18:13 PM UTC 24 |
| Finished | Sep 01 11:18:28 PM UTC 24 |
| Peak memory | 231964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554940275 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2554940275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.2228316191 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 1481705405 ps |
| CPU time | 6.02 seconds |
| Started | Sep 01 11:18:09 PM UTC 24 |
| Finished | Sep 01 11:18:17 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228316191 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2228316191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.4028148243 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 1176928996 ps |
| CPU time | 38.4 seconds |
| Started | Sep 01 11:18:11 PM UTC 24 |
| Finished | Sep 01 11:18:50 PM UTC 24 |
| Peak memory | 262640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028148243 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.4028148243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.2962118777 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 112644572 ps |
| CPU time | 13 seconds |
| Started | Sep 01 11:18:11 PM UTC 24 |
| Finished | Sep 01 11:18:25 PM UTC 24 |
| Peak memory | 262456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962118777 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2962118777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2938567618 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 2411729881 ps |
| CPU time | 80.35 seconds |
| Started | Sep 01 11:18:15 PM UTC 24 |
| Finished | Sep 01 11:19:37 PM UTC 24 |
| Peak memory | 281068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2938567618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 35.lc_ctrl_stress_all.2938567618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.4179244490 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 16993225100 ps |
| CPU time | 114.41 seconds |
| Started | Sep 01 11:18:15 PM UTC 24 |
| Finished | Sep 01 11:20:12 PM UTC 24 |
| Peak memory | 293504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179244490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.4179244490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3152550831 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 15607974 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 11:18:11 PM UTC 24 |
| Finished | Sep 01 11:18:13 PM UTC 24 |
| Peak memory | 218412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152550831 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35 .lc_ctrl_volatile_unlock_smoke.3152550831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.2814666739 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 83725270 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 11:18:25 PM UTC 24 |
| Finished | Sep 01 11:18:27 PM UTC 24 |
| Peak memory | 218584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814666739 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2814666739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.85271606 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 1071176359 ps |
| CPU time | 16.07 seconds |
| Started | Sep 01 11:18:20 PM UTC 24 |
| Finished | Sep 01 11:18:37 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85271606 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.85271606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.3706257092 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 1462655856 ps |
| CPU time | 8.04 seconds |
| Started | Sep 01 11:18:21 PM UTC 24 |
| Finished | Sep 01 11:18:30 PM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706257092 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3706257092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.1165693725 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 53081879 ps |
| CPU time | 3.79 seconds |
| Started | Sep 01 11:18:19 PM UTC 24 |
| Finished | Sep 01 11:18:24 PM UTC 24 |
| Peak memory | 236072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165693725 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1165693725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.1117558527 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 2634733742 ps |
| CPU time | 18.73 seconds |
| Started | Sep 01 11:18:21 PM UTC 24 |
| Finished | Sep 01 11:18:41 PM UTC 24 |
| Peak memory | 237656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117558527 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1117558527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.2823005731 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 596646437 ps |
| CPU time | 16.26 seconds |
| Started | Sep 01 11:18:23 PM UTC 24 |
| Finished | Sep 01 11:18:40 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823005731 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_to ken_digest.2823005731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.2117783301 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 2595063657 ps |
| CPU time | 14.1 seconds |
| Started | Sep 01 11:18:21 PM UTC 24 |
| Finished | Sep 01 11:18:37 PM UTC 24 |
| Peak memory | 232008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117783301 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token _mux.2117783301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.1754777185 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 433384675 ps |
| CPU time | 17.18 seconds |
| Started | Sep 01 11:18:20 PM UTC 24 |
| Finished | Sep 01 11:18:38 PM UTC 24 |
| Peak memory | 231896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754777185 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1754777185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.1882455868 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 52210314 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 11:18:17 PM UTC 24 |
| Finished | Sep 01 11:18:20 PM UTC 24 |
| Peak memory | 222316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882455868 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1882455868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.1809222665 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 234208633 ps |
| CPU time | 36.38 seconds |
| Started | Sep 01 11:18:17 PM UTC 24 |
| Finished | Sep 01 11:18:55 PM UTC 24 |
| Peak memory | 262496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809222665 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1809222665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.2692520746 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 157926569 ps |
| CPU time | 8.65 seconds |
| Started | Sep 01 11:18:19 PM UTC 24 |
| Finished | Sep 01 11:18:28 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692520746 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2692520746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.1804085930 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 2140205329 ps |
| CPU time | 46.24 seconds |
| Started | Sep 01 11:18:23 PM UTC 24 |
| Finished | Sep 01 11:19:10 PM UTC 24 |
| Peak memory | 262952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1804085930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 36.lc_ctrl_stress_all.1804085930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.4141069043 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 14165986 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 11:18:17 PM UTC 24 |
| Finished | Sep 01 11:18:19 PM UTC 24 |
| Peak memory | 218532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141069043 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36 .lc_ctrl_volatile_unlock_smoke.4141069043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.2950640117 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 62741083 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 11:18:36 PM UTC 24 |
| Finished | Sep 01 11:18:38 PM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950640117 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2950640117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.3818218354 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 996079206 ps |
| CPU time | 24.89 seconds |
| Started | Sep 01 11:18:29 PM UTC 24 |
| Finished | Sep 01 11:18:55 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818218354 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3818218354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.3320855965 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 415527275 ps |
| CPU time | 4.67 seconds |
| Started | Sep 01 11:18:30 PM UTC 24 |
| Finished | Sep 01 11:18:36 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320855965 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3320855965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.4002458758 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 107856905 ps |
| CPU time | 2.97 seconds |
| Started | Sep 01 11:18:29 PM UTC 24 |
| Finished | Sep 01 11:18:33 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002458758 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.4002458758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.2085089408 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 3855535381 ps |
| CPU time | 13.9 seconds |
| Started | Sep 01 11:18:30 PM UTC 24 |
| Finished | Sep 01 11:18:45 PM UTC 24 |
| Peak memory | 237648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085089408 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2085089408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.2939356410 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 634636520 ps |
| CPU time | 16.87 seconds |
| Started | Sep 01 11:18:31 PM UTC 24 |
| Finished | Sep 01 11:18:50 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939356410 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_to ken_digest.2939356410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.3600353432 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 266936720 ps |
| CPU time | 12.32 seconds |
| Started | Sep 01 11:18:31 PM UTC 24 |
| Finished | Sep 01 11:18:45 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600353432 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token _mux.3600353432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.903384536 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 1522940971 ps |
| CPU time | 12.93 seconds |
| Started | Sep 01 11:18:30 PM UTC 24 |
| Finished | Sep 01 11:18:44 PM UTC 24 |
| Peak memory | 232272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903384536 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.903384536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.2595313018 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 89746473 ps |
| CPU time | 7.78 seconds |
| Started | Sep 01 11:18:26 PM UTC 24 |
| Finished | Sep 01 11:18:35 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595313018 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2595313018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.2675051619 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 321743296 ps |
| CPU time | 44.58 seconds |
| Started | Sep 01 11:18:26 PM UTC 24 |
| Finished | Sep 01 11:19:12 PM UTC 24 |
| Peak memory | 260452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675051619 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2675051619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.1220041893 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 169486428 ps |
| CPU time | 12.61 seconds |
| Started | Sep 01 11:18:27 PM UTC 24 |
| Finished | Sep 01 11:18:41 PM UTC 24 |
| Peak memory | 260456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220041893 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1220041893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.544915635 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 8485756677 ps |
| CPU time | 133.17 seconds |
| Started | Sep 01 11:18:31 PM UTC 24 |
| Finished | Sep 01 11:20:47 PM UTC 24 |
| Peak memory | 262892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=544915635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 37.lc_ctrl_stress_all.544915635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.438323361 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 50022261 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 11:18:26 PM UTC 24 |
| Finished | Sep 01 11:18:29 PM UTC 24 |
| Peak memory | 228704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438323361 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37. lc_ctrl_volatile_unlock_smoke.438323361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.1300716485 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 26017859 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 11:18:44 PM UTC 24 |
| Finished | Sep 01 11:18:47 PM UTC 24 |
| Peak memory | 217372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300716485 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1300716485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.1481378307 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 5572938842 ps |
| CPU time | 19.01 seconds |
| Started | Sep 01 11:18:40 PM UTC 24 |
| Finished | Sep 01 11:19:01 PM UTC 24 |
| Peak memory | 230228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481378307 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1481378307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2938605672 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1983386371 ps |
| CPU time | 14.34 seconds |
| Started | Sep 01 11:18:41 PM UTC 24 |
| Finished | Sep 01 11:18:56 PM UTC 24 |
| Peak memory | 229948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938605672 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2938605672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.3014268462 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 66282962 ps |
| CPU time | 2.15 seconds |
| Started | Sep 01 11:18:39 PM UTC 24 |
| Finished | Sep 01 11:18:43 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014268462 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3014268462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.1626817013 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 257002402 ps |
| CPU time | 14.73 seconds |
| Started | Sep 01 11:18:42 PM UTC 24 |
| Finished | Sep 01 11:18:58 PM UTC 24 |
| Peak memory | 237792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626817013 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1626817013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.3679464360 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 232658469 ps |
| CPU time | 14.73 seconds |
| Started | Sep 01 11:18:42 PM UTC 24 |
| Finished | Sep 01 11:18:58 PM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679464360 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_to ken_digest.3679464360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.1411321191 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 389364586 ps |
| CPU time | 17.74 seconds |
| Started | Sep 01 11:18:42 PM UTC 24 |
| Finished | Sep 01 11:19:01 PM UTC 24 |
| Peak memory | 229916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411321191 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token _mux.1411321191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.2076858486 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2504007009 ps |
| CPU time | 10.36 seconds |
| Started | Sep 01 11:18:40 PM UTC 24 |
| Finished | Sep 01 11:18:52 PM UTC 24 |
| Peak memory | 232024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076858486 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2076858486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.1320660000 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 173266966 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 11:18:37 PM UTC 24 |
| Finished | Sep 01 11:18:39 PM UTC 24 |
| Peak memory | 228620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320660000 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1320660000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.933272490 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 210039389 ps |
| CPU time | 21.19 seconds |
| Started | Sep 01 11:18:38 PM UTC 24 |
| Finished | Sep 01 11:19:01 PM UTC 24 |
| Peak memory | 262508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933272490 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.933272490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.3169085611 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 56781933 ps |
| CPU time | 8.28 seconds |
| Started | Sep 01 11:18:39 PM UTC 24 |
| Finished | Sep 01 11:18:49 PM UTC 24 |
| Peak memory | 260456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169085611 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3169085611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.2459191634 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 2873238932 ps |
| CPU time | 100.43 seconds |
| Started | Sep 01 11:18:43 PM UTC 24 |
| Finished | Sep 01 11:20:26 PM UTC 24 |
| Peak memory | 287468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2459191634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 38.lc_ctrl_stress_all.2459191634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2294007170 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 15947336 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 11:18:38 PM UTC 24 |
| Finished | Sep 01 11:18:41 PM UTC 24 |
| Peak memory | 222388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294007170 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38 .lc_ctrl_volatile_unlock_smoke.2294007170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.1654973953 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 67782350 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 11:18:56 PM UTC 24 |
| Finished | Sep 01 11:18:58 PM UTC 24 |
| Peak memory | 219060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654973953 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1654973953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.1760494749 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 455663703 ps |
| CPU time | 22.57 seconds |
| Started | Sep 01 11:18:48 PM UTC 24 |
| Finished | Sep 01 11:19:12 PM UTC 24 |
| Peak memory | 229844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760494749 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1760494749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.4119365968 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 279472330 ps |
| CPU time | 8.07 seconds |
| Started | Sep 01 11:18:50 PM UTC 24 |
| Finished | Sep 01 11:18:59 PM UTC 24 |
| Peak memory | 229512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119365968 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.4119365968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.645501829 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 58627156 ps |
| CPU time | 4.31 seconds |
| Started | Sep 01 11:18:48 PM UTC 24 |
| Finished | Sep 01 11:18:53 PM UTC 24 |
| Peak memory | 232224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645501829 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.645501829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1284194694 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 439395913 ps |
| CPU time | 20.98 seconds |
| Started | Sep 01 11:18:50 PM UTC 24 |
| Finished | Sep 01 11:19:12 PM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284194694 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1284194694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.453546254 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3226328718 ps |
| CPU time | 26.49 seconds |
| Started | Sep 01 11:18:51 PM UTC 24 |
| Finished | Sep 01 11:19:19 PM UTC 24 |
| Peak memory | 237968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453546254 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_tok en_digest.453546254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.2608282389 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1560198017 ps |
| CPU time | 14.96 seconds |
| Started | Sep 01 11:18:51 PM UTC 24 |
| Finished | Sep 01 11:19:08 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608282389 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token _mux.2608282389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.105404500 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 1976212667 ps |
| CPU time | 19.93 seconds |
| Started | Sep 01 11:18:49 PM UTC 24 |
| Finished | Sep 01 11:19:10 PM UTC 24 |
| Peak memory | 232208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105404500 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.105404500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.2170876555 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 91662612 ps |
| CPU time | 2.11 seconds |
| Started | Sep 01 11:18:46 PM UTC 24 |
| Finished | Sep 01 11:18:49 PM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170876555 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2170876555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.1500861663 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 486267519 ps |
| CPU time | 43.09 seconds |
| Started | Sep 01 11:18:46 PM UTC 24 |
| Finished | Sep 01 11:19:30 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500861663 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1500861663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.414818530 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 54260921 ps |
| CPU time | 8.81 seconds |
| Started | Sep 01 11:18:48 PM UTC 24 |
| Finished | Sep 01 11:18:58 PM UTC 24 |
| Peak memory | 258644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414818530 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.414818530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.4125198102 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 686667812 ps |
| CPU time | 47.72 seconds |
| Started | Sep 01 11:18:53 PM UTC 24 |
| Finished | Sep 01 11:19:43 PM UTC 24 |
| Peak memory | 262832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4125198102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 39.lc_ctrl_stress_all.4125198102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.884269467 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1471651631 ps |
| CPU time | 50.22 seconds |
| Started | Sep 01 11:18:53 PM UTC 24 |
| Finished | Sep 01 11:19:46 PM UTC 24 |
| Peak memory | 262624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884269467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.884269467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2141497533 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 27691939 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 11:18:46 PM UTC 24 |
| Finished | Sep 01 11:18:48 PM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141497533 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39 .lc_ctrl_volatile_unlock_smoke.2141497533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.3772945609 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 38017639 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 11:10:54 PM UTC 24 |
| Finished | Sep 01 11:10:57 PM UTC 24 |
| Peak memory | 218528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772945609 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3772945609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.4076167032 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 401658512 ps |
| CPU time | 18.34 seconds |
| Started | Sep 01 11:10:31 PM UTC 24 |
| Finished | Sep 01 11:10:50 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076167032 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.4076167032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.1843766505 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1717165485 ps |
| CPU time | 9.86 seconds |
| Started | Sep 01 11:10:43 PM UTC 24 |
| Finished | Sep 01 11:10:54 PM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843766505 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1843766505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.2727328660 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 10954493411 ps |
| CPU time | 47.84 seconds |
| Started | Sep 01 11:10:41 PM UTC 24 |
| Finished | Sep 01 11:11:30 PM UTC 24 |
| Peak memory | 231892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727328660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jt ag_errors.2727328660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.1555860244 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 910047398 ps |
| CPU time | 25.29 seconds |
| Started | Sep 01 11:10:44 PM UTC 24 |
| Finished | Sep 01 11:11:10 PM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555860244 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_prior ity.1555860244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.1697699722 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 685064816 ps |
| CPU time | 7.85 seconds |
| Started | Sep 01 11:10:37 PM UTC 24 |
| Finished | Sep 01 11:10:46 PM UTC 24 |
| Peak memory | 231804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697699722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl _jtag_prog_failure.1697699722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1135264213 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 3378707569 ps |
| CPU time | 18.7 seconds |
| Started | Sep 01 11:10:45 PM UTC 24 |
| Finished | Sep 01 11:11:05 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135264213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ ctrl_jtag_regwen_during_op.1135264213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.4082952371 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 862524002 ps |
| CPU time | 5.48 seconds |
| Started | Sep 01 11:10:35 PM UTC 24 |
| Finished | Sep 01 11:10:42 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082952371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_s moke.4082952371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.1782175636 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2995038813 ps |
| CPU time | 74.17 seconds |
| Started | Sep 01 11:10:36 PM UTC 24 |
| Finished | Sep 01 11:11:52 PM UTC 24 |
| Peak memory | 282972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782175636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr l_jtag_state_failure.1782175636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.1919270896 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1377785171 ps |
| CPU time | 23.66 seconds |
| Started | Sep 01 11:10:36 PM UTC 24 |
| Finished | Sep 01 11:11:01 PM UTC 24 |
| Peak memory | 262436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919270896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ ctrl_jtag_state_post_trans.1919270896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.1886104454 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 64040156 ps |
| CPU time | 4.74 seconds |
| Started | Sep 01 11:10:30 PM UTC 24 |
| Finished | Sep 01 11:10:36 PM UTC 24 |
| Peak memory | 236300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886104454 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1886104454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.1631930742 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 223653386 ps |
| CPU time | 9.04 seconds |
| Started | Sep 01 11:10:33 PM UTC 24 |
| Finished | Sep 01 11:10:43 PM UTC 24 |
| Peak memory | 225384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631930742 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1631930742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.4133185979 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 205789659 ps |
| CPU time | 57.07 seconds |
| Started | Sep 01 11:10:51 PM UTC 24 |
| Finished | Sep 01 11:11:50 PM UTC 24 |
| Peak memory | 298140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133185979 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.4133185979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.3074439323 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 535906514 ps |
| CPU time | 22.99 seconds |
| Started | Sep 01 11:10:46 PM UTC 24 |
| Finished | Sep 01 11:11:11 PM UTC 24 |
| Peak memory | 237588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074439323 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3074439323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.2190371303 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 448569637 ps |
| CPU time | 22.94 seconds |
| Started | Sep 01 11:10:48 PM UTC 24 |
| Finished | Sep 01 11:11:12 PM UTC 24 |
| Peak memory | 231812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190371303 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_tok en_digest.2190371303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.1111508899 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 466360432 ps |
| CPU time | 22.42 seconds |
| Started | Sep 01 11:10:46 PM UTC 24 |
| Finished | Sep 01 11:11:10 PM UTC 24 |
| Peak memory | 237932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111508899 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_ mux.1111508899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.4136775881 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 630743482 ps |
| CPU time | 13.79 seconds |
| Started | Sep 01 11:10:32 PM UTC 24 |
| Finished | Sep 01 11:10:47 PM UTC 24 |
| Peak memory | 237636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136775881 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.4136775881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.3886412750 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 65642387 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 11:10:25 PM UTC 24 |
| Finished | Sep 01 11:10:28 PM UTC 24 |
| Peak memory | 222312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886412750 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3886412750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1254632910 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 263048148 ps |
| CPU time | 39.73 seconds |
| Started | Sep 01 11:10:28 PM UTC 24 |
| Finished | Sep 01 11:11:10 PM UTC 24 |
| Peak memory | 262508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254632910 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1254632910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.3658599534 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 168135369 ps |
| CPU time | 9.3 seconds |
| Started | Sep 01 11:10:29 PM UTC 24 |
| Finished | Sep 01 11:10:40 PM UTC 24 |
| Peak memory | 260376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658599534 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3658599534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.2762594774 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 7181096950 ps |
| CPU time | 147.42 seconds |
| Started | Sep 01 11:10:48 PM UTC 24 |
| Finished | Sep 01 11:13:18 PM UTC 24 |
| Peak memory | 280992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2762594774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 4.lc_ctrl_stress_all.2762594774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.165321055 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 7069830879 ps |
| CPU time | 176.42 seconds |
| Started | Sep 01 11:10:49 PM UTC 24 |
| Finished | Sep 01 11:13:48 PM UTC 24 |
| Peak memory | 295812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165321055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.165321055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.2111743026 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 26128418 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 11:19:04 PM UTC 24 |
| Finished | Sep 01 11:19:06 PM UTC 24 |
| Peak memory | 217372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111743026 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2111743026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.2889422224 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 987607323 ps |
| CPU time | 19.25 seconds |
| Started | Sep 01 11:19:00 PM UTC 24 |
| Finished | Sep 01 11:19:20 PM UTC 24 |
| Peak memory | 232148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889422224 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2889422224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.1664156167 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 2293801295 ps |
| CPU time | 16.3 seconds |
| Started | Sep 01 11:19:00 PM UTC 24 |
| Finished | Sep 01 11:19:17 PM UTC 24 |
| Peak memory | 229568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664156167 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1664156167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.2815280049 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 345388952 ps |
| CPU time | 4.52 seconds |
| Started | Sep 01 11:19:00 PM UTC 24 |
| Finished | Sep 01 11:19:05 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815280049 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2815280049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.2650046851 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 961411244 ps |
| CPU time | 11.86 seconds |
| Started | Sep 01 11:19:01 PM UTC 24 |
| Finished | Sep 01 11:19:14 PM UTC 24 |
| Peak memory | 231944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650046851 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2650046851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.2723709303 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 249754965 ps |
| CPU time | 11.14 seconds |
| Started | Sep 01 11:19:02 PM UTC 24 |
| Finished | Sep 01 11:19:15 PM UTC 24 |
| Peak memory | 231816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723709303 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_to ken_digest.2723709303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.341068596 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 1994848773 ps |
| CPU time | 17.27 seconds |
| Started | Sep 01 11:19:01 PM UTC 24 |
| Finished | Sep 01 11:19:19 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341068596 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_ mux.341068596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.985090377 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 340295020 ps |
| CPU time | 15.67 seconds |
| Started | Sep 01 11:19:00 PM UTC 24 |
| Finished | Sep 01 11:19:16 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985090377 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.985090377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1550060301 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 80534318 ps |
| CPU time | 5.07 seconds |
| Started | Sep 01 11:18:56 PM UTC 24 |
| Finished | Sep 01 11:19:02 PM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550060301 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1550060301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.1325597398 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 640345571 ps |
| CPU time | 50.66 seconds |
| Started | Sep 01 11:18:58 PM UTC 24 |
| Finished | Sep 01 11:19:51 PM UTC 24 |
| Peak memory | 260784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325597398 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1325597398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.2873168043 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 119483669 ps |
| CPU time | 3.79 seconds |
| Started | Sep 01 11:18:59 PM UTC 24 |
| Finished | Sep 01 11:19:04 PM UTC 24 |
| Peak memory | 237996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873168043 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2873168043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.2319015191 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 22926636267 ps |
| CPU time | 154.54 seconds |
| Started | Sep 01 11:19:03 PM UTC 24 |
| Finished | Sep 01 11:21:40 PM UTC 24 |
| Peak memory | 272816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2319015191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 40.lc_ctrl_stress_all.2319015191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.4251446245 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 83484460 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 11:18:57 PM UTC 24 |
| Finished | Sep 01 11:18:59 PM UTC 24 |
| Peak memory | 218344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251446245 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40 .lc_ctrl_volatile_unlock_smoke.4251446245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.927642422 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 19707589 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 11:19:14 PM UTC 24 |
| Finished | Sep 01 11:19:16 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927642422 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.927642422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.3303096315 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 257369665 ps |
| CPU time | 9.38 seconds |
| Started | Sep 01 11:19:09 PM UTC 24 |
| Finished | Sep 01 11:19:20 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303096315 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3303096315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.2356884652 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1595816610 ps |
| CPU time | 9.89 seconds |
| Started | Sep 01 11:19:11 PM UTC 24 |
| Finished | Sep 01 11:19:22 PM UTC 24 |
| Peak memory | 228852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356884652 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2356884652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.2608775478 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 67505677 ps |
| CPU time | 4.26 seconds |
| Started | Sep 01 11:19:08 PM UTC 24 |
| Finished | Sep 01 11:19:13 PM UTC 24 |
| Peak memory | 236312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608775478 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2608775478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.2444001332 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 573569695 ps |
| CPU time | 20.48 seconds |
| Started | Sep 01 11:19:11 PM UTC 24 |
| Finished | Sep 01 11:19:33 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444001332 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2444001332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.1557496712 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 308677816 ps |
| CPU time | 9.87 seconds |
| Started | Sep 01 11:19:12 PM UTC 24 |
| Finished | Sep 01 11:19:23 PM UTC 24 |
| Peak memory | 237848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557496712 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_to ken_digest.1557496712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.1887566356 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 799710088 ps |
| CPU time | 9.8 seconds |
| Started | Sep 01 11:19:11 PM UTC 24 |
| Finished | Sep 01 11:19:22 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887566356 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token _mux.1887566356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.5827969 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 341478813 ps |
| CPU time | 13.3 seconds |
| Started | Sep 01 11:19:09 PM UTC 24 |
| Finished | Sep 01 11:19:24 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5827969 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.5827969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.1327072248 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 540666290 ps |
| CPU time | 2.11 seconds |
| Started | Sep 01 11:19:05 PM UTC 24 |
| Finished | Sep 01 11:19:08 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327072248 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1327072248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.985778830 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 768802901 ps |
| CPU time | 37.58 seconds |
| Started | Sep 01 11:19:07 PM UTC 24 |
| Finished | Sep 01 11:19:46 PM UTC 24 |
| Peak memory | 262580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985778830 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.985778830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.2532005719 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 162105735 ps |
| CPU time | 9.12 seconds |
| Started | Sep 01 11:19:08 PM UTC 24 |
| Finished | Sep 01 11:19:18 PM UTC 24 |
| Peak memory | 258716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532005719 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2532005719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.1826548077 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 5678756281 ps |
| CPU time | 209.65 seconds |
| Started | Sep 01 11:19:12 PM UTC 24 |
| Finished | Sep 01 11:22:45 PM UTC 24 |
| Peak memory | 281072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1826548077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 41.lc_ctrl_stress_all.1826548077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1020563644 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 63936865 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 11:19:06 PM UTC 24 |
| Finished | Sep 01 11:19:08 PM UTC 24 |
| Peak memory | 228692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020563644 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41 .lc_ctrl_volatile_unlock_smoke.1020563644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.3513957255 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 119097614 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 11:19:22 PM UTC 24 |
| Finished | Sep 01 11:19:25 PM UTC 24 |
| Peak memory | 217228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513957255 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3513957255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1892588203 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 354163422 ps |
| CPU time | 16.38 seconds |
| Started | Sep 01 11:19:18 PM UTC 24 |
| Finished | Sep 01 11:19:36 PM UTC 24 |
| Peak memory | 232148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892588203 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1892588203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.418644728 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1401872731 ps |
| CPU time | 11.63 seconds |
| Started | Sep 01 11:19:20 PM UTC 24 |
| Finished | Sep 01 11:19:32 PM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418644728 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.418644728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.2655224564 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 250002888 ps |
| CPU time | 4.87 seconds |
| Started | Sep 01 11:19:17 PM UTC 24 |
| Finished | Sep 01 11:19:23 PM UTC 24 |
| Peak memory | 232212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655224564 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2655224564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.1782847990 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 435824122 ps |
| CPU time | 12.75 seconds |
| Started | Sep 01 11:19:21 PM UTC 24 |
| Finished | Sep 01 11:19:35 PM UTC 24 |
| Peak memory | 237664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782847990 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1782847990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.2944311426 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 1450191537 ps |
| CPU time | 15.72 seconds |
| Started | Sep 01 11:19:21 PM UTC 24 |
| Finished | Sep 01 11:19:38 PM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944311426 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_to ken_digest.2944311426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.3154643861 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 300087895 ps |
| CPU time | 11.41 seconds |
| Started | Sep 01 11:19:21 PM UTC 24 |
| Finished | Sep 01 11:19:34 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154643861 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token _mux.3154643861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.2495239115 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 615768888 ps |
| CPU time | 18.06 seconds |
| Started | Sep 01 11:19:18 PM UTC 24 |
| Finished | Sep 01 11:19:38 PM UTC 24 |
| Peak memory | 231888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495239115 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2495239115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.1745134667 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 80465648 ps |
| CPU time | 3.47 seconds |
| Started | Sep 01 11:19:15 PM UTC 24 |
| Finished | Sep 01 11:19:19 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745134667 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1745134667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.3001026318 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 1402027247 ps |
| CPU time | 46.63 seconds |
| Started | Sep 01 11:19:16 PM UTC 24 |
| Finished | Sep 01 11:20:04 PM UTC 24 |
| Peak memory | 262576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001026318 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3001026318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.3459264429 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 248890679 ps |
| CPU time | 9.72 seconds |
| Started | Sep 01 11:19:17 PM UTC 24 |
| Finished | Sep 01 11:19:28 PM UTC 24 |
| Peak memory | 262756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459264429 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3459264429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.1202697224 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 7431234370 ps |
| CPU time | 171.34 seconds |
| Started | Sep 01 11:19:21 PM UTC 24 |
| Finished | Sep 01 11:22:15 PM UTC 24 |
| Peak memory | 287148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1202697224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 42.lc_ctrl_stress_all.1202697224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.2617602681 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 4310422919 ps |
| CPU time | 161.53 seconds |
| Started | Sep 01 11:19:21 PM UTC 24 |
| Finished | Sep 01 11:22:06 PM UTC 24 |
| Peak memory | 273008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617602681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.2617602681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1997100211 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 27827747 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 11:19:15 PM UTC 24 |
| Finished | Sep 01 11:19:17 PM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997100211 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42 .lc_ctrl_volatile_unlock_smoke.1997100211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.2401134418 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 101472949 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 11:19:34 PM UTC 24 |
| Finished | Sep 01 11:19:36 PM UTC 24 |
| Peak memory | 217372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401134418 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2401134418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.1011820741 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 414001317 ps |
| CPU time | 15.29 seconds |
| Started | Sep 01 11:19:27 PM UTC 24 |
| Finished | Sep 01 11:19:44 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011820741 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1011820741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.205381749 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 72383394 ps |
| CPU time | 3.51 seconds |
| Started | Sep 01 11:19:28 PM UTC 24 |
| Finished | Sep 01 11:19:33 PM UTC 24 |
| Peak memory | 229540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205381749 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.205381749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.879017494 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 92998766 ps |
| CPU time | 4.26 seconds |
| Started | Sep 01 11:19:26 PM UTC 24 |
| Finished | Sep 01 11:19:31 PM UTC 24 |
| Peak memory | 236060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879017494 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.879017494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.3838590173 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 1409232275 ps |
| CPU time | 15.71 seconds |
| Started | Sep 01 11:19:30 PM UTC 24 |
| Finished | Sep 01 11:19:47 PM UTC 24 |
| Peak memory | 237580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838590173 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3838590173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.3343266914 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 655369717 ps |
| CPU time | 11.77 seconds |
| Started | Sep 01 11:19:30 PM UTC 24 |
| Finished | Sep 01 11:19:43 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343266914 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_to ken_digest.3343266914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.3483302933 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 1188517165 ps |
| CPU time | 13.57 seconds |
| Started | Sep 01 11:19:30 PM UTC 24 |
| Finished | Sep 01 11:19:45 PM UTC 24 |
| Peak memory | 232008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483302933 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token _mux.3483302933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.2647259235 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 746082040 ps |
| CPU time | 17.42 seconds |
| Started | Sep 01 11:19:27 PM UTC 24 |
| Finished | Sep 01 11:19:46 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647259235 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2647259235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.455204568 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 84169929 ps |
| CPU time | 2.75 seconds |
| Started | Sep 01 11:19:22 PM UTC 24 |
| Finished | Sep 01 11:19:26 PM UTC 24 |
| Peak memory | 225604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455204568 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.455204568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.3132428183 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 199559410 ps |
| CPU time | 32.41 seconds |
| Started | Sep 01 11:19:25 PM UTC 24 |
| Finished | Sep 01 11:19:59 PM UTC 24 |
| Peak memory | 262504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132428183 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3132428183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.1587274589 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 100742500 ps |
| CPU time | 17.27 seconds |
| Started | Sep 01 11:19:25 PM UTC 24 |
| Finished | Sep 01 11:19:43 PM UTC 24 |
| Peak memory | 262504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587274589 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1587274589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.3015032478 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 7785712114 ps |
| CPU time | 167.06 seconds |
| Started | Sep 01 11:19:31 PM UTC 24 |
| Finished | Sep 01 11:22:21 PM UTC 24 |
| Peak memory | 232012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3015032478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 43.lc_ctrl_stress_all.3015032478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.885755847 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 23962479 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 11:19:24 PM UTC 24 |
| Finished | Sep 01 11:19:26 PM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885755847 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43. lc_ctrl_volatile_unlock_smoke.885755847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.1031631847 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 12109458 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 11:19:42 PM UTC 24 |
| Finished | Sep 01 11:19:45 PM UTC 24 |
| Peak memory | 219060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031631847 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1031631847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.3159035013 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 2674620406 ps |
| CPU time | 25.33 seconds |
| Started | Sep 01 11:19:37 PM UTC 24 |
| Finished | Sep 01 11:20:04 PM UTC 24 |
| Peak memory | 232020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159035013 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3159035013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.1583241849 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 856179607 ps |
| CPU time | 6.38 seconds |
| Started | Sep 01 11:19:39 PM UTC 24 |
| Finished | Sep 01 11:19:46 PM UTC 24 |
| Peak memory | 229680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583241849 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1583241849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.1626157623 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 169598404 ps |
| CPU time | 3.02 seconds |
| Started | Sep 01 11:19:37 PM UTC 24 |
| Finished | Sep 01 11:19:41 PM UTC 24 |
| Peak memory | 234004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626157623 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1626157623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.165800947 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 259280737 ps |
| CPU time | 14.88 seconds |
| Started | Sep 01 11:19:39 PM UTC 24 |
| Finished | Sep 01 11:19:55 PM UTC 24 |
| Peak memory | 237976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165800947 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.165800947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2535033416 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 294440006 ps |
| CPU time | 13.57 seconds |
| Started | Sep 01 11:19:39 PM UTC 24 |
| Finished | Sep 01 11:19:54 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535033416 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_to ken_digest.2535033416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.3538680753 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 1878584898 ps |
| CPU time | 12.96 seconds |
| Started | Sep 01 11:19:39 PM UTC 24 |
| Finished | Sep 01 11:19:53 PM UTC 24 |
| Peak memory | 231944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538680753 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token _mux.3538680753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.351127363 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 337317955 ps |
| CPU time | 13.35 seconds |
| Started | Sep 01 11:19:37 PM UTC 24 |
| Finished | Sep 01 11:19:52 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351127363 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.351127363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.1702006098 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 90885704 ps |
| CPU time | 3.26 seconds |
| Started | Sep 01 11:19:34 PM UTC 24 |
| Finished | Sep 01 11:19:38 PM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702006098 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1702006098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.1448151052 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 847877277 ps |
| CPU time | 36.43 seconds |
| Started | Sep 01 11:19:35 PM UTC 24 |
| Finished | Sep 01 11:20:13 PM UTC 24 |
| Peak memory | 262576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448151052 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1448151052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.780869599 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 88111294 ps |
| CPU time | 3.64 seconds |
| Started | Sep 01 11:19:36 PM UTC 24 |
| Finished | Sep 01 11:19:41 PM UTC 24 |
| Peak memory | 236360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780869599 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.780869599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.3731451592 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 23579404037 ps |
| CPU time | 726.16 seconds |
| Started | Sep 01 11:19:42 PM UTC 24 |
| Finished | Sep 01 11:31:58 PM UTC 24 |
| Peak memory | 273136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3731451592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 44.lc_ctrl_stress_all.3731451592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3818795494 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 22977857393 ps |
| CPU time | 296.54 seconds |
| Started | Sep 01 11:19:42 PM UTC 24 |
| Finished | Sep 01 11:24:44 PM UTC 24 |
| Peak memory | 432788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818795494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.3818795494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2686942096 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 86694344 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 11:19:34 PM UTC 24 |
| Finished | Sep 01 11:19:36 PM UTC 24 |
| Peak memory | 222384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686942096 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44 .lc_ctrl_volatile_unlock_smoke.2686942096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.1117141144 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 71108793 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 11:19:48 PM UTC 24 |
| Finished | Sep 01 11:19:50 PM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117141144 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1117141144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.204703856 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 1890011189 ps |
| CPU time | 25.31 seconds |
| Started | Sep 01 11:19:46 PM UTC 24 |
| Finished | Sep 01 11:20:13 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204703856 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.204703856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.3202764870 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 563714625 ps |
| CPU time | 8.37 seconds |
| Started | Sep 01 11:19:46 PM UTC 24 |
| Finished | Sep 01 11:19:56 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202764870 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3202764870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.1515207617 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 116011049 ps |
| CPU time | 3.79 seconds |
| Started | Sep 01 11:19:46 PM UTC 24 |
| Finished | Sep 01 11:19:51 PM UTC 24 |
| Peak memory | 236244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515207617 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1515207617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.4220467234 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 412337005 ps |
| CPU time | 15.2 seconds |
| Started | Sep 01 11:19:47 PM UTC 24 |
| Finished | Sep 01 11:20:03 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220467234 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.4220467234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.4251458394 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 1283115282 ps |
| CPU time | 13.65 seconds |
| Started | Sep 01 11:19:48 PM UTC 24 |
| Finished | Sep 01 11:20:03 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251458394 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_to ken_digest.4251458394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.3496014994 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 763274905 ps |
| CPU time | 10.62 seconds |
| Started | Sep 01 11:19:47 PM UTC 24 |
| Finished | Sep 01 11:19:58 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496014994 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token _mux.3496014994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.3106828057 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 304726692 ps |
| CPU time | 13.41 seconds |
| Started | Sep 01 11:19:46 PM UTC 24 |
| Finished | Sep 01 11:20:01 PM UTC 24 |
| Peak memory | 231964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106828057 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3106828057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.3421236968 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 32963124 ps |
| CPU time | 2.13 seconds |
| Started | Sep 01 11:19:44 PM UTC 24 |
| Finished | Sep 01 11:19:47 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421236968 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3421236968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.2223184913 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 221370212 ps |
| CPU time | 27.48 seconds |
| Started | Sep 01 11:19:45 PM UTC 24 |
| Finished | Sep 01 11:20:14 PM UTC 24 |
| Peak memory | 262576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223184913 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2223184913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.4253039736 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 285140628 ps |
| CPU time | 11.52 seconds |
| Started | Sep 01 11:19:45 PM UTC 24 |
| Finished | Sep 01 11:19:58 PM UTC 24 |
| Peak memory | 262576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253039736 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.4253039736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.1181135717 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 12594352200 ps |
| CPU time | 122.9 seconds |
| Started | Sep 01 11:19:48 PM UTC 24 |
| Finished | Sep 01 11:21:53 PM UTC 24 |
| Peak memory | 295656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1181135717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 45.lc_ctrl_stress_all.1181135717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1200514527 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 26922510 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 11:19:44 PM UTC 24 |
| Finished | Sep 01 11:19:46 PM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200514527 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45 .lc_ctrl_volatile_unlock_smoke.1200514527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.2541559461 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 28375099 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 11:19:57 PM UTC 24 |
| Finished | Sep 01 11:20:00 PM UTC 24 |
| Peak memory | 218448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541559461 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2541559461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.3569018852 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 458878272 ps |
| CPU time | 14.38 seconds |
| Started | Sep 01 11:19:52 PM UTC 24 |
| Finished | Sep 01 11:20:08 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569018852 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3569018852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.1296751601 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 212884260 ps |
| CPU time | 2.09 seconds |
| Started | Sep 01 11:19:54 PM UTC 24 |
| Finished | Sep 01 11:19:57 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296751601 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1296751601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.848648853 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 54314939 ps |
| CPU time | 2.83 seconds |
| Started | Sep 01 11:19:52 PM UTC 24 |
| Finished | Sep 01 11:19:56 PM UTC 24 |
| Peak memory | 231964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848648853 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.848648853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.4293670050 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 846578879 ps |
| CPU time | 22.95 seconds |
| Started | Sep 01 11:19:55 PM UTC 24 |
| Finished | Sep 01 11:20:19 PM UTC 24 |
| Peak memory | 237664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293670050 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.4293670050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.1173125076 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 494492173 ps |
| CPU time | 10.46 seconds |
| Started | Sep 01 11:19:56 PM UTC 24 |
| Finished | Sep 01 11:20:08 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173125076 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_to ken_digest.1173125076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.2558519326 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 825968955 ps |
| CPU time | 28.92 seconds |
| Started | Sep 01 11:19:55 PM UTC 24 |
| Finished | Sep 01 11:20:25 PM UTC 24 |
| Peak memory | 237652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558519326 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token _mux.2558519326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.1891324647 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 475644679 ps |
| CPU time | 9.49 seconds |
| Started | Sep 01 11:19:54 PM UTC 24 |
| Finished | Sep 01 11:20:04 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891324647 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1891324647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.3679407650 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 108464809 ps |
| CPU time | 4.2 seconds |
| Started | Sep 01 11:19:50 PM UTC 24 |
| Finished | Sep 01 11:19:56 PM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679407650 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3679407650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.3528513829 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 788390548 ps |
| CPU time | 26.87 seconds |
| Started | Sep 01 11:19:52 PM UTC 24 |
| Finished | Sep 01 11:20:20 PM UTC 24 |
| Peak memory | 262576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528513829 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3528513829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.2784387544 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 482164633 ps |
| CPU time | 4.24 seconds |
| Started | Sep 01 11:19:52 PM UTC 24 |
| Finished | Sep 01 11:19:57 PM UTC 24 |
| Peak memory | 234260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784387544 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2784387544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.3096359440 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 21925883013 ps |
| CPU time | 81.48 seconds |
| Started | Sep 01 11:19:56 PM UTC 24 |
| Finished | Sep 01 11:21:20 PM UTC 24 |
| Peak memory | 262704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3096359440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 46.lc_ctrl_stress_all.3096359440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.261930383 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 15768161 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 11:19:52 PM UTC 24 |
| Finished | Sep 01 11:19:54 PM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261930383 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46. lc_ctrl_volatile_unlock_smoke.261930383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.984674069 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 68528302 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 11:20:05 PM UTC 24 |
| Finished | Sep 01 11:20:08 PM UTC 24 |
| Peak memory | 218588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984674069 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.984674069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.3006591021 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 386216084 ps |
| CPU time | 15.53 seconds |
| Started | Sep 01 11:19:59 PM UTC 24 |
| Finished | Sep 01 11:20:16 PM UTC 24 |
| Peak memory | 230168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006591021 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3006591021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.3739531260 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 1294651032 ps |
| CPU time | 5.37 seconds |
| Started | Sep 01 11:20:00 PM UTC 24 |
| Finished | Sep 01 11:20:07 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739531260 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3739531260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.663044587 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 50728337 ps |
| CPU time | 3.24 seconds |
| Started | Sep 01 11:19:59 PM UTC 24 |
| Finished | Sep 01 11:20:03 PM UTC 24 |
| Peak memory | 231968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663044587 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.663044587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.1758068464 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 315906872 ps |
| CPU time | 17.61 seconds |
| Started | Sep 01 11:20:01 PM UTC 24 |
| Finished | Sep 01 11:20:20 PM UTC 24 |
| Peak memory | 237920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758068464 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1758068464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.3787945784 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 448073214 ps |
| CPU time | 15.58 seconds |
| Started | Sep 01 11:20:04 PM UTC 24 |
| Finished | Sep 01 11:20:20 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787945784 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_to ken_digest.3787945784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.3045450570 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 1539404480 ps |
| CPU time | 29.1 seconds |
| Started | Sep 01 11:20:02 PM UTC 24 |
| Finished | Sep 01 11:20:33 PM UTC 24 |
| Peak memory | 232264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045450570 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token _mux.3045450570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.3741192744 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 657653318 ps |
| CPU time | 9.42 seconds |
| Started | Sep 01 11:20:00 PM UTC 24 |
| Finished | Sep 01 11:20:11 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741192744 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3741192744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.1184914073 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 180217678 ps |
| CPU time | 7.42 seconds |
| Started | Sep 01 11:19:57 PM UTC 24 |
| Finished | Sep 01 11:20:06 PM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184914073 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1184914073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1032198481 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 205462132 ps |
| CPU time | 26.02 seconds |
| Started | Sep 01 11:19:59 PM UTC 24 |
| Finished | Sep 01 11:20:26 PM UTC 24 |
| Peak memory | 260456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032198481 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1032198481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.1488903535 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 127209184 ps |
| CPU time | 11.36 seconds |
| Started | Sep 01 11:19:59 PM UTC 24 |
| Finished | Sep 01 11:20:11 PM UTC 24 |
| Peak memory | 260376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488903535 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1488903535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.247646733 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 29177763384 ps |
| CPU time | 335.01 seconds |
| Started | Sep 01 11:20:04 PM UTC 24 |
| Finished | Sep 01 11:25:44 PM UTC 24 |
| Peak memory | 234312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=247646733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 47.lc_ctrl_stress_all.247646733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1593464244 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 3002728193 ps |
| CPU time | 82.1 seconds |
| Started | Sep 01 11:20:04 PM UTC 24 |
| Finished | Sep 01 11:21:28 PM UTC 24 |
| Peak memory | 262688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593464244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.1593464244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3531426259 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 47172988 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 11:19:57 PM UTC 24 |
| Finished | Sep 01 11:19:59 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531426259 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47 .lc_ctrl_volatile_unlock_smoke.3531426259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.460411573 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 13868364 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 11:20:14 PM UTC 24 |
| Finished | Sep 01 11:20:17 PM UTC 24 |
| Peak memory | 216656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460411573 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.460411573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.3870522231 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 343486993 ps |
| CPU time | 10.53 seconds |
| Started | Sep 01 11:20:09 PM UTC 24 |
| Finished | Sep 01 11:20:20 PM UTC 24 |
| Peak memory | 231888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870522231 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3870522231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.4181882341 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 144311422 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 11:20:09 PM UTC 24 |
| Finished | Sep 01 11:20:12 PM UTC 24 |
| Peak memory | 229452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181882341 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.4181882341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.1353550420 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 59647217 ps |
| CPU time | 4.6 seconds |
| Started | Sep 01 11:20:09 PM UTC 24 |
| Finished | Sep 01 11:20:14 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353550420 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1353550420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.2431612956 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 211190892 ps |
| CPU time | 11.84 seconds |
| Started | Sep 01 11:20:11 PM UTC 24 |
| Finished | Sep 01 11:20:24 PM UTC 24 |
| Peak memory | 229828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431612956 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2431612956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.2489461266 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 222012874 ps |
| CPU time | 10.12 seconds |
| Started | Sep 01 11:20:13 PM UTC 24 |
| Finished | Sep 01 11:20:24 PM UTC 24 |
| Peak memory | 237516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489461266 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_to ken_digest.2489461266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.1119429520 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 1226409987 ps |
| CPU time | 8.47 seconds |
| Started | Sep 01 11:20:11 PM UTC 24 |
| Finished | Sep 01 11:20:21 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119429520 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token _mux.1119429520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.1572684508 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 262968213 ps |
| CPU time | 10.46 seconds |
| Started | Sep 01 11:20:09 PM UTC 24 |
| Finished | Sep 01 11:20:20 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572684508 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1572684508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.106248661 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 71619704 ps |
| CPU time | 3.44 seconds |
| Started | Sep 01 11:20:05 PM UTC 24 |
| Finished | Sep 01 11:20:10 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106248661 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.106248661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.2262787127 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 972602877 ps |
| CPU time | 46.69 seconds |
| Started | Sep 01 11:20:06 PM UTC 24 |
| Finished | Sep 01 11:20:55 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262787127 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2262787127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.2839688846 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 74829438 ps |
| CPU time | 4.66 seconds |
| Started | Sep 01 11:20:08 PM UTC 24 |
| Finished | Sep 01 11:20:13 PM UTC 24 |
| Peak memory | 232208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839688846 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2839688846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.3974192751 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 9501955388 ps |
| CPU time | 157.69 seconds |
| Started | Sep 01 11:20:13 PM UTC 24 |
| Finished | Sep 01 11:22:54 PM UTC 24 |
| Peak memory | 280992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3974192751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 48.lc_ctrl_stress_all.3974192751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.121353608 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 20595813 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 11:20:05 PM UTC 24 |
| Finished | Sep 01 11:20:08 PM UTC 24 |
| Peak memory | 228744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121353608 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48. lc_ctrl_volatile_unlock_smoke.121353608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.3697251587 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 20692763 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 11:20:22 PM UTC 24 |
| Finished | Sep 01 11:20:24 PM UTC 24 |
| Peak memory | 217192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697251587 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3697251587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.910856794 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 585441479 ps |
| CPU time | 14.57 seconds |
| Started | Sep 01 11:20:17 PM UTC 24 |
| Finished | Sep 01 11:20:33 PM UTC 24 |
| Peak memory | 231948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910856794 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.910856794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.3979496535 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 364049977 ps |
| CPU time | 2.53 seconds |
| Started | Sep 01 11:20:18 PM UTC 24 |
| Finished | Sep 01 11:20:22 PM UTC 24 |
| Peak memory | 229840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979496535 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3979496535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.1708908234 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 116894086 ps |
| CPU time | 4.21 seconds |
| Started | Sep 01 11:20:16 PM UTC 24 |
| Finished | Sep 01 11:20:21 PM UTC 24 |
| Peak memory | 232020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708908234 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1708908234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.3357077727 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 403958220 ps |
| CPU time | 18.31 seconds |
| Started | Sep 01 11:20:20 PM UTC 24 |
| Finished | Sep 01 11:20:40 PM UTC 24 |
| Peak memory | 237920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357077727 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3357077727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.2547705978 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 1090129492 ps |
| CPU time | 16.43 seconds |
| Started | Sep 01 11:20:22 PM UTC 24 |
| Finished | Sep 01 11:20:40 PM UTC 24 |
| Peak memory | 237588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547705978 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_to ken_digest.2547705978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.2338221494 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1338739868 ps |
| CPU time | 13.67 seconds |
| Started | Sep 01 11:20:20 PM UTC 24 |
| Finished | Sep 01 11:20:36 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338221494 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token _mux.2338221494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.94849817 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 1184605809 ps |
| CPU time | 9.81 seconds |
| Started | Sep 01 11:20:17 PM UTC 24 |
| Finished | Sep 01 11:20:28 PM UTC 24 |
| Peak memory | 237940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94849817 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.94849817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.3147334172 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 259718612 ps |
| CPU time | 5.5 seconds |
| Started | Sep 01 11:20:14 PM UTC 24 |
| Finished | Sep 01 11:20:21 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147334172 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3147334172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.418731627 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 530715201 ps |
| CPU time | 42.44 seconds |
| Started | Sep 01 11:20:14 PM UTC 24 |
| Finished | Sep 01 11:20:58 PM UTC 24 |
| Peak memory | 260788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418731627 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.418731627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.2768023945 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 511668693 ps |
| CPU time | 8.04 seconds |
| Started | Sep 01 11:20:16 PM UTC 24 |
| Finished | Sep 01 11:20:25 PM UTC 24 |
| Peak memory | 234264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768023945 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2768023945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.2737453234 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 5679507987 ps |
| CPU time | 132.82 seconds |
| Started | Sep 01 11:20:22 PM UTC 24 |
| Finished | Sep 01 11:22:37 PM UTC 24 |
| Peak memory | 237648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2737453234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 49.lc_ctrl_stress_all.2737453234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.829290616 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 2392316110 ps |
| CPU time | 90.12 seconds |
| Started | Sep 01 11:20:22 PM UTC 24 |
| Finished | Sep 01 11:21:54 PM UTC 24 |
| Peak memory | 285336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829290616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.829290616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2133608167 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 20533609 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 11:20:14 PM UTC 24 |
| Finished | Sep 01 11:20:17 PM UTC 24 |
| Peak memory | 222384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133608167 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49 .lc_ctrl_volatile_unlock_smoke.2133608167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.2580452019 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 13309503 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 11:11:18 PM UTC 24 |
| Finished | Sep 01 11:11:20 PM UTC 24 |
| Peak memory | 217312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580452019 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2580452019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.443341360 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 395700534 ps |
| CPU time | 17.3 seconds |
| Started | Sep 01 11:11:01 PM UTC 24 |
| Finished | Sep 01 11:11:19 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443341360 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.443341360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.530115631 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 600496021 ps |
| CPU time | 17.76 seconds |
| Started | Sep 01 11:11:09 PM UTC 24 |
| Finished | Sep 01 11:11:28 PM UTC 24 |
| Peak memory | 229860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530115631 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.530115631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.798021440 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 6850838749 ps |
| CPU time | 104.36 seconds |
| Started | Sep 01 11:11:08 PM UTC 24 |
| Finished | Sep 01 11:12:55 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798021440 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta g_errors.798021440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.3598461574 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 242800821 ps |
| CPU time | 5.65 seconds |
| Started | Sep 01 11:11:10 PM UTC 24 |
| Finished | Sep 01 11:11:17 PM UTC 24 |
| Peak memory | 229660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598461574 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_prior ity.3598461574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.2355760679 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 660451346 ps |
| CPU time | 5.16 seconds |
| Started | Sep 01 11:11:07 PM UTC 24 |
| Finished | Sep 01 11:11:13 PM UTC 24 |
| Peak memory | 233856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355760679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl _jtag_prog_failure.2355760679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3071665904 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1340823699 ps |
| CPU time | 14.12 seconds |
| Started | Sep 01 11:11:12 PM UTC 24 |
| Finished | Sep 01 11:11:27 PM UTC 24 |
| Peak memory | 229504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071665904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ ctrl_jtag_regwen_during_op.3071665904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.2587939331 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 498168475 ps |
| CPU time | 10.34 seconds |
| Started | Sep 01 11:11:06 PM UTC 24 |
| Finished | Sep 01 11:11:17 PM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587939331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_s moke.2587939331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1153674283 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 628445266 ps |
| CPU time | 26.53 seconds |
| Started | Sep 01 11:11:07 PM UTC 24 |
| Finished | Sep 01 11:11:35 PM UTC 24 |
| Peak memory | 262516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153674283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ ctrl_jtag_state_post_trans.1153674283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.4020976091 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 298145056 ps |
| CPU time | 4.18 seconds |
| Started | Sep 01 11:11:01 PM UTC 24 |
| Finished | Sep 01 11:11:06 PM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020976091 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.4020976091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.2668864076 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1406155242 ps |
| CPU time | 21.54 seconds |
| Started | Sep 01 11:11:03 PM UTC 24 |
| Finished | Sep 01 11:11:26 PM UTC 24 |
| Peak memory | 229652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668864076 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2668864076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.2689416147 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 567929631 ps |
| CPU time | 28.78 seconds |
| Started | Sep 01 11:11:12 PM UTC 24 |
| Finished | Sep 01 11:11:42 PM UTC 24 |
| Peak memory | 237668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689416147 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2689416147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.1927260620 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1962363595 ps |
| CPU time | 19.5 seconds |
| Started | Sep 01 11:11:13 PM UTC 24 |
| Finished | Sep 01 11:11:34 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927260620 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_tok en_digest.1927260620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.275138193 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 234343913 ps |
| CPU time | 11.27 seconds |
| Started | Sep 01 11:11:12 PM UTC 24 |
| Finished | Sep 01 11:11:24 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275138193 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.275138193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.2696155521 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 433528946 ps |
| CPU time | 13.61 seconds |
| Started | Sep 01 11:11:02 PM UTC 24 |
| Finished | Sep 01 11:11:17 PM UTC 24 |
| Peak memory | 231960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696155521 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2696155521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.357793510 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 40124450 ps |
| CPU time | 3.09 seconds |
| Started | Sep 01 11:10:56 PM UTC 24 |
| Finished | Sep 01 11:11:00 PM UTC 24 |
| Peak memory | 225480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357793510 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.357793510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.598332436 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 185268669 ps |
| CPU time | 3.97 seconds |
| Started | Sep 01 11:11:01 PM UTC 24 |
| Finished | Sep 01 11:11:06 PM UTC 24 |
| Peak memory | 238192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598332436 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.598332436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.932982394 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 4894434888 ps |
| CPU time | 178.27 seconds |
| Started | Sep 01 11:11:14 PM UTC 24 |
| Finished | Sep 01 11:14:15 PM UTC 24 |
| Peak memory | 285260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=932982394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 5.lc_ctrl_stress_all.932982394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2322539209 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 85448990 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 11:10:57 PM UTC 24 |
| Finished | Sep 01 11:11:00 PM UTC 24 |
| Peak memory | 228692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322539209 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5. lc_ctrl_volatile_unlock_smoke.2322539209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.372414669 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 78232701 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 11:11:38 PM UTC 24 |
| Finished | Sep 01 11:11:40 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372414669 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.372414669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.467587296 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 29098803 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 11:11:26 PM UTC 24 |
| Finished | Sep 01 11:11:29 PM UTC 24 |
| Peak memory | 218648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467587296 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.467587296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.53401137 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 271560593 ps |
| CPU time | 12.49 seconds |
| Started | Sep 01 11:11:24 PM UTC 24 |
| Finished | Sep 01 11:11:37 PM UTC 24 |
| Peak memory | 237592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53401137 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.53401137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.4210494827 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 603597802 ps |
| CPU time | 6.61 seconds |
| Started | Sep 01 11:11:31 PM UTC 24 |
| Finished | Sep 01 11:11:39 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210494827 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.4210494827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.1654265394 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1912949884 ps |
| CPU time | 44.21 seconds |
| Started | Sep 01 11:11:31 PM UTC 24 |
| Finished | Sep 01 11:12:17 PM UTC 24 |
| Peak memory | 231812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654265394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jt ag_errors.1654265394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.1742135167 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 184381821 ps |
| CPU time | 4.86 seconds |
| Started | Sep 01 11:11:31 PM UTC 24 |
| Finished | Sep 01 11:11:37 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742135167 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_prior ity.1742135167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2924529030 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1469606167 ps |
| CPU time | 12.79 seconds |
| Started | Sep 01 11:11:30 PM UTC 24 |
| Finished | Sep 01 11:11:43 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924529030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl _jtag_prog_failure.2924529030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3703105181 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 651521684 ps |
| CPU time | 23.5 seconds |
| Started | Sep 01 11:11:33 PM UTC 24 |
| Finished | Sep 01 11:11:58 PM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703105181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ ctrl_jtag_regwen_during_op.3703105181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.3464567771 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 863682328 ps |
| CPU time | 6.6 seconds |
| Started | Sep 01 11:11:27 PM UTC 24 |
| Finished | Sep 01 11:11:35 PM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464567771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_s moke.3464567771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.355963121 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2282478558 ps |
| CPU time | 67.7 seconds |
| Started | Sep 01 11:11:27 PM UTC 24 |
| Finished | Sep 01 11:12:37 PM UTC 24 |
| Peak memory | 287416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355963121 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl _jtag_state_failure.355963121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3674789356 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 741561075 ps |
| CPU time | 22.73 seconds |
| Started | Sep 01 11:11:28 PM UTC 24 |
| Finished | Sep 01 11:11:52 PM UTC 24 |
| Peak memory | 262436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674789356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ ctrl_jtag_state_post_trans.3674789356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.3600523105 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 104165039 ps |
| CPU time | 2.54 seconds |
| Started | Sep 01 11:11:22 PM UTC 24 |
| Finished | Sep 01 11:11:25 PM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600523105 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3600523105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.2970107424 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 3448562655 ps |
| CPU time | 31.92 seconds |
| Started | Sep 01 11:11:25 PM UTC 24 |
| Finished | Sep 01 11:11:58 PM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970107424 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2970107424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3367912574 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 971111161 ps |
| CPU time | 20.1 seconds |
| Started | Sep 01 11:11:33 PM UTC 24 |
| Finished | Sep 01 11:11:55 PM UTC 24 |
| Peak memory | 237924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367912574 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3367912574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2113766902 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1008361587 ps |
| CPU time | 13.33 seconds |
| Started | Sep 01 11:11:36 PM UTC 24 |
| Finished | Sep 01 11:11:50 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113766902 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_tok en_digest.2113766902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.2888677253 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 315780194 ps |
| CPU time | 16.58 seconds |
| Started | Sep 01 11:11:35 PM UTC 24 |
| Finished | Sep 01 11:11:52 PM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888677253 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_ mux.2888677253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.1456213058 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1114269835 ps |
| CPU time | 15.11 seconds |
| Started | Sep 01 11:11:25 PM UTC 24 |
| Finished | Sep 01 11:11:41 PM UTC 24 |
| Peak memory | 237400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456213058 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1456213058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.1692725349 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 189070880 ps |
| CPU time | 3.5 seconds |
| Started | Sep 01 11:11:18 PM UTC 24 |
| Finished | Sep 01 11:11:23 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692725349 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1692725349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1560452810 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 1057097344 ps |
| CPU time | 27.98 seconds |
| Started | Sep 01 11:11:21 PM UTC 24 |
| Finished | Sep 01 11:11:50 PM UTC 24 |
| Peak memory | 262508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560452810 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1560452810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.1542259853 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 58828903 ps |
| CPU time | 9.73 seconds |
| Started | Sep 01 11:11:22 PM UTC 24 |
| Finished | Sep 01 11:11:32 PM UTC 24 |
| Peak memory | 262584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542259853 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1542259853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.768717184 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 16548097341 ps |
| CPU time | 135.1 seconds |
| Started | Sep 01 11:11:36 PM UTC 24 |
| Finished | Sep 01 11:13:54 PM UTC 24 |
| Peak memory | 236360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=768717184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 6.lc_ctrl_stress_all.768717184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2763651491 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 41703310 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 11:11:18 PM UTC 24 |
| Finished | Sep 01 11:11:20 PM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763651491 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6. lc_ctrl_volatile_unlock_smoke.2763651491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.930305548 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 18365735 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 11:12:01 PM UTC 24 |
| Finished | Sep 01 11:12:03 PM UTC 24 |
| Peak memory | 218824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930305548 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.930305548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.3326973513 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 19577268 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 11:11:50 PM UTC 24 |
| Finished | Sep 01 11:11:52 PM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326973513 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3326973513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.1886658086 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 930577148 ps |
| CPU time | 13.67 seconds |
| Started | Sep 01 11:11:45 PM UTC 24 |
| Finished | Sep 01 11:11:59 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886658086 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1886658086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1143084798 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1497272493 ps |
| CPU time | 9 seconds |
| Started | Sep 01 11:11:54 PM UTC 24 |
| Finished | Sep 01 11:12:04 PM UTC 24 |
| Peak memory | 229620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143084798 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1143084798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3673416800 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1546528599 ps |
| CPU time | 35.3 seconds |
| Started | Sep 01 11:11:54 PM UTC 24 |
| Finished | Sep 01 11:12:30 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673416800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jt ag_errors.3673416800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.259796939 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3999579479 ps |
| CPU time | 11.3 seconds |
| Started | Sep 01 11:11:54 PM UTC 24 |
| Finished | Sep 01 11:12:06 PM UTC 24 |
| Peak memory | 229680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259796939 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.259796939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1424149869 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 383599313 ps |
| CPU time | 8.39 seconds |
| Started | Sep 01 11:11:54 PM UTC 24 |
| Finished | Sep 01 11:12:03 PM UTC 24 |
| Peak memory | 235904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424149869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl _jtag_prog_failure.1424149869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.490843207 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3673785813 ps |
| CPU time | 15.47 seconds |
| Started | Sep 01 11:11:54 PM UTC 24 |
| Finished | Sep 01 11:12:11 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490843207 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_c trl_jtag_regwen_during_op.490843207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.2676449050 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2956464175 ps |
| CPU time | 12.47 seconds |
| Started | Sep 01 11:11:50 PM UTC 24 |
| Finished | Sep 01 11:12:04 PM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676449050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_s moke.2676449050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.4043209914 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 10249220174 ps |
| CPU time | 68.13 seconds |
| Started | Sep 01 11:11:51 PM UTC 24 |
| Finished | Sep 01 11:13:01 PM UTC 24 |
| Peak memory | 287208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043209914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr l_jtag_state_failure.4043209914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.852397625 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1728423592 ps |
| CPU time | 19.43 seconds |
| Started | Sep 01 11:11:51 PM UTC 24 |
| Finished | Sep 01 11:12:12 PM UTC 24 |
| Peak memory | 262512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852397625 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_c trl_jtag_state_post_trans.852397625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.866011289 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 256675376 ps |
| CPU time | 3.84 seconds |
| Started | Sep 01 11:11:45 PM UTC 24 |
| Finished | Sep 01 11:11:50 PM UTC 24 |
| Peak memory | 236292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866011289 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.866011289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.1805921699 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 366480313 ps |
| CPU time | 10.27 seconds |
| Started | Sep 01 11:11:45 PM UTC 24 |
| Finished | Sep 01 11:11:56 PM UTC 24 |
| Peak memory | 225868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805921699 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1805921699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.2058490986 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 247394445 ps |
| CPU time | 11.72 seconds |
| Started | Sep 01 11:11:55 PM UTC 24 |
| Finished | Sep 01 11:12:08 PM UTC 24 |
| Peak memory | 237732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058490986 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2058490986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.195210937 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2297632870 ps |
| CPU time | 15.69 seconds |
| Started | Sep 01 11:11:57 PM UTC 24 |
| Finished | Sep 01 11:12:14 PM UTC 24 |
| Peak memory | 237588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195210937 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_toke n_digest.195210937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.3459763107 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 234021981 ps |
| CPU time | 12.5 seconds |
| Started | Sep 01 11:11:55 PM UTC 24 |
| Finished | Sep 01 11:12:09 PM UTC 24 |
| Peak memory | 231888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459763107 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_ mux.3459763107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.726401586 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 540077827 ps |
| CPU time | 8.58 seconds |
| Started | Sep 01 11:11:45 PM UTC 24 |
| Finished | Sep 01 11:11:54 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726401586 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.726401586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3995292267 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 34652134 ps |
| CPU time | 3.26 seconds |
| Started | Sep 01 11:11:39 PM UTC 24 |
| Finished | Sep 01 11:11:43 PM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995292267 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3995292267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3571574823 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 296133765 ps |
| CPU time | 27.58 seconds |
| Started | Sep 01 11:11:42 PM UTC 24 |
| Finished | Sep 01 11:12:11 PM UTC 24 |
| Peak memory | 262832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571574823 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3571574823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3813203676 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 90223165 ps |
| CPU time | 9.51 seconds |
| Started | Sep 01 11:11:43 PM UTC 24 |
| Finished | Sep 01 11:11:53 PM UTC 24 |
| Peak memory | 260448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813203676 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3813203676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.395123554 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 31145518551 ps |
| CPU time | 224.78 seconds |
| Started | Sep 01 11:11:58 PM UTC 24 |
| Finished | Sep 01 11:15:47 PM UTC 24 |
| Peak memory | 326584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=395123554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 7.lc_ctrl_stress_all.395123554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3854775683 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 15787159 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 11:11:41 PM UTC 24 |
| Finished | Sep 01 11:11:44 PM UTC 24 |
| Peak memory | 218236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854775683 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7. lc_ctrl_volatile_unlock_smoke.3854775683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.3563170245 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 108287637 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 11:12:22 PM UTC 24 |
| Finished | Sep 01 11:12:24 PM UTC 24 |
| Peak memory | 218644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563170245 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3563170245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.181291285 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 16920659 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 11:12:10 PM UTC 24 |
| Finished | Sep 01 11:12:12 PM UTC 24 |
| Peak memory | 218492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181291285 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.181291285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.586859963 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 5150789280 ps |
| CPU time | 22.42 seconds |
| Started | Sep 01 11:12:07 PM UTC 24 |
| Finished | Sep 01 11:12:31 PM UTC 24 |
| Peak memory | 229960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586859963 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.586859963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.3959534434 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 73309723 ps |
| CPU time | 3.23 seconds |
| Started | Sep 01 11:12:14 PM UTC 24 |
| Finished | Sep 01 11:12:19 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959534434 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3959534434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.2409227420 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2658322742 ps |
| CPU time | 44.62 seconds |
| Started | Sep 01 11:12:13 PM UTC 24 |
| Finished | Sep 01 11:12:59 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409227420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jt ag_errors.2409227420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3143724938 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1948692709 ps |
| CPU time | 9.15 seconds |
| Started | Sep 01 11:12:16 PM UTC 24 |
| Finished | Sep 01 11:12:26 PM UTC 24 |
| Peak memory | 229640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143724938 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_prior ity.3143724938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.1691168743 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 151215070 ps |
| CPU time | 6.59 seconds |
| Started | Sep 01 11:12:13 PM UTC 24 |
| Finished | Sep 01 11:12:21 PM UTC 24 |
| Peak memory | 231808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691168743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl _jtag_prog_failure.1691168743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.256238113 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 928490487 ps |
| CPU time | 19.77 seconds |
| Started | Sep 01 11:12:16 PM UTC 24 |
| Finished | Sep 01 11:12:37 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256238113 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_c trl_jtag_regwen_during_op.256238113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1626132620 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 970767349 ps |
| CPU time | 9.2 seconds |
| Started | Sep 01 11:12:10 PM UTC 24 |
| Finished | Sep 01 11:12:20 PM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626132620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_s moke.1626132620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.368212003 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 6720318189 ps |
| CPU time | 61.2 seconds |
| Started | Sep 01 11:12:12 PM UTC 24 |
| Finished | Sep 01 11:13:15 PM UTC 24 |
| Peak memory | 281008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368212003 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl _jtag_state_failure.368212003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3813991513 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1713470231 ps |
| CPU time | 15.88 seconds |
| Started | Sep 01 11:12:12 PM UTC 24 |
| Finished | Sep 01 11:12:29 PM UTC 24 |
| Peak memory | 262436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813991513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ ctrl_jtag_state_post_trans.3813991513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.740248254 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 351014126 ps |
| CPU time | 5.67 seconds |
| Started | Sep 01 11:12:07 PM UTC 24 |
| Finished | Sep 01 11:12:14 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740248254 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.740248254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.1469673688 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 202221471 ps |
| CPU time | 10.04 seconds |
| Started | Sep 01 11:12:09 PM UTC 24 |
| Finished | Sep 01 11:12:20 PM UTC 24 |
| Peak memory | 225556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469673688 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1469673688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.666675984 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 1856231454 ps |
| CPU time | 19.09 seconds |
| Started | Sep 01 11:12:18 PM UTC 24 |
| Finished | Sep 01 11:12:38 PM UTC 24 |
| Peak memory | 237580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666675984 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.666675984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.1770819650 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 410275970 ps |
| CPU time | 15.27 seconds |
| Started | Sep 01 11:12:20 PM UTC 24 |
| Finished | Sep 01 11:12:37 PM UTC 24 |
| Peak memory | 231812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770819650 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_tok en_digest.1770819650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.3448828778 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 231497166 ps |
| CPU time | 10.35 seconds |
| Started | Sep 01 11:12:20 PM UTC 24 |
| Finished | Sep 01 11:12:32 PM UTC 24 |
| Peak memory | 237596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448828778 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_ mux.3448828778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.526847 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1328432896 ps |
| CPU time | 10.55 seconds |
| Started | Sep 01 11:12:09 PM UTC 24 |
| Finished | Sep 01 11:12:20 PM UTC 24 |
| Peak memory | 231792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.526847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.2003321151 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 37229000 ps |
| CPU time | 4.05 seconds |
| Started | Sep 01 11:12:04 PM UTC 24 |
| Finished | Sep 01 11:12:09 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003321151 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2003321151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.2197358070 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1196715235 ps |
| CPU time | 36.67 seconds |
| Started | Sep 01 11:12:05 PM UTC 24 |
| Finished | Sep 01 11:12:43 PM UTC 24 |
| Peak memory | 262508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197358070 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2197358070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.781842333 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 68344854 ps |
| CPU time | 9.01 seconds |
| Started | Sep 01 11:12:05 PM UTC 24 |
| Finished | Sep 01 11:12:15 PM UTC 24 |
| Peak memory | 262460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781842333 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.781842333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.1418749457 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 4407382540 ps |
| CPU time | 121.51 seconds |
| Started | Sep 01 11:12:21 PM UTC 24 |
| Finished | Sep 01 11:14:25 PM UTC 24 |
| Peak memory | 287484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1418749457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 8.lc_ctrl_stress_all.1418749457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.4111712970 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 4269363421 ps |
| CPU time | 195.82 seconds |
| Started | Sep 01 11:12:22 PM UTC 24 |
| Finished | Sep 01 11:15:40 PM UTC 24 |
| Peak memory | 279088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111712970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.4111712970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1162716419 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 40323852 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 11:12:04 PM UTC 24 |
| Finished | Sep 01 11:12:06 PM UTC 24 |
| Peak memory | 228692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162716419 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8. lc_ctrl_volatile_unlock_smoke.1162716419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3671669402 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 18803060 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 11:12:44 PM UTC 24 |
| Finished | Sep 01 11:12:47 PM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671669402 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3671669402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3301734393 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 13980978 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 11:12:32 PM UTC 24 |
| Finished | Sep 01 11:12:34 PM UTC 24 |
| Peak memory | 216996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301734393 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3301734393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.4241851938 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1235625992 ps |
| CPU time | 12.72 seconds |
| Started | Sep 01 11:12:26 PM UTC 24 |
| Finished | Sep 01 11:12:40 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241851938 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.4241851938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3478026231 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1280596126 ps |
| CPU time | 4.6 seconds |
| Started | Sep 01 11:12:38 PM UTC 24 |
| Finished | Sep 01 11:12:44 PM UTC 24 |
| Peak memory | 229668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478026231 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3478026231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.3429957679 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 35770543470 ps |
| CPU time | 80.95 seconds |
| Started | Sep 01 11:12:35 PM UTC 24 |
| Finished | Sep 01 11:13:58 PM UTC 24 |
| Peak memory | 237584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429957679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jt ag_errors.3429957679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.834120393 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 236875875 ps |
| CPU time | 5.01 seconds |
| Started | Sep 01 11:12:38 PM UTC 24 |
| Finished | Sep 01 11:12:45 PM UTC 24 |
| Peak memory | 230000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834120393 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.834120393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.257413290 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1160552825 ps |
| CPU time | 21.83 seconds |
| Started | Sep 01 11:12:35 PM UTC 24 |
| Finished | Sep 01 11:12:59 PM UTC 24 |
| Peak memory | 231824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257413290 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_ jtag_prog_failure.257413290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2299978719 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 707183585 ps |
| CPU time | 15.99 seconds |
| Started | Sep 01 11:12:38 PM UTC 24 |
| Finished | Sep 01 11:12:56 PM UTC 24 |
| Peak memory | 229828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299978719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ ctrl_jtag_regwen_during_op.2299978719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.3533522272 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 218350124 ps |
| CPU time | 6.12 seconds |
| Started | Sep 01 11:12:32 PM UTC 24 |
| Finished | Sep 01 11:12:39 PM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533522272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_s moke.3533522272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.1537895656 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 8025159618 ps |
| CPU time | 35.21 seconds |
| Started | Sep 01 11:12:32 PM UTC 24 |
| Finished | Sep 01 11:13:09 PM UTC 24 |
| Peak memory | 262504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537895656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr l_jtag_state_failure.1537895656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.2160503613 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 318685798 ps |
| CPU time | 21.01 seconds |
| Started | Sep 01 11:12:33 PM UTC 24 |
| Finished | Sep 01 11:12:55 PM UTC 24 |
| Peak memory | 260392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160503613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ ctrl_jtag_state_post_trans.2160503613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.1671128318 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 95175948 ps |
| CPU time | 3.51 seconds |
| Started | Sep 01 11:12:25 PM UTC 24 |
| Finished | Sep 01 11:12:30 PM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671128318 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1671128318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.4240602737 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 650207041 ps |
| CPU time | 15.72 seconds |
| Started | Sep 01 11:12:30 PM UTC 24 |
| Finished | Sep 01 11:12:47 PM UTC 24 |
| Peak memory | 229564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240602737 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.4240602737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.1485904120 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1377906883 ps |
| CPU time | 20.59 seconds |
| Started | Sep 01 11:12:38 PM UTC 24 |
| Finished | Sep 01 11:13:01 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485904120 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1485904120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2868114761 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 276353877 ps |
| CPU time | 8.61 seconds |
| Started | Sep 01 11:12:40 PM UTC 24 |
| Finished | Sep 01 11:12:50 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868114761 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_tok en_digest.2868114761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.2114104043 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1296179911 ps |
| CPU time | 10.79 seconds |
| Started | Sep 01 11:12:39 PM UTC 24 |
| Finished | Sep 01 11:12:50 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114104043 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_ mux.2114104043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.2161399999 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 419573181 ps |
| CPU time | 8.75 seconds |
| Started | Sep 01 11:12:27 PM UTC 24 |
| Finished | Sep 01 11:12:37 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161399999 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2161399999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.399876597 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 86745366 ps |
| CPU time | 2.57 seconds |
| Started | Sep 01 11:12:22 PM UTC 24 |
| Finished | Sep 01 11:12:25 PM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399876597 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.399876597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.509344801 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 173920350 ps |
| CPU time | 35.42 seconds |
| Started | Sep 01 11:12:24 PM UTC 24 |
| Finished | Sep 01 11:13:01 PM UTC 24 |
| Peak memory | 262580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509344801 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.509344801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.3176757517 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 331745962 ps |
| CPU time | 10.4 seconds |
| Started | Sep 01 11:12:25 PM UTC 24 |
| Finished | Sep 01 11:12:37 PM UTC 24 |
| Peak memory | 262748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176757517 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3176757517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3405625584 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 971394015 ps |
| CPU time | 45.04 seconds |
| Started | Sep 01 11:12:40 PM UTC 24 |
| Finished | Sep 01 11:13:27 PM UTC 24 |
| Peak memory | 262832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3405625584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 9.lc_ctrl_stress_all.3405625584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1999538995 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 15933950 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 11:12:22 PM UTC 24 |
| Finished | Sep 01 11:12:24 PM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999538995 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9. lc_ctrl_volatile_unlock_smoke.1999538995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_volatile_unlock_smoke/latest |
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