| T816 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.1184914073 |
|
|
Sep 01 11:19:57 PM UTC 24 |
Sep 01 11:20:06 PM UTC 24 |
180217678 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.3739531260 |
|
|
Sep 01 11:20:00 PM UTC 24 |
Sep 01 11:20:07 PM UTC 24 |
1294651032 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.1173125076 |
|
|
Sep 01 11:19:56 PM UTC 24 |
Sep 01 11:20:08 PM UTC 24 |
494492173 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.984674069 |
|
|
Sep 01 11:20:05 PM UTC 24 |
Sep 01 11:20:08 PM UTC 24 |
68528302 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.3569018852 |
|
|
Sep 01 11:19:52 PM UTC 24 |
Sep 01 11:20:08 PM UTC 24 |
458878272 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.121353608 |
|
|
Sep 01 11:20:05 PM UTC 24 |
Sep 01 11:20:08 PM UTC 24 |
20595813 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.106248661 |
|
|
Sep 01 11:20:05 PM UTC 24 |
Sep 01 11:20:10 PM UTC 24 |
71619704 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.3741192744 |
|
|
Sep 01 11:20:00 PM UTC 24 |
Sep 01 11:20:11 PM UTC 24 |
657653318 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.1488903535 |
|
|
Sep 01 11:19:59 PM UTC 24 |
Sep 01 11:20:11 PM UTC 24 |
127209184 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.4179244490 |
|
|
Sep 01 11:18:15 PM UTC 24 |
Sep 01 11:20:12 PM UTC 24 |
16993225100 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.4181882341 |
|
|
Sep 01 11:20:09 PM UTC 24 |
Sep 01 11:20:12 PM UTC 24 |
144311422 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.3692496791 |
|
|
Sep 01 11:18:07 PM UTC 24 |
Sep 01 11:20:12 PM UTC 24 |
7719497486 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.1448151052 |
|
|
Sep 01 11:19:35 PM UTC 24 |
Sep 01 11:20:13 PM UTC 24 |
847877277 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.204703856 |
|
|
Sep 01 11:19:46 PM UTC 24 |
Sep 01 11:20:13 PM UTC 24 |
1890011189 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.2839688846 |
|
|
Sep 01 11:20:08 PM UTC 24 |
Sep 01 11:20:13 PM UTC 24 |
74829438 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.2223184913 |
|
|
Sep 01 11:19:45 PM UTC 24 |
Sep 01 11:20:14 PM UTC 24 |
221370212 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.1353550420 |
|
|
Sep 01 11:20:09 PM UTC 24 |
Sep 01 11:20:14 PM UTC 24 |
59647217 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.3006591021 |
|
|
Sep 01 11:19:59 PM UTC 24 |
Sep 01 11:20:16 PM UTC 24 |
386216084 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.460411573 |
|
|
Sep 01 11:20:14 PM UTC 24 |
Sep 01 11:20:17 PM UTC 24 |
13868364 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2133608167 |
|
|
Sep 01 11:20:14 PM UTC 24 |
Sep 01 11:20:17 PM UTC 24 |
20533609 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.4293670050 |
|
|
Sep 01 11:19:55 PM UTC 24 |
Sep 01 11:20:19 PM UTC 24 |
846578879 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.2664737100 |
|
|
Sep 01 11:17:19 PM UTC 24 |
Sep 01 11:20:19 PM UTC 24 |
11111843763 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.1758068464 |
|
|
Sep 01 11:20:01 PM UTC 24 |
Sep 01 11:20:20 PM UTC 24 |
315906872 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.3528513829 |
|
|
Sep 01 11:19:52 PM UTC 24 |
Sep 01 11:20:20 PM UTC 24 |
788390548 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.1572684508 |
|
|
Sep 01 11:20:09 PM UTC 24 |
Sep 01 11:20:20 PM UTC 24 |
262968213 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.3787945784 |
|
|
Sep 01 11:20:04 PM UTC 24 |
Sep 01 11:20:20 PM UTC 24 |
448073214 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.3870522231 |
|
|
Sep 01 11:20:09 PM UTC 24 |
Sep 01 11:20:20 PM UTC 24 |
343486993 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.1119429520 |
|
|
Sep 01 11:20:11 PM UTC 24 |
Sep 01 11:20:21 PM UTC 24 |
1226409987 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.3147334172 |
|
|
Sep 01 11:20:14 PM UTC 24 |
Sep 01 11:20:21 PM UTC 24 |
259718612 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.1708908234 |
|
|
Sep 01 11:20:16 PM UTC 24 |
Sep 01 11:20:21 PM UTC 24 |
116894086 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.3979496535 |
|
|
Sep 01 11:20:18 PM UTC 24 |
Sep 01 11:20:22 PM UTC 24 |
364049977 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.2489461266 |
|
|
Sep 01 11:20:13 PM UTC 24 |
Sep 01 11:20:24 PM UTC 24 |
222012874 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.2431612956 |
|
|
Sep 01 11:20:11 PM UTC 24 |
Sep 01 11:20:24 PM UTC 24 |
211190892 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.3697251587 |
|
|
Sep 01 11:20:22 PM UTC 24 |
Sep 01 11:20:24 PM UTC 24 |
20692763 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.2768023945 |
|
|
Sep 01 11:20:16 PM UTC 24 |
Sep 01 11:20:25 PM UTC 24 |
511668693 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.2558519326 |
|
|
Sep 01 11:19:55 PM UTC 24 |
Sep 01 11:20:25 PM UTC 24 |
825968955 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1032198481 |
|
|
Sep 01 11:19:59 PM UTC 24 |
Sep 01 11:20:26 PM UTC 24 |
205462132 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.2459191634 |
|
|
Sep 01 11:18:43 PM UTC 24 |
Sep 01 11:20:26 PM UTC 24 |
2873238932 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.94849817 |
|
|
Sep 01 11:20:17 PM UTC 24 |
Sep 01 11:20:28 PM UTC 24 |
1184605809 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.3045450570 |
|
|
Sep 01 11:20:02 PM UTC 24 |
Sep 01 11:20:33 PM UTC 24 |
1539404480 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.910856794 |
|
|
Sep 01 11:20:17 PM UTC 24 |
Sep 01 11:20:33 PM UTC 24 |
585441479 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.2338221494 |
|
|
Sep 01 11:20:20 PM UTC 24 |
Sep 01 11:20:36 PM UTC 24 |
1338739868 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.2547705978 |
|
|
Sep 01 11:20:22 PM UTC 24 |
Sep 01 11:20:40 PM UTC 24 |
1090129492 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.3357077727 |
|
|
Sep 01 11:20:20 PM UTC 24 |
Sep 01 11:20:40 PM UTC 24 |
403958220 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.544915635 |
|
|
Sep 01 11:18:31 PM UTC 24 |
Sep 01 11:20:47 PM UTC 24 |
8485756677 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.1970869502 |
|
|
Sep 01 11:19:14 PM UTC 24 |
Sep 01 11:21:08 PM UTC 24 |
3030640823 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.3096359440 |
|
|
Sep 01 11:19:56 PM UTC 24 |
Sep 01 11:21:20 PM UTC 24 |
21925883013 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1593464244 |
|
|
Sep 01 11:20:04 PM UTC 24 |
Sep 01 11:21:28 PM UTC 24 |
3002728193 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.619743763 |
|
|
Sep 01 11:15:44 PM UTC 24 |
Sep 01 11:21:32 PM UTC 24 |
9156001267 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.2319015191 |
|
|
Sep 01 11:19:03 PM UTC 24 |
Sep 01 11:21:40 PM UTC 24 |
22926636267 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.1181135717 |
|
|
Sep 01 11:19:48 PM UTC 24 |
Sep 01 11:21:53 PM UTC 24 |
12594352200 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.829290616 |
|
|
Sep 01 11:20:22 PM UTC 24 |
Sep 01 11:21:54 PM UTC 24 |
2392316110 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.2617602681 |
|
|
Sep 01 11:19:21 PM UTC 24 |
Sep 01 11:22:06 PM UTC 24 |
4310422919 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.1202697224 |
|
|
Sep 01 11:19:21 PM UTC 24 |
Sep 01 11:22:15 PM UTC 24 |
7431234370 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.3015032478 |
|
|
Sep 01 11:19:31 PM UTC 24 |
Sep 01 11:22:21 PM UTC 24 |
7785712114 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.660929588 |
|
|
Sep 01 11:16:27 PM UTC 24 |
Sep 01 11:22:28 PM UTC 24 |
10290349390 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.2737453234 |
|
|
Sep 01 11:20:22 PM UTC 24 |
Sep 01 11:22:37 PM UTC 24 |
5679507987 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.1826548077 |
|
|
Sep 01 11:19:12 PM UTC 24 |
Sep 01 11:22:45 PM UTC 24 |
5678756281 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.2397609405 |
|
|
Sep 01 11:16:54 PM UTC 24 |
Sep 01 11:22:48 PM UTC 24 |
17416913845 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.3974192751 |
|
|
Sep 01 11:20:13 PM UTC 24 |
Sep 01 11:22:54 PM UTC 24 |
9501955388 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.1101642602 |
|
|
Sep 01 11:13:57 PM UTC 24 |
Sep 01 11:23:11 PM UTC 24 |
16504664627 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.2251931699 |
|
|
Sep 01 11:14:46 PM UTC 24 |
Sep 01 11:23:38 PM UTC 24 |
61159787472 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.3818795494 |
|
|
Sep 01 11:19:42 PM UTC 24 |
Sep 01 11:24:44 PM UTC 24 |
22977857393 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.247646733 |
|
|
Sep 01 11:20:04 PM UTC 24 |
Sep 01 11:25:44 PM UTC 24 |
29177763384 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.3739126883 |
|
|
Sep 01 11:17:59 PM UTC 24 |
Sep 01 11:30:29 PM UTC 24 |
82082815034 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.3731451592 |
|
|
Sep 01 11:19:42 PM UTC 24 |
Sep 01 11:31:58 PM UTC 24 |
23579404037 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2126554945 |
|
|
Sep 01 11:20:23 PM UTC 24 |
Sep 01 11:20:26 PM UTC 24 |
173303808 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3179799964 |
|
|
Sep 01 11:20:22 PM UTC 24 |
Sep 01 11:20:27 PM UTC 24 |
788804782 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.25708901 |
|
|
Sep 01 11:20:22 PM UTC 24 |
Sep 01 11:20:27 PM UTC 24 |
73638514 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1934620367 |
|
|
Sep 01 11:20:26 PM UTC 24 |
Sep 01 11:20:28 PM UTC 24 |
38668272 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2655477208 |
|
|
Sep 01 11:20:26 PM UTC 24 |
Sep 01 11:20:30 PM UTC 24 |
150437124 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1238794107 |
|
|
Sep 01 11:20:26 PM UTC 24 |
Sep 01 11:20:30 PM UTC 24 |
109760290 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1832791896 |
|
|
Sep 01 11:20:26 PM UTC 24 |
Sep 01 11:20:30 PM UTC 24 |
153469212 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3315116629 |
|
|
Sep 01 11:20:28 PM UTC 24 |
Sep 01 11:20:30 PM UTC 24 |
13683009 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4075921624 |
|
|
Sep 01 11:20:28 PM UTC 24 |
Sep 01 11:20:31 PM UTC 24 |
84437703 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2282702253 |
|
|
Sep 01 11:20:28 PM UTC 24 |
Sep 01 11:20:31 PM UTC 24 |
19749316 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.305148900 |
|
|
Sep 01 11:20:26 PM UTC 24 |
Sep 01 11:20:31 PM UTC 24 |
581551944 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4228274072 |
|
|
Sep 01 11:20:28 PM UTC 24 |
Sep 01 11:20:31 PM UTC 24 |
59301085 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.435005694 |
|
|
Sep 01 11:20:28 PM UTC 24 |
Sep 01 11:20:32 PM UTC 24 |
93939654 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.888659118 |
|
|
Sep 01 11:20:22 PM UTC 24 |
Sep 01 11:20:32 PM UTC 24 |
299998127 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3625167601 |
|
|
Sep 01 11:20:29 PM UTC 24 |
Sep 01 11:20:32 PM UTC 24 |
218231626 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2513526055 |
|
|
Sep 01 11:20:22 PM UTC 24 |
Sep 01 11:20:33 PM UTC 24 |
558741521 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2257442582 |
|
|
Sep 01 11:20:28 PM UTC 24 |
Sep 01 11:20:34 PM UTC 24 |
355561464 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1554675445 |
|
|
Sep 01 11:20:31 PM UTC 24 |
Sep 01 11:20:34 PM UTC 24 |
265609346 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2989764418 |
|
|
Sep 01 11:20:31 PM UTC 24 |
Sep 01 11:20:34 PM UTC 24 |
20835506 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1053742426 |
|
|
Sep 01 11:20:33 PM UTC 24 |
Sep 01 11:20:35 PM UTC 24 |
64513081 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2608463406 |
|
|
Sep 01 11:20:33 PM UTC 24 |
Sep 01 11:20:35 PM UTC 24 |
32775886 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.684771313 |
|
|
Sep 01 11:20:33 PM UTC 24 |
Sep 01 11:20:36 PM UTC 24 |
104057952 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1875350199 |
|
|
Sep 01 11:20:33 PM UTC 24 |
Sep 01 11:20:36 PM UTC 24 |
41716139 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.450449290 |
|
|
Sep 01 11:20:31 PM UTC 24 |
Sep 01 11:20:36 PM UTC 24 |
75007277 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1453648674 |
|
|
Sep 01 11:20:33 PM UTC 24 |
Sep 01 11:20:36 PM UTC 24 |
30697510 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.512529972 |
|
|
Sep 01 11:20:31 PM UTC 24 |
Sep 01 11:20:37 PM UTC 24 |
89020790 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.927365153 |
|
|
Sep 01 11:20:34 PM UTC 24 |
Sep 01 11:20:38 PM UTC 24 |
112821284 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3942962095 |
|
|
Sep 01 11:20:31 PM UTC 24 |
Sep 01 11:20:38 PM UTC 24 |
1624878163 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.813959632 |
|
|
Sep 01 11:20:34 PM UTC 24 |
Sep 01 11:20:38 PM UTC 24 |
290399210 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3887832924 |
|
|
Sep 01 11:20:29 PM UTC 24 |
Sep 01 11:20:38 PM UTC 24 |
2147839855 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2954084353 |
|
|
Sep 01 11:20:34 PM UTC 24 |
Sep 01 11:20:39 PM UTC 24 |
590481484 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3426951613 |
|
|
Sep 01 11:20:36 PM UTC 24 |
Sep 01 11:20:39 PM UTC 24 |
24767604 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2043228326 |
|
|
Sep 01 11:20:36 PM UTC 24 |
Sep 01 11:20:39 PM UTC 24 |
292376297 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4218121439 |
|
|
Sep 01 11:20:36 PM UTC 24 |
Sep 01 11:20:40 PM UTC 24 |
182758285 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1135375155 |
|
|
Sep 01 11:20:37 PM UTC 24 |
Sep 01 11:20:40 PM UTC 24 |
116170741 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3629387455 |
|
|
Sep 01 11:20:37 PM UTC 24 |
Sep 01 11:20:40 PM UTC 24 |
37799174 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.98158594 |
|
|
Sep 01 11:20:30 PM UTC 24 |
Sep 01 11:20:40 PM UTC 24 |
1155309213 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3532410053 |
|
|
Sep 01 11:20:37 PM UTC 24 |
Sep 01 11:20:40 PM UTC 24 |
48589919 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.4005153294 |
|
|
Sep 01 11:20:37 PM UTC 24 |
Sep 01 11:20:40 PM UTC 24 |
75361491 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1113627159 |
|
|
Sep 01 11:20:36 PM UTC 24 |
Sep 01 11:20:40 PM UTC 24 |
106818503 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3240879082 |
|
|
Sep 01 11:20:37 PM UTC 24 |
Sep 01 11:20:41 PM UTC 24 |
152656430 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2288588981 |
|
|
Sep 01 11:20:39 PM UTC 24 |
Sep 01 11:20:41 PM UTC 24 |
16377529 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2265755223 |
|
|
Sep 01 11:20:39 PM UTC 24 |
Sep 01 11:20:42 PM UTC 24 |
67674443 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3421564110 |
|
|
Sep 01 11:20:40 PM UTC 24 |
Sep 01 11:20:42 PM UTC 24 |
23076005 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3206842739 |
|
|
Sep 01 11:20:39 PM UTC 24 |
Sep 01 11:20:42 PM UTC 24 |
252708023 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2226219955 |
|
|
Sep 01 11:20:40 PM UTC 24 |
Sep 01 11:20:43 PM UTC 24 |
33347729 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3461832276 |
|
|
Sep 01 11:20:48 PM UTC 24 |
Sep 01 11:20:52 PM UTC 24 |
59239745 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1349246584 |
|
|
Sep 01 11:20:36 PM UTC 24 |
Sep 01 11:20:44 PM UTC 24 |
116598388 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3305888801 |
|
|
Sep 01 11:20:42 PM UTC 24 |
Sep 01 11:20:44 PM UTC 24 |
37396764 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2470685205 |
|
|
Sep 01 11:20:40 PM UTC 24 |
Sep 01 11:20:44 PM UTC 24 |
114267558 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.363970500 |
|
|
Sep 01 11:20:42 PM UTC 24 |
Sep 01 11:20:44 PM UTC 24 |
29782056 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3600577226 |
|
|
Sep 01 11:20:40 PM UTC 24 |
Sep 01 11:20:45 PM UTC 24 |
87374789 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2733332729 |
|
|
Sep 01 11:20:42 PM UTC 24 |
Sep 01 11:20:45 PM UTC 24 |
85175282 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1552418956 |
|
|
Sep 01 11:20:42 PM UTC 24 |
Sep 01 11:20:45 PM UTC 24 |
32577499 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4195908771 |
|
|
Sep 01 11:20:42 PM UTC 24 |
Sep 01 11:20:45 PM UTC 24 |
104633440 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2570313491 |
|
|
Sep 01 11:20:39 PM UTC 24 |
Sep 01 11:20:45 PM UTC 24 |
2188211837 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.825980376 |
|
|
Sep 01 11:20:42 PM UTC 24 |
Sep 01 11:20:45 PM UTC 24 |
24388333 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2434097395 |
|
|
Sep 01 11:20:40 PM UTC 24 |
Sep 01 11:20:45 PM UTC 24 |
493909947 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.18563510 |
|
|
Sep 01 11:20:40 PM UTC 24 |
Sep 01 11:20:46 PM UTC 24 |
89661311 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3508804239 |
|
|
Sep 01 11:20:44 PM UTC 24 |
Sep 01 11:20:47 PM UTC 24 |
157392952 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.381373608 |
|
|
Sep 01 11:20:43 PM UTC 24 |
Sep 01 11:20:47 PM UTC 24 |
301202947 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.935710042 |
|
|
Sep 01 11:20:45 PM UTC 24 |
Sep 01 11:20:47 PM UTC 24 |
21261589 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2389542571 |
|
|
Sep 01 11:20:45 PM UTC 24 |
Sep 01 11:20:47 PM UTC 24 |
14539156 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3112835141 |
|
|
Sep 01 11:20:42 PM UTC 24 |
Sep 01 11:20:48 PM UTC 24 |
628046158 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.520358964 |
|
|
Sep 01 11:20:34 PM UTC 24 |
Sep 01 11:20:48 PM UTC 24 |
10025819811 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2369850890 |
|
|
Sep 01 11:20:44 PM UTC 24 |
Sep 01 11:20:49 PM UTC 24 |
43988310 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3421942324 |
|
|
Sep 01 11:20:46 PM UTC 24 |
Sep 01 11:20:49 PM UTC 24 |
71130452 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2558903485 |
|
|
Sep 01 11:20:46 PM UTC 24 |
Sep 01 11:20:49 PM UTC 24 |
54759287 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.710675560 |
|
|
Sep 01 11:20:45 PM UTC 24 |
Sep 01 11:20:49 PM UTC 24 |
463164182 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1676932473 |
|
|
Sep 01 11:20:46 PM UTC 24 |
Sep 01 11:20:50 PM UTC 24 |
729595033 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4068294430 |
|
|
Sep 01 11:20:46 PM UTC 24 |
Sep 01 11:20:50 PM UTC 24 |
52693992 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2817027668 |
|
|
Sep 01 11:20:47 PM UTC 24 |
Sep 01 11:20:50 PM UTC 24 |
250375432 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3083716159 |
|
|
Sep 01 11:20:48 PM UTC 24 |
Sep 01 11:20:50 PM UTC 24 |
28327888 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1935934665 |
|
|
Sep 01 11:20:44 PM UTC 24 |
Sep 01 11:20:51 PM UTC 24 |
1410087925 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.921286110 |
|
|
Sep 01 11:20:48 PM UTC 24 |
Sep 01 11:20:51 PM UTC 24 |
69161214 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3283082373 |
|
|
Sep 01 11:20:45 PM UTC 24 |
Sep 01 11:20:51 PM UTC 24 |
104542517 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1276070289 |
|
|
Sep 01 11:20:52 PM UTC 24 |
Sep 01 11:20:55 PM UTC 24 |
31757059 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.417861897 |
|
|
Sep 01 11:20:48 PM UTC 24 |
Sep 01 11:20:51 PM UTC 24 |
19177704 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1123566303 |
|
|
Sep 01 11:20:42 PM UTC 24 |
Sep 01 11:20:51 PM UTC 24 |
268543916 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3499519270 |
|
|
Sep 01 11:20:49 PM UTC 24 |
Sep 01 11:20:52 PM UTC 24 |
161883084 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2470305818 |
|
|
Sep 01 11:20:48 PM UTC 24 |
Sep 01 11:20:52 PM UTC 24 |
125688356 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.406488851 |
|
|
Sep 01 11:20:49 PM UTC 24 |
Sep 01 11:20:52 PM UTC 24 |
67456085 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.414369119 |
|
|
Sep 01 11:20:50 PM UTC 24 |
Sep 01 11:20:53 PM UTC 24 |
64662881 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1665434715 |
|
|
Sep 01 11:20:49 PM UTC 24 |
Sep 01 11:20:53 PM UTC 24 |
54417217 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1245582887 |
|
|
Sep 01 11:20:51 PM UTC 24 |
Sep 01 11:20:53 PM UTC 24 |
70770271 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1489424463 |
|
|
Sep 01 11:20:51 PM UTC 24 |
Sep 01 11:20:54 PM UTC 24 |
97883946 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4218097373 |
|
|
Sep 01 11:20:42 PM UTC 24 |
Sep 01 11:20:55 PM UTC 24 |
1737836262 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2301776678 |
|
|
Sep 01 11:20:48 PM UTC 24 |
Sep 01 11:20:55 PM UTC 24 |
467051246 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3312489508 |
|
|
Sep 01 11:20:52 PM UTC 24 |
Sep 01 11:20:56 PM UTC 24 |
45437773 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3385731318 |
|
|
Sep 01 11:20:39 PM UTC 24 |
Sep 01 11:20:56 PM UTC 24 |
5107853864 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2096884202 |
|
|
Sep 01 11:20:52 PM UTC 24 |
Sep 01 11:20:56 PM UTC 24 |
32886221 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2669289393 |
|
|
Sep 01 11:20:54 PM UTC 24 |
Sep 01 11:20:56 PM UTC 24 |
652358310 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1143971896 |
|
|
Sep 01 11:20:51 PM UTC 24 |
Sep 01 11:20:56 PM UTC 24 |
388044324 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.799829895 |
|
|
Sep 01 11:20:54 PM UTC 24 |
Sep 01 11:20:57 PM UTC 24 |
30723579 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.852615981 |
|
|
Sep 01 11:20:51 PM UTC 24 |
Sep 01 11:20:57 PM UTC 24 |
449736613 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1722595956 |
|
|
Sep 01 11:20:56 PM UTC 24 |
Sep 01 11:20:58 PM UTC 24 |
15855077 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3934791656 |
|
|
Sep 01 11:20:52 PM UTC 24 |
Sep 01 11:20:58 PM UTC 24 |
103440820 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3339717096 |
|
|
Sep 01 11:20:54 PM UTC 24 |
Sep 01 11:20:58 PM UTC 24 |
52543532 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1531231265 |
|
|
Sep 01 11:20:51 PM UTC 24 |
Sep 01 11:20:58 PM UTC 24 |
585835370 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1145459456 |
|
|
Sep 01 11:20:54 PM UTC 24 |
Sep 01 11:20:58 PM UTC 24 |
342874645 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.4211772120 |
|
|
Sep 01 11:20:53 PM UTC 24 |
Sep 01 11:20:58 PM UTC 24 |
444948322 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2571997152 |
|
|
Sep 01 11:20:56 PM UTC 24 |
Sep 01 11:20:58 PM UTC 24 |
25756857 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.663858946 |
|
|
Sep 01 11:20:56 PM UTC 24 |
Sep 01 11:20:58 PM UTC 24 |
20345363 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3069639338 |
|
|
Sep 01 11:20:34 PM UTC 24 |
Sep 01 11:20:58 PM UTC 24 |
1105969521 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3931264758 |
|
|
Sep 01 11:20:54 PM UTC 24 |
Sep 01 11:20:58 PM UTC 24 |
206129642 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1323539218 |
|
|
Sep 01 11:20:47 PM UTC 24 |
Sep 01 11:20:59 PM UTC 24 |
1950814235 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4092221286 |
|
|
Sep 01 11:20:57 PM UTC 24 |
Sep 01 11:21:00 PM UTC 24 |
272102839 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3650477210 |
|
|
Sep 01 11:20:55 PM UTC 24 |
Sep 01 11:21:00 PM UTC 24 |
48586034 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3265548816 |
|
|
Sep 01 11:20:57 PM UTC 24 |
Sep 01 11:21:00 PM UTC 24 |
64285626 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1598134750 |
|
|
Sep 01 11:21:08 PM UTC 24 |
Sep 01 11:21:10 PM UTC 24 |
32006144 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1324748886 |
|
|
Sep 01 11:21:08 PM UTC 24 |
Sep 01 11:21:10 PM UTC 24 |
108481395 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2508050004 |
|
|
Sep 01 11:20:56 PM UTC 24 |
Sep 01 11:21:00 PM UTC 24 |
191296511 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.818466611 |
|
|
Sep 01 11:20:58 PM UTC 24 |
Sep 01 11:21:01 PM UTC 24 |
15907780 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.276054926 |
|
|
Sep 01 11:20:59 PM UTC 24 |
Sep 01 11:21:01 PM UTC 24 |
105504349 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1773676966 |
|
|
Sep 01 11:20:57 PM UTC 24 |
Sep 01 11:21:01 PM UTC 24 |
200793028 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.849983858 |
|
|
Sep 01 11:20:47 PM UTC 24 |
Sep 01 11:21:01 PM UTC 24 |
697986199 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.871252458 |
|
|
Sep 01 11:20:54 PM UTC 24 |
Sep 01 11:21:02 PM UTC 24 |
1316633718 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3866393992 |
|
|
Sep 01 11:20:59 PM UTC 24 |
Sep 01 11:21:02 PM UTC 24 |
193297797 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1470684917 |
|
|
Sep 01 11:20:59 PM UTC 24 |
Sep 01 11:21:02 PM UTC 24 |
80053574 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4256719128 |
|
|
Sep 01 11:20:59 PM UTC 24 |
Sep 01 11:21:02 PM UTC 24 |
43553651 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3792862941 |
|
|
Sep 01 11:20:59 PM UTC 24 |
Sep 01 11:21:03 PM UTC 24 |
83035443 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3572318502 |
|
|
Sep 01 11:21:01 PM UTC 24 |
Sep 01 11:21:03 PM UTC 24 |
58003615 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3864353054 |
|
|
Sep 01 11:21:01 PM UTC 24 |
Sep 01 11:21:03 PM UTC 24 |
30085730 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3271095153 |
|
|
Sep 01 11:21:01 PM UTC 24 |
Sep 01 11:21:03 PM UTC 24 |
112325380 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2688269476 |
|
|
Sep 01 11:21:01 PM UTC 24 |
Sep 01 11:21:03 PM UTC 24 |
60202130 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2086331637 |
|
|
Sep 01 11:20:54 PM UTC 24 |
Sep 01 11:21:04 PM UTC 24 |
225312935 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1485601322 |
|
|
Sep 01 11:21:01 PM UTC 24 |
Sep 01 11:21:04 PM UTC 24 |
103534819 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1102067918 |
|
|
Sep 01 11:20:51 PM UTC 24 |
Sep 01 11:21:04 PM UTC 24 |
427448169 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3182202725 |
|
|
Sep 01 11:21:01 PM UTC 24 |
Sep 01 11:21:05 PM UTC 24 |
153070928 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.806906531 |
|
|
Sep 01 11:21:03 PM UTC 24 |
Sep 01 11:21:05 PM UTC 24 |
33021840 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1419179071 |
|
|
Sep 01 11:20:57 PM UTC 24 |
Sep 01 11:21:05 PM UTC 24 |
378675198 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2110745028 |
|
|
Sep 01 11:21:01 PM UTC 24 |
Sep 01 11:21:05 PM UTC 24 |
172419269 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2459500681 |
|
|
Sep 01 11:20:58 PM UTC 24 |
Sep 01 11:21:05 PM UTC 24 |
426007167 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.213350635 |
|
|
Sep 01 11:21:03 PM UTC 24 |
Sep 01 11:21:06 PM UTC 24 |
15492169 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1266606132 |
|
|
Sep 01 11:21:03 PM UTC 24 |
Sep 01 11:21:06 PM UTC 24 |
32183663 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.992325969 |
|
|
Sep 01 11:21:03 PM UTC 24 |
Sep 01 11:21:06 PM UTC 24 |
16501254 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2205275596 |
|
|
Sep 01 11:21:03 PM UTC 24 |
Sep 01 11:21:06 PM UTC 24 |
69193893 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2123925813 |
|
|
Sep 01 11:21:03 PM UTC 24 |
Sep 01 11:21:07 PM UTC 24 |
224134996 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.318882915 |
|
|
Sep 01 11:21:03 PM UTC 24 |
Sep 01 11:21:07 PM UTC 24 |
160722002 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2231836876 |
|
|
Sep 01 11:21:05 PM UTC 24 |
Sep 01 11:21:07 PM UTC 24 |
19034584 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1984630542 |
|
|
Sep 01 11:21:05 PM UTC 24 |
Sep 01 11:21:07 PM UTC 24 |
30137371 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1611899059 |
|
|
Sep 01 11:21:03 PM UTC 24 |
Sep 01 11:21:07 PM UTC 24 |
372823777 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1232822372 |
|
|
Sep 01 11:21:05 PM UTC 24 |
Sep 01 11:21:08 PM UTC 24 |
47101968 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3135406632 |
|
|
Sep 01 11:20:58 PM UTC 24 |
Sep 01 11:21:08 PM UTC 24 |
129392623 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1157748438 |
|
|
Sep 01 11:21:05 PM UTC 24 |
Sep 01 11:21:08 PM UTC 24 |
113957930 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3235140211 |
|
|
Sep 01 11:21:05 PM UTC 24 |
Sep 01 11:21:08 PM UTC 24 |
915375968 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.781843252 |
|
|
Sep 01 11:21:03 PM UTC 24 |
Sep 01 11:21:09 PM UTC 24 |
1136827772 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1129878111 |
|
|
Sep 01 11:21:11 PM UTC 24 |
Sep 01 11:21:13 PM UTC 24 |
15323633 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3815518371 |
|
|
Sep 01 11:21:03 PM UTC 24 |
Sep 01 11:21:09 PM UTC 24 |
219562938 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1530891444 |
|
|
Sep 01 11:21:05 PM UTC 24 |
Sep 01 11:21:10 PM UTC 24 |
68699229 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1462461522 |
|
|
Sep 01 11:21:07 PM UTC 24 |
Sep 01 11:21:10 PM UTC 24 |
35290353 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2860549216 |
|
|
Sep 01 11:21:07 PM UTC 24 |
Sep 01 11:21:10 PM UTC 24 |
58209912 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2945564847 |
|
|
Sep 01 11:21:08 PM UTC 24 |
Sep 01 11:21:10 PM UTC 24 |
175863779 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2021067957 |
|
|
Sep 01 11:21:07 PM UTC 24 |
Sep 01 11:21:11 PM UTC 24 |
156927022 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.262862578 |
|
|
Sep 01 11:21:00 PM UTC 24 |
Sep 01 11:21:11 PM UTC 24 |
694151132 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.703677979 |
|
|
Sep 01 11:21:07 PM UTC 24 |
Sep 01 11:21:12 PM UTC 24 |
141646090 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1492560554 |
|
|
Sep 01 11:21:07 PM UTC 24 |
Sep 01 11:21:12 PM UTC 24 |
71465548 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3286276812 |
|
|
Sep 01 11:21:07 PM UTC 24 |
Sep 01 11:21:12 PM UTC 24 |
363303602 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2818038906 |
|
|
Sep 01 11:21:08 PM UTC 24 |
Sep 01 11:21:14 PM UTC 24 |
136300926 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3083200831 |
|
|
Sep 01 11:21:11 PM UTC 24 |
Sep 01 11:21:14 PM UTC 24 |
27256328 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1108438270 |
|
|
Sep 01 11:21:07 PM UTC 24 |
Sep 01 11:21:14 PM UTC 24 |
1198118535 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2900291925 |
|
|
Sep 01 11:21:11 PM UTC 24 |
Sep 01 11:21:14 PM UTC 24 |
208745492 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3051513683 |
|
|
Sep 01 11:21:11 PM UTC 24 |
Sep 01 11:21:14 PM UTC 24 |
23364639 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4122036135 |
|
|
Sep 01 11:21:12 PM UTC 24 |
Sep 01 11:21:14 PM UTC 24 |
48036989 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2976541725 |
|
|
Sep 01 11:21:12 PM UTC 24 |
Sep 01 11:21:14 PM UTC 24 |
105446898 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1592691084 |
|
|
Sep 01 11:20:57 PM UTC 24 |
Sep 01 11:21:14 PM UTC 24 |
13594675237 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2824918407 |
|
|
Sep 01 11:21:11 PM UTC 24 |
Sep 01 11:21:14 PM UTC 24 |
38852090 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1093626318 |
|
|
Sep 01 11:21:12 PM UTC 24 |
Sep 01 11:21:14 PM UTC 24 |
28668406 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3645865021 |
|
|
Sep 01 11:21:12 PM UTC 24 |
Sep 01 11:21:14 PM UTC 24 |
21503052 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2170657835 |
|
|
Sep 01 11:21:11 PM UTC 24 |
Sep 01 11:21:14 PM UTC 24 |
113537842 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1543186793 |
|
|
Sep 01 11:21:12 PM UTC 24 |
Sep 01 11:21:14 PM UTC 24 |
73842162 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1674142839 |
|
|
Sep 01 11:21:12 PM UTC 24 |
Sep 01 11:21:15 PM UTC 24 |
79731409 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4174897716 |
|
|
Sep 01 11:21:12 PM UTC 24 |
Sep 01 11:21:15 PM UTC 24 |
61013678 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2422337518 |
|
|
Sep 01 11:21:11 PM UTC 24 |
Sep 01 11:21:15 PM UTC 24 |
66970951 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.903152974 |
|
|
Sep 01 11:21:11 PM UTC 24 |
Sep 01 11:21:15 PM UTC 24 |
105579582 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3125602638 |
|
|
Sep 01 11:21:14 PM UTC 24 |
Sep 01 11:21:16 PM UTC 24 |
18253344 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3009881738 |
|
|
Sep 01 11:21:12 PM UTC 24 |
Sep 01 11:21:16 PM UTC 24 |
61787875 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1054748004 |
|
|
Sep 01 11:21:14 PM UTC 24 |
Sep 01 11:21:16 PM UTC 24 |
154332151 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2353510584 |
|
|
Sep 01 11:21:12 PM UTC 24 |
Sep 01 11:21:17 PM UTC 24 |
315890931 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.394550083 |
|
|
Sep 01 11:21:14 PM UTC 24 |
Sep 01 11:21:17 PM UTC 24 |
20363967 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3827458147 |
|
|
Sep 01 11:21:12 PM UTC 24 |
Sep 01 11:21:17 PM UTC 24 |
255146719 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2256773561 |
|
|
Sep 01 11:21:01 PM UTC 24 |
Sep 01 11:21:18 PM UTC 24 |
2483842776 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2323541318 |
|
|
Sep 01 11:21:14 PM UTC 24 |
Sep 01 11:21:19 PM UTC 24 |
288014222 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.4143052303 |
|
|
Sep 01 11:21:14 PM UTC 24 |
Sep 01 11:21:19 PM UTC 24 |
194570671 ps |