| T827 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.1765958803 |
|
|
Sep 18 09:26:10 PM UTC 24 |
Sep 18 09:26:47 PM UTC 24 |
2069163506 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.2218533649 |
|
|
Sep 18 09:26:37 PM UTC 24 |
Sep 18 09:26:48 PM UTC 24 |
730683373 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.4192642370 |
|
|
Sep 18 09:26:44 PM UTC 24 |
Sep 18 09:26:48 PM UTC 24 |
40731596 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.4102247278 |
|
|
Sep 18 09:26:37 PM UTC 24 |
Sep 18 09:26:48 PM UTC 24 |
287642322 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.1890594855 |
|
|
Sep 18 09:26:25 PM UTC 24 |
Sep 18 09:26:49 PM UTC 24 |
1020026278 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.4278206216 |
|
|
Sep 18 09:26:22 PM UTC 24 |
Sep 18 09:26:49 PM UTC 24 |
1619679933 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.3161261609 |
|
|
Sep 18 09:26:48 PM UTC 24 |
Sep 18 09:26:50 PM UTC 24 |
58601080 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.3088326724 |
|
|
Sep 18 09:26:38 PM UTC 24 |
Sep 18 09:26:50 PM UTC 24 |
323519766 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1141384470 |
|
|
Sep 18 09:26:48 PM UTC 24 |
Sep 18 09:26:50 PM UTC 24 |
12538696 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.4136698769 |
|
|
Sep 18 09:24:49 PM UTC 24 |
Sep 18 09:26:51 PM UTC 24 |
4887850212 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.1031284040 |
|
|
Sep 18 09:26:56 PM UTC 24 |
Sep 18 09:27:04 PM UTC 24 |
215866947 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.4040033635 |
|
|
Sep 18 09:26:48 PM UTC 24 |
Sep 18 09:26:52 PM UTC 24 |
149744445 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.3383632669 |
|
|
Sep 18 09:26:38 PM UTC 24 |
Sep 18 09:26:52 PM UTC 24 |
524700333 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.2843633315 |
|
|
Sep 18 09:26:48 PM UTC 24 |
Sep 18 09:27:10 PM UTC 24 |
1451027103 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.130382323 |
|
|
Sep 18 09:26:49 PM UTC 24 |
Sep 18 09:26:53 PM UTC 24 |
39276176 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.3129279778 |
|
|
Sep 18 09:26:43 PM UTC 24 |
Sep 18 09:26:53 PM UTC 24 |
113561830 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.1426592355 |
|
|
Sep 18 09:23:27 PM UTC 24 |
Sep 18 09:26:54 PM UTC 24 |
6995377574 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.3584684590 |
|
|
Sep 18 09:26:52 PM UTC 24 |
Sep 18 09:26:55 PM UTC 24 |
21331386 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2542970422 |
|
|
Sep 18 09:26:52 PM UTC 24 |
Sep 18 09:26:55 PM UTC 24 |
36480741 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.1276866672 |
|
|
Sep 18 09:26:46 PM UTC 24 |
Sep 18 09:26:55 PM UTC 24 |
4343728461 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.3465133902 |
|
|
Sep 18 09:26:51 PM UTC 24 |
Sep 18 09:27:04 PM UTC 24 |
491999508 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.997239086 |
|
|
Sep 18 09:26:52 PM UTC 24 |
Sep 18 09:26:55 PM UTC 24 |
18989483 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.1687844503 |
|
|
Sep 18 09:26:46 PM UTC 24 |
Sep 18 09:26:55 PM UTC 24 |
179869204 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.2949338559 |
|
|
Sep 18 09:26:44 PM UTC 24 |
Sep 18 09:26:56 PM UTC 24 |
502798127 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.3636317885 |
|
|
Sep 18 09:24:31 PM UTC 24 |
Sep 18 09:26:56 PM UTC 24 |
6635088955 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.1257953700 |
|
|
Sep 18 09:26:38 PM UTC 24 |
Sep 18 09:26:57 PM UTC 24 |
775514536 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.1091617842 |
|
|
Sep 18 09:26:49 PM UTC 24 |
Sep 18 09:26:57 PM UTC 24 |
5344086704 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.1012404300 |
|
|
Sep 18 09:26:37 PM UTC 24 |
Sep 18 09:26:57 PM UTC 24 |
686995138 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.490188269 |
|
|
Sep 18 09:26:49 PM UTC 24 |
Sep 18 09:26:57 PM UTC 24 |
921922216 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.3387069370 |
|
|
Sep 18 09:26:45 PM UTC 24 |
Sep 18 09:26:58 PM UTC 24 |
690368686 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.3667323998 |
|
|
Sep 18 09:25:57 PM UTC 24 |
Sep 18 09:26:58 PM UTC 24 |
7758928151 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.4004970538 |
|
|
Sep 18 09:26:33 PM UTC 24 |
Sep 18 09:26:58 PM UTC 24 |
965351269 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.2667719225 |
|
|
Sep 18 09:26:54 PM UTC 24 |
Sep 18 09:26:59 PM UTC 24 |
75525702 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.2103162965 |
|
|
Sep 18 09:26:49 PM UTC 24 |
Sep 18 09:26:59 PM UTC 24 |
836282463 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.1563603369 |
|
|
Sep 18 09:26:56 PM UTC 24 |
Sep 18 09:26:59 PM UTC 24 |
259243197 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.2198438370 |
|
|
Sep 18 09:26:35 PM UTC 24 |
Sep 18 09:26:59 PM UTC 24 |
545550243 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.134306487 |
|
|
Sep 18 09:26:57 PM UTC 24 |
Sep 18 09:27:00 PM UTC 24 |
40929970 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.1624896498 |
|
|
Sep 18 09:26:49 PM UTC 24 |
Sep 18 09:27:00 PM UTC 24 |
829611125 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.3260904787 |
|
|
Sep 18 09:26:46 PM UTC 24 |
Sep 18 09:27:00 PM UTC 24 |
368871592 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.727042477 |
|
|
Sep 18 09:26:51 PM UTC 24 |
Sep 18 09:27:01 PM UTC 24 |
895649759 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.4163508239 |
|
|
Sep 18 09:26:51 PM UTC 24 |
Sep 18 09:27:02 PM UTC 24 |
254084521 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.744745924 |
|
|
Sep 18 09:26:54 PM UTC 24 |
Sep 18 09:27:03 PM UTC 24 |
71260739 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.2603887810 |
|
|
Sep 18 09:26:42 PM UTC 24 |
Sep 18 09:27:03 PM UTC 24 |
403619904 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.3038423502 |
|
|
Sep 18 09:26:56 PM UTC 24 |
Sep 18 09:27:03 PM UTC 24 |
225583188 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.191817737 |
|
|
Sep 18 09:26:46 PM UTC 24 |
Sep 18 09:27:04 PM UTC 24 |
2972854773 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.2451539015 |
|
|
Sep 18 09:26:56 PM UTC 24 |
Sep 18 09:27:12 PM UTC 24 |
3620949248 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.1238520150 |
|
|
Sep 18 09:26:35 PM UTC 24 |
Sep 18 09:27:16 PM UTC 24 |
5232304693 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.189460447 |
|
|
Sep 18 09:25:07 PM UTC 24 |
Sep 18 09:27:16 PM UTC 24 |
8872854302 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2519082119 |
|
|
Sep 18 09:26:35 PM UTC 24 |
Sep 18 09:27:17 PM UTC 24 |
5970955128 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.810372485 |
|
|
Sep 18 09:26:54 PM UTC 24 |
Sep 18 09:27:19 PM UTC 24 |
321339212 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.3490366723 |
|
|
Sep 18 09:25:14 PM UTC 24 |
Sep 18 09:27:30 PM UTC 24 |
7296767850 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.829564194 |
|
|
Sep 18 09:26:23 PM UTC 24 |
Sep 18 09:27:41 PM UTC 24 |
3202069216 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.3233141385 |
|
|
Sep 18 09:25:18 PM UTC 24 |
Sep 18 09:27:42 PM UTC 24 |
3615945664 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.293700712 |
|
|
Sep 18 09:26:17 PM UTC 24 |
Sep 18 09:27:43 PM UTC 24 |
5357992765 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.3275893139 |
|
|
Sep 18 09:20:34 PM UTC 24 |
Sep 18 09:27:54 PM UTC 24 |
12817946697 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1820022021 |
|
|
Sep 18 09:24:39 PM UTC 24 |
Sep 18 09:28:03 PM UTC 24 |
7061905912 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.1282018651 |
|
|
Sep 18 09:26:29 PM UTC 24 |
Sep 18 09:28:19 PM UTC 24 |
14144299835 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.1321926862 |
|
|
Sep 18 09:26:02 PM UTC 24 |
Sep 18 09:28:23 PM UTC 24 |
17294144759 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2975465621 |
|
|
Sep 18 09:26:52 PM UTC 24 |
Sep 18 09:28:31 PM UTC 24 |
9694298666 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.670247823 |
|
|
Sep 18 09:25:50 PM UTC 24 |
Sep 18 09:28:41 PM UTC 24 |
31864535597 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.2531879827 |
|
|
Sep 18 09:26:51 PM UTC 24 |
Sep 18 09:28:44 PM UTC 24 |
22127944346 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.609916076 |
|
|
Sep 18 09:26:56 PM UTC 24 |
Sep 18 09:28:56 PM UTC 24 |
22964895909 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.367657383 |
|
|
Sep 18 09:24:23 PM UTC 24 |
Sep 18 09:28:59 PM UTC 24 |
22140190483 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.1165769040 |
|
|
Sep 18 09:25:39 PM UTC 24 |
Sep 18 09:29:08 PM UTC 24 |
19684134820 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.66687393 |
|
|
Sep 18 09:26:40 PM UTC 24 |
Sep 18 09:29:48 PM UTC 24 |
71191583057 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.2837692802 |
|
|
Sep 18 09:26:16 PM UTC 24 |
Sep 18 09:30:18 PM UTC 24 |
6876826385 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.3624371357 |
|
|
Sep 18 09:25:32 PM UTC 24 |
Sep 18 09:30:32 PM UTC 24 |
34696428411 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.2898003595 |
|
|
Sep 18 09:21:07 PM UTC 24 |
Sep 18 09:30:53 PM UTC 24 |
239296595496 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.1217581904 |
|
|
Sep 18 09:25:25 PM UTC 24 |
Sep 18 09:31:00 PM UTC 24 |
42640368014 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.3579068475 |
|
|
Sep 18 09:26:48 PM UTC 24 |
Sep 18 09:35:47 PM UTC 24 |
26621254869 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.3657768827 |
|
|
Sep 18 09:26:23 PM UTC 24 |
Sep 18 09:36:35 PM UTC 24 |
194895572371 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4033595176 |
|
|
Sep 18 09:26:57 PM UTC 24 |
Sep 18 09:27:00 PM UTC 24 |
130985337 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4130201355 |
|
|
Sep 18 09:26:57 PM UTC 24 |
Sep 18 09:27:01 PM UTC 24 |
278022730 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2726212825 |
|
|
Sep 18 09:26:59 PM UTC 24 |
Sep 18 09:27:02 PM UTC 24 |
178418355 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.68842702 |
|
|
Sep 18 09:27:01 PM UTC 24 |
Sep 18 09:27:03 PM UTC 24 |
14547082 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.802841656 |
|
|
Sep 18 09:27:01 PM UTC 24 |
Sep 18 09:27:03 PM UTC 24 |
73447154 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2221801067 |
|
|
Sep 18 09:27:01 PM UTC 24 |
Sep 18 09:27:03 PM UTC 24 |
64922816 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3209792025 |
|
|
Sep 18 09:27:01 PM UTC 24 |
Sep 18 09:27:04 PM UTC 24 |
72787651 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1649770131 |
|
|
Sep 18 09:27:01 PM UTC 24 |
Sep 18 09:27:04 PM UTC 24 |
23598263 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1149368022 |
|
|
Sep 18 09:27:13 PM UTC 24 |
Sep 18 09:27:17 PM UTC 24 |
36572882 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1828826664 |
|
|
Sep 18 09:27:01 PM UTC 24 |
Sep 18 09:27:04 PM UTC 24 |
22799398 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.22153424 |
|
|
Sep 18 09:27:01 PM UTC 24 |
Sep 18 09:27:04 PM UTC 24 |
209835205 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3901553276 |
|
|
Sep 18 09:27:02 PM UTC 24 |
Sep 18 09:27:05 PM UTC 24 |
69774059 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3245071491 |
|
|
Sep 18 09:27:02 PM UTC 24 |
Sep 18 09:27:05 PM UTC 24 |
91471633 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4276465575 |
|
|
Sep 18 09:27:01 PM UTC 24 |
Sep 18 09:27:06 PM UTC 24 |
645187688 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.4001267789 |
|
|
Sep 18 09:27:01 PM UTC 24 |
Sep 18 09:27:06 PM UTC 24 |
541318573 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2975048376 |
|
|
Sep 18 09:27:02 PM UTC 24 |
Sep 18 09:27:07 PM UTC 24 |
261906387 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1939792411 |
|
|
Sep 18 09:27:04 PM UTC 24 |
Sep 18 09:27:07 PM UTC 24 |
45994266 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1145642514 |
|
|
Sep 18 09:27:04 PM UTC 24 |
Sep 18 09:27:07 PM UTC 24 |
66314746 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2106935050 |
|
|
Sep 18 09:27:04 PM UTC 24 |
Sep 18 09:27:07 PM UTC 24 |
39635931 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.938962974 |
|
|
Sep 18 09:27:02 PM UTC 24 |
Sep 18 09:27:07 PM UTC 24 |
187614027 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2713553216 |
|
|
Sep 18 09:26:59 PM UTC 24 |
Sep 18 09:27:07 PM UTC 24 |
1241319021 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3584163969 |
|
|
Sep 18 09:27:04 PM UTC 24 |
Sep 18 09:27:07 PM UTC 24 |
28648856 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3891593040 |
|
|
Sep 18 09:27:04 PM UTC 24 |
Sep 18 09:27:08 PM UTC 24 |
362417085 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.940307491 |
|
|
Sep 18 09:26:59 PM UTC 24 |
Sep 18 09:27:08 PM UTC 24 |
586591706 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3417370470 |
|
|
Sep 18 09:27:05 PM UTC 24 |
Sep 18 09:27:08 PM UTC 24 |
105752029 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1067675216 |
|
|
Sep 18 09:27:04 PM UTC 24 |
Sep 18 09:27:08 PM UTC 24 |
91726661 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3727201681 |
|
|
Sep 18 09:27:05 PM UTC 24 |
Sep 18 09:27:08 PM UTC 24 |
29777009 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1274740128 |
|
|
Sep 18 09:27:04 PM UTC 24 |
Sep 18 09:27:08 PM UTC 24 |
111170078 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4233264516 |
|
|
Sep 18 09:27:06 PM UTC 24 |
Sep 18 09:27:08 PM UTC 24 |
403951661 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2240265190 |
|
|
Sep 18 09:27:04 PM UTC 24 |
Sep 18 09:27:09 PM UTC 24 |
121895810 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3829048516 |
|
|
Sep 18 09:27:06 PM UTC 24 |
Sep 18 09:27:09 PM UTC 24 |
171805977 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1430378623 |
|
|
Sep 18 09:27:06 PM UTC 24 |
Sep 18 09:27:09 PM UTC 24 |
280615496 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.338956128 |
|
|
Sep 18 09:27:07 PM UTC 24 |
Sep 18 09:27:10 PM UTC 24 |
278409676 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2643611154 |
|
|
Sep 18 09:27:07 PM UTC 24 |
Sep 18 09:27:10 PM UTC 24 |
55330193 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1576028120 |
|
|
Sep 18 09:27:06 PM UTC 24 |
Sep 18 09:27:10 PM UTC 24 |
648130228 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2190442899 |
|
|
Sep 18 09:27:08 PM UTC 24 |
Sep 18 09:27:11 PM UTC 24 |
93048505 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.153164119 |
|
|
Sep 18 09:27:08 PM UTC 24 |
Sep 18 09:27:11 PM UTC 24 |
48030246 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3981882385 |
|
|
Sep 18 09:27:08 PM UTC 24 |
Sep 18 09:27:11 PM UTC 24 |
184307332 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1508256943 |
|
|
Sep 18 09:26:59 PM UTC 24 |
Sep 18 09:27:11 PM UTC 24 |
974297938 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.837735484 |
|
|
Sep 18 09:27:08 PM UTC 24 |
Sep 18 09:27:12 PM UTC 24 |
171423765 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1898297007 |
|
|
Sep 18 09:27:07 PM UTC 24 |
Sep 18 09:27:12 PM UTC 24 |
457285171 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.706968495 |
|
|
Sep 18 09:27:08 PM UTC 24 |
Sep 18 09:27:12 PM UTC 24 |
390657763 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3232735988 |
|
|
Sep 18 09:27:08 PM UTC 24 |
Sep 18 09:27:12 PM UTC 24 |
63795525 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2491629377 |
|
|
Sep 18 09:27:07 PM UTC 24 |
Sep 18 09:27:13 PM UTC 24 |
127003059 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1052685291 |
|
|
Sep 18 09:27:10 PM UTC 24 |
Sep 18 09:27:13 PM UTC 24 |
31295457 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.776745533 |
|
|
Sep 18 09:27:09 PM UTC 24 |
Sep 18 09:27:13 PM UTC 24 |
151652986 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2564887197 |
|
|
Sep 18 09:27:10 PM UTC 24 |
Sep 18 09:27:13 PM UTC 24 |
30580477 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3996432151 |
|
|
Sep 18 09:27:10 PM UTC 24 |
Sep 18 09:27:13 PM UTC 24 |
232358716 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3066936309 |
|
|
Sep 18 09:27:10 PM UTC 24 |
Sep 18 09:27:13 PM UTC 24 |
21014106 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3523945079 |
|
|
Sep 18 09:27:10 PM UTC 24 |
Sep 18 09:27:14 PM UTC 24 |
85983295 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1990704279 |
|
|
Sep 18 09:27:10 PM UTC 24 |
Sep 18 09:27:14 PM UTC 24 |
130091076 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4093681121 |
|
|
Sep 18 09:27:10 PM UTC 24 |
Sep 18 09:27:14 PM UTC 24 |
179343806 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.919996888 |
|
|
Sep 18 09:27:11 PM UTC 24 |
Sep 18 09:27:14 PM UTC 24 |
51947250 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2143005670 |
|
|
Sep 18 09:27:12 PM UTC 24 |
Sep 18 09:27:14 PM UTC 24 |
368266547 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2558114717 |
|
|
Sep 18 09:27:11 PM UTC 24 |
Sep 18 09:27:15 PM UTC 24 |
46487765 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2752901779 |
|
|
Sep 18 09:27:13 PM UTC 24 |
Sep 18 09:27:16 PM UTC 24 |
21003379 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.193146613 |
|
|
Sep 18 09:27:13 PM UTC 24 |
Sep 18 09:27:16 PM UTC 24 |
148099707 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1020868783 |
|
|
Sep 18 09:27:14 PM UTC 24 |
Sep 18 09:27:17 PM UTC 24 |
75603364 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3177454490 |
|
|
Sep 18 09:27:14 PM UTC 24 |
Sep 18 09:27:17 PM UTC 24 |
66765951 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.108949063 |
|
|
Sep 18 09:27:11 PM UTC 24 |
Sep 18 09:27:15 PM UTC 24 |
170901819 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3212972570 |
|
|
Sep 18 09:27:11 PM UTC 24 |
Sep 18 09:27:15 PM UTC 24 |
147005136 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.223636013 |
|
|
Sep 18 09:27:10 PM UTC 24 |
Sep 18 09:27:16 PM UTC 24 |
319254820 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3066386178 |
|
|
Sep 18 09:27:13 PM UTC 24 |
Sep 18 09:27:16 PM UTC 24 |
52867989 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1100773579 |
|
|
Sep 18 09:27:13 PM UTC 24 |
Sep 18 09:27:16 PM UTC 24 |
392697198 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1259480719 |
|
|
Sep 18 09:27:13 PM UTC 24 |
Sep 18 09:27:17 PM UTC 24 |
123962442 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1021863610 |
|
|
Sep 18 09:27:14 PM UTC 24 |
Sep 18 09:27:17 PM UTC 24 |
370930899 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2302572878 |
|
|
Sep 18 09:27:14 PM UTC 24 |
Sep 18 09:27:17 PM UTC 24 |
59836565 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1017818568 |
|
|
Sep 18 09:27:14 PM UTC 24 |
Sep 18 09:27:18 PM UTC 24 |
68331737 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.405961868 |
|
|
Sep 18 09:27:16 PM UTC 24 |
Sep 18 09:27:18 PM UTC 24 |
13583599 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1976320304 |
|
|
Sep 18 09:27:14 PM UTC 24 |
Sep 18 09:27:18 PM UTC 24 |
246661175 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.892347892 |
|
|
Sep 18 09:27:13 PM UTC 24 |
Sep 18 09:27:18 PM UTC 24 |
109909743 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2391429374 |
|
|
Sep 18 09:27:16 PM UTC 24 |
Sep 18 09:27:18 PM UTC 24 |
17253385 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1723703398 |
|
|
Sep 18 09:27:16 PM UTC 24 |
Sep 18 09:27:18 PM UTC 24 |
59617553 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.499197095 |
|
|
Sep 18 09:27:16 PM UTC 24 |
Sep 18 09:27:19 PM UTC 24 |
171975519 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3343536278 |
|
|
Sep 18 09:27:16 PM UTC 24 |
Sep 18 09:27:19 PM UTC 24 |
51638052 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2460181806 |
|
|
Sep 18 09:27:18 PM UTC 24 |
Sep 18 09:27:20 PM UTC 24 |
21281561 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1478259770 |
|
|
Sep 18 09:27:16 PM UTC 24 |
Sep 18 09:27:19 PM UTC 24 |
46090046 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1521865290 |
|
|
Sep 18 09:27:17 PM UTC 24 |
Sep 18 09:27:20 PM UTC 24 |
62810622 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4071523548 |
|
|
Sep 18 09:27:17 PM UTC 24 |
Sep 18 09:27:20 PM UTC 24 |
591351267 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3358767075 |
|
|
Sep 18 09:27:18 PM UTC 24 |
Sep 18 09:27:20 PM UTC 24 |
14696416 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4218629390 |
|
|
Sep 18 09:27:18 PM UTC 24 |
Sep 18 09:27:20 PM UTC 24 |
64637652 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.291257697 |
|
|
Sep 18 09:27:17 PM UTC 24 |
Sep 18 09:27:20 PM UTC 24 |
152739783 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3645987626 |
|
|
Sep 18 09:27:31 PM UTC 24 |
Sep 18 09:27:33 PM UTC 24 |
27658761 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3720896048 |
|
|
Sep 18 09:27:09 PM UTC 24 |
Sep 18 09:27:21 PM UTC 24 |
1405345451 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.91392933 |
|
|
Sep 18 09:27:18 PM UTC 24 |
Sep 18 09:27:21 PM UTC 24 |
1399790800 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.394983919 |
|
|
Sep 18 09:27:18 PM UTC 24 |
Sep 18 09:27:21 PM UTC 24 |
849685707 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2134279195 |
|
|
Sep 18 09:27:19 PM UTC 24 |
Sep 18 09:27:21 PM UTC 24 |
214097840 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1547576021 |
|
|
Sep 18 09:27:02 PM UTC 24 |
Sep 18 09:27:22 PM UTC 24 |
2071763994 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1472575277 |
|
|
Sep 18 09:27:19 PM UTC 24 |
Sep 18 09:27:22 PM UTC 24 |
43773123 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.954789579 |
|
|
Sep 18 09:27:17 PM UTC 24 |
Sep 18 09:27:22 PM UTC 24 |
213531538 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1792861850 |
|
|
Sep 18 09:27:06 PM UTC 24 |
Sep 18 09:27:22 PM UTC 24 |
730126257 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3948470582 |
|
|
Sep 18 09:27:27 PM UTC 24 |
Sep 18 09:27:33 PM UTC 24 |
114790972 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.562302893 |
|
|
Sep 18 09:27:31 PM UTC 24 |
Sep 18 09:27:34 PM UTC 24 |
17316901 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.799805866 |
|
|
Sep 18 09:27:19 PM UTC 24 |
Sep 18 09:27:22 PM UTC 24 |
123717618 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3197200286 |
|
|
Sep 18 09:27:18 PM UTC 24 |
Sep 18 09:27:22 PM UTC 24 |
126502176 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4108906848 |
|
|
Sep 18 09:27:16 PM UTC 24 |
Sep 18 09:27:23 PM UTC 24 |
1469689968 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.244672964 |
|
|
Sep 18 09:27:19 PM UTC 24 |
Sep 18 09:27:23 PM UTC 24 |
890435911 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2390276601 |
|
|
Sep 18 09:27:21 PM UTC 24 |
Sep 18 09:27:23 PM UTC 24 |
14011210 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1374928509 |
|
|
Sep 18 09:27:19 PM UTC 24 |
Sep 18 09:27:23 PM UTC 24 |
76541255 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2225648804 |
|
|
Sep 18 09:27:21 PM UTC 24 |
Sep 18 09:27:23 PM UTC 24 |
47737161 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3947892555 |
|
|
Sep 18 09:27:21 PM UTC 24 |
Sep 18 09:27:23 PM UTC 24 |
174998256 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2004013255 |
|
|
Sep 18 09:27:21 PM UTC 24 |
Sep 18 09:27:23 PM UTC 24 |
47422383 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3400861292 |
|
|
Sep 18 09:27:21 PM UTC 24 |
Sep 18 09:27:23 PM UTC 24 |
305543836 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.260800449 |
|
|
Sep 18 09:27:21 PM UTC 24 |
Sep 18 09:27:24 PM UTC 24 |
21967535 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.248944905 |
|
|
Sep 18 09:27:19 PM UTC 24 |
Sep 18 09:27:24 PM UTC 24 |
393676358 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3110491282 |
|
|
Sep 18 09:27:09 PM UTC 24 |
Sep 18 09:27:24 PM UTC 24 |
4405256742 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4286844817 |
|
|
Sep 18 09:27:21 PM UTC 24 |
Sep 18 09:27:24 PM UTC 24 |
28163109 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3078771349 |
|
|
Sep 18 09:27:22 PM UTC 24 |
Sep 18 09:27:25 PM UTC 24 |
106833679 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3767449632 |
|
|
Sep 18 09:27:23 PM UTC 24 |
Sep 18 09:27:25 PM UTC 24 |
84024327 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2081819313 |
|
|
Sep 18 09:27:22 PM UTC 24 |
Sep 18 09:27:25 PM UTC 24 |
44924166 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3770200991 |
|
|
Sep 18 09:27:19 PM UTC 24 |
Sep 18 09:27:25 PM UTC 24 |
356587460 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.425015505 |
|
|
Sep 18 09:27:21 PM UTC 24 |
Sep 18 09:27:26 PM UTC 24 |
198916003 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3519861509 |
|
|
Sep 18 09:27:23 PM UTC 24 |
Sep 18 09:27:26 PM UTC 24 |
163148406 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2245281711 |
|
|
Sep 18 09:27:24 PM UTC 24 |
Sep 18 09:27:26 PM UTC 24 |
72428795 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1727507125 |
|
|
Sep 18 09:27:22 PM UTC 24 |
Sep 18 09:27:27 PM UTC 24 |
102529728 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.865218338 |
|
|
Sep 18 09:27:13 PM UTC 24 |
Sep 18 09:27:27 PM UTC 24 |
1042572397 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1411034439 |
|
|
Sep 18 09:27:25 PM UTC 24 |
Sep 18 09:27:27 PM UTC 24 |
14376140 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3974355485 |
|
|
Sep 18 09:27:22 PM UTC 24 |
Sep 18 09:27:27 PM UTC 24 |
743635913 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.715682194 |
|
|
Sep 18 09:27:24 PM UTC 24 |
Sep 18 09:27:27 PM UTC 24 |
187661917 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.192634837 |
|
|
Sep 18 09:27:25 PM UTC 24 |
Sep 18 09:27:27 PM UTC 24 |
61045447 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2893315404 |
|
|
Sep 18 09:27:13 PM UTC 24 |
Sep 18 09:27:27 PM UTC 24 |
5205680783 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1049208584 |
|
|
Sep 18 09:27:24 PM UTC 24 |
Sep 18 09:27:27 PM UTC 24 |
532067917 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2076235145 |
|
|
Sep 18 09:27:24 PM UTC 24 |
Sep 18 09:27:27 PM UTC 24 |
202401125 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.245341812 |
|
|
Sep 18 09:27:24 PM UTC 24 |
Sep 18 09:27:27 PM UTC 24 |
179777644 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2456881234 |
|
|
Sep 18 09:27:24 PM UTC 24 |
Sep 18 09:27:28 PM UTC 24 |
73175439 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1151845379 |
|
|
Sep 18 09:27:24 PM UTC 24 |
Sep 18 09:27:28 PM UTC 24 |
253327148 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1363498576 |
|
|
Sep 18 09:27:26 PM UTC 24 |
Sep 18 09:27:28 PM UTC 24 |
44984274 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3622147219 |
|
|
Sep 18 09:27:26 PM UTC 24 |
Sep 18 09:27:29 PM UTC 24 |
114178697 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1580461291 |
|
|
Sep 18 09:27:26 PM UTC 24 |
Sep 18 09:27:29 PM UTC 24 |
43892883 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2688525485 |
|
|
Sep 18 09:27:24 PM UTC 24 |
Sep 18 09:27:29 PM UTC 24 |
44140305 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2649581542 |
|
|
Sep 18 09:27:27 PM UTC 24 |
Sep 18 09:27:30 PM UTC 24 |
35732137 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2509499449 |
|
|
Sep 18 09:27:26 PM UTC 24 |
Sep 18 09:27:30 PM UTC 24 |
159114100 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.82607889 |
|
|
Sep 18 09:27:26 PM UTC 24 |
Sep 18 09:27:30 PM UTC 24 |
30727691 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3908415507 |
|
|
Sep 18 09:27:26 PM UTC 24 |
Sep 18 09:27:30 PM UTC 24 |
81243520 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2133834983 |
|
|
Sep 18 09:27:25 PM UTC 24 |
Sep 18 09:27:30 PM UTC 24 |
415912601 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1451581474 |
|
|
Sep 18 09:27:27 PM UTC 24 |
Sep 18 09:27:30 PM UTC 24 |
41792534 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3803650880 |
|
|
Sep 18 09:27:06 PM UTC 24 |
Sep 18 09:27:30 PM UTC 24 |
3991418399 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2312770733 |
|
|
Sep 18 09:27:26 PM UTC 24 |
Sep 18 09:27:30 PM UTC 24 |
414234004 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2093756541 |
|
|
Sep 18 09:27:28 PM UTC 24 |
Sep 18 09:27:30 PM UTC 24 |
17318941 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1123051272 |
|
|
Sep 18 09:27:27 PM UTC 24 |
Sep 18 09:27:30 PM UTC 24 |
25993782 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3098881076 |
|
|
Sep 18 09:27:28 PM UTC 24 |
Sep 18 09:27:31 PM UTC 24 |
22561161 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3037627574 |
|
|
Sep 18 09:27:19 PM UTC 24 |
Sep 18 09:27:31 PM UTC 24 |
1819903941 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4285844763 |
|
|
Sep 18 09:27:28 PM UTC 24 |
Sep 18 09:27:31 PM UTC 24 |
60278388 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.16643105 |
|
|
Sep 18 09:27:29 PM UTC 24 |
Sep 18 09:27:31 PM UTC 24 |
49102257 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2856951710 |
|
|
Sep 18 09:27:28 PM UTC 24 |
Sep 18 09:27:32 PM UTC 24 |
331538552 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.881754834 |
|
|
Sep 18 09:27:29 PM UTC 24 |
Sep 18 09:27:32 PM UTC 24 |
48211627 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3942232502 |
|
|
Sep 18 09:27:29 PM UTC 24 |
Sep 18 09:27:32 PM UTC 24 |
63524066 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3594574244 |
|
|
Sep 18 09:27:29 PM UTC 24 |
Sep 18 09:27:32 PM UTC 24 |
100110982 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3367156299 |
|
|
Sep 18 09:27:21 PM UTC 24 |
Sep 18 09:27:32 PM UTC 24 |
838029921 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2706287707 |
|
|
Sep 18 09:27:29 PM UTC 24 |
Sep 18 09:27:33 PM UTC 24 |
252368654 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.29153460 |
|
|
Sep 18 09:27:31 PM UTC 24 |
Sep 18 09:27:33 PM UTC 24 |
48195690 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.70006946 |
|
|
Sep 18 09:27:29 PM UTC 24 |
Sep 18 09:27:34 PM UTC 24 |
45667585 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4008664519 |
|
|
Sep 18 09:27:31 PM UTC 24 |
Sep 18 09:27:34 PM UTC 24 |
51563785 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2159929171 |
|
|
Sep 18 09:27:31 PM UTC 24 |
Sep 18 09:27:34 PM UTC 24 |
34837233 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2532050855 |
|
|
Sep 18 09:27:31 PM UTC 24 |
Sep 18 09:27:34 PM UTC 24 |
21988606 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2419795455 |
|
|
Sep 18 09:27:31 PM UTC 24 |
Sep 18 09:27:34 PM UTC 24 |
45727495 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2628208469 |
|
|
Sep 18 09:27:29 PM UTC 24 |
Sep 18 09:27:34 PM UTC 24 |
956009828 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.35991144 |
|
|
Sep 18 09:27:31 PM UTC 24 |
Sep 18 09:27:34 PM UTC 24 |
66631388 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.512130835 |
|
|
Sep 18 09:27:31 PM UTC 24 |
Sep 18 09:27:34 PM UTC 24 |
121251693 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3483680673 |
|
|
Sep 18 09:27:29 PM UTC 24 |
Sep 18 09:27:34 PM UTC 24 |
599636928 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4274785219 |
|
|
Sep 18 09:27:31 PM UTC 24 |
Sep 18 09:27:35 PM UTC 24 |
24801995 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.606570904 |
|
|
Sep 18 09:27:31 PM UTC 24 |
Sep 18 09:27:35 PM UTC 24 |
126301553 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.517155672 |
|
|
Sep 18 09:27:33 PM UTC 24 |
Sep 18 09:27:35 PM UTC 24 |
14508893 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2280898503 |
|
|
Sep 18 09:27:31 PM UTC 24 |
Sep 18 09:27:35 PM UTC 24 |
374843503 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.465867973 |
|
|
Sep 18 09:27:33 PM UTC 24 |
Sep 18 09:27:36 PM UTC 24 |
42663827 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.717215289 |
|
|
Sep 18 09:27:18 PM UTC 24 |
Sep 18 09:27:36 PM UTC 24 |
694544760 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2584782888 |
|
|
Sep 18 09:27:33 PM UTC 24 |
Sep 18 09:27:36 PM UTC 24 |
23358833 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4215168813 |
|
|
Sep 18 09:27:33 PM UTC 24 |
Sep 18 09:27:36 PM UTC 24 |
31858053 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3122245941 |
|
|
Sep 18 09:27:31 PM UTC 24 |
Sep 18 09:27:36 PM UTC 24 |
645549503 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.958623075 |
|
|
Sep 18 09:27:33 PM UTC 24 |
Sep 18 09:27:36 PM UTC 24 |
43613105 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1439723070 |
|
|
Sep 18 09:27:33 PM UTC 24 |
Sep 18 09:27:36 PM UTC 24 |
36684419 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2199220121 |
|
|
Sep 18 09:27:33 PM UTC 24 |
Sep 18 09:27:36 PM UTC 24 |
82640441 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.258241747 |
|
|
Sep 18 09:27:34 PM UTC 24 |
Sep 18 09:27:37 PM UTC 24 |
18587782 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1322987258 |
|
|
Sep 18 09:27:34 PM UTC 24 |
Sep 18 09:27:37 PM UTC 24 |
122928900 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3245688608 |
|
|
Sep 18 09:27:35 PM UTC 24 |
Sep 18 09:27:37 PM UTC 24 |
43724445 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2897747235 |
|
|
Sep 18 09:27:35 PM UTC 24 |
Sep 18 09:27:37 PM UTC 24 |
20325630 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1662437689 |
|
|
Sep 18 09:27:31 PM UTC 24 |
Sep 18 09:27:38 PM UTC 24 |
331280356 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1872703447 |
|
|
Sep 18 09:27:33 PM UTC 24 |
Sep 18 09:27:39 PM UTC 24 |
110235267 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.335960053 |
|
|
Sep 18 09:27:34 PM UTC 24 |
Sep 18 09:27:39 PM UTC 24 |
104014584 ps |