| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.27 | 97.97 | 96.04 | 93.40 | 100.00 | 98.53 | 99.00 | 95.94 |
| T1001 | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4182001168 | Sep 18 09:27:22 PM UTC 24 | Sep 18 09:27:40 PM UTC 24 | 2520524524 ps | ||
| T1002 | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1158829739 | Sep 18 09:27:34 PM UTC 24 | Sep 18 09:27:41 PM UTC 24 | 323300192 ps | ||
| T1003 | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2864268031 | Sep 18 09:27:18 PM UTC 24 | Sep 18 09:27:43 PM UTC 24 | 5948893575 ps | ||
| T1004 | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1131945283 | Sep 18 09:27:16 PM UTC 24 | Sep 18 09:27:44 PM UTC 24 | 1449786303 ps | ||
| T1005 | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.4066917053 | Sep 18 09:27:24 PM UTC 24 | Sep 18 09:27:50 PM UTC 24 | 1015662765 ps | ||
| T1006 | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4826600 | Sep 18 09:27:24 PM UTC 24 | Sep 18 09:27:56 PM UTC 24 | 9470227964 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.185883360 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 1873719098 ps |
| CPU time | 15.38 seconds |
| Started | Sep 18 09:19:15 PM UTC 24 |
| Finished | Sep 18 09:19:31 PM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185883360 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.185883360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3780123639 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1899775626 ps |
| CPU time | 14.35 seconds |
| Started | Sep 18 09:19:21 PM UTC 24 |
| Finished | Sep 18 09:19:36 PM UTC 24 |
| Peak memory | 258456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780123639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ ctrl_jtag_state_post_trans.3780123639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3017353850 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 439243786 ps |
| CPU time | 18.44 seconds |
| Started | Sep 18 09:19:14 PM UTC 24 |
| Finished | Sep 18 09:19:33 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017353850 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3017353850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2566196398 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 571258623 ps |
| CPU time | 20.81 seconds |
| Started | Sep 18 09:19:25 PM UTC 24 |
| Finished | Sep 18 09:19:48 PM UTC 24 |
| Peak memory | 231724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566196398 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2566196398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3839174835 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 11335461971 ps |
| CPU time | 93.21 seconds |
| Started | Sep 18 09:19:28 PM UTC 24 |
| Finished | Sep 18 09:21:03 PM UTC 24 |
| Peak memory | 264584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3839174835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 0.lc_ctrl_stress_all.3839174835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.1706010323 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1910018659 ps |
| CPU time | 13.87 seconds |
| Started | Sep 18 09:20:01 PM UTC 24 |
| Finished | Sep 18 09:20:16 PM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706010323 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1706010323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1274211490 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 18170951 ps |
| CPU time | 1.32 seconds |
| Started | Sep 18 09:19:34 PM UTC 24 |
| Finished | Sep 18 09:19:36 PM UTC 24 |
| Peak memory | 217360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274211490 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. lc_ctrl_volatile_unlock_smoke.1274211490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.4281868328 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 31385470900 ps |
| CPU time | 131.28 seconds |
| Started | Sep 18 09:19:29 PM UTC 24 |
| Finished | Sep 18 09:21:43 PM UTC 24 |
| Peak memory | 289228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281868328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.4281868328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3280109454 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7988344115 ps |
| CPU time | 9.61 seconds |
| Started | Sep 18 09:19:22 PM UTC 24 |
| Finished | Sep 18 09:19:33 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280109454 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3280109454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.4081967253 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1240222806 ps |
| CPU time | 10.02 seconds |
| Started | Sep 18 09:22:13 PM UTC 24 |
| Finished | Sep 18 09:22:24 PM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081967253 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.4081967253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.669365531 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 504917153 ps |
| CPU time | 28.67 seconds |
| Started | Sep 18 09:19:54 PM UTC 24 |
| Finished | Sep 18 09:20:24 PM UTC 24 |
| Peak memory | 289724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669365531 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.669365531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4276465575 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 645187688 ps |
| CPU time | 3.77 seconds |
| Started | Sep 18 09:27:01 PM UTC 24 |
| Finished | Sep 18 09:27:06 PM UTC 24 |
| Peak memory | 235868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276465575 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_ intg_err.4276465575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.808944231 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3306352985 ps |
| CPU time | 53.94 seconds |
| Started | Sep 18 09:19:20 PM UTC 24 |
| Finished | Sep 18 09:20:15 PM UTC 24 |
| Peak memory | 289104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808944231 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl _jtag_state_failure.808944231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2804363376 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 26309427092 ps |
| CPU time | 115.5 seconds |
| Started | Sep 18 09:22:52 PM UTC 24 |
| Finished | Sep 18 09:24:49 PM UTC 24 |
| Peak memory | 241856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804363376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2804363376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2713553216 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1241319021 ps |
| CPU time | 7.14 seconds |
| Started | Sep 18 09:26:59 PM UTC 24 |
| Finished | Sep 18 09:27:07 PM UTC 24 |
| Peak memory | 231824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713553216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2713553216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1160589270 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4870636199 ps |
| CPU time | 14.03 seconds |
| Started | Sep 18 09:19:27 PM UTC 24 |
| Finished | Sep 18 09:19:43 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160589270 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_ mux.1160589270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2823311542 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 15131494 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 09:23:02 PM UTC 24 |
| Finished | Sep 18 09:23:04 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823311542 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15 .lc_ctrl_volatile_unlock_smoke.2823311542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.562302893 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 17316901 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 09:27:31 PM UTC 24 |
| Finished | Sep 18 09:27:34 PM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562302893 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.562302893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2730112450 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 22503342 ps |
| CPU time | 1.52 seconds |
| Started | Sep 18 09:19:31 PM UTC 24 |
| Finished | Sep 18 09:19:34 PM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730112450 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2730112450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3649129911 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8364653962 ps |
| CPU time | 62.64 seconds |
| Started | Sep 18 09:20:34 PM UTC 24 |
| Finished | Sep 18 09:21:39 PM UTC 24 |
| Peak memory | 238028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649129911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3649129911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.494388188 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 996348660 ps |
| CPU time | 47.08 seconds |
| Started | Sep 18 09:20:04 PM UTC 24 |
| Finished | Sep 18 09:20:52 PM UTC 24 |
| Peak memory | 262372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494388188 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl _jtag_state_failure.494388188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1149368022 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 36572882 ps |
| CPU time | 2.69 seconds |
| Started | Sep 18 09:27:13 PM UTC 24 |
| Finished | Sep 18 09:27:17 PM UTC 24 |
| Peak memory | 231676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149368022 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1149368022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1898297007 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 457285171 ps |
| CPU time | 3.98 seconds |
| Started | Sep 18 09:27:07 PM UTC 24 |
| Finished | Sep 18 09:27:12 PM UTC 24 |
| Peak memory | 229996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898297007 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_ intg_err.1898297007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1462435091 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 52381350 ps |
| CPU time | 3.83 seconds |
| Started | Sep 18 09:19:33 PM UTC 24 |
| Finished | Sep 18 09:19:38 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462435091 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1462435091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.335960053 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 104014584 ps |
| CPU time | 3.78 seconds |
| Started | Sep 18 09:27:34 PM UTC 24 |
| Finished | Sep 18 09:27:39 PM UTC 24 |
| Peak memory | 235864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335960053 -asse rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_ intg_err.335960053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3279873745 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 654584291 ps |
| CPU time | 5.45 seconds |
| Started | Sep 18 09:19:14 PM UTC 24 |
| Finished | Sep 18 09:19:20 PM UTC 24 |
| Peak memory | 233848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279873745 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3279873745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3538249262 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 20345046568 ps |
| CPU time | 95.02 seconds |
| Started | Sep 18 09:19:53 PM UTC 24 |
| Finished | Sep 18 09:21:30 PM UTC 24 |
| Peak memory | 281044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538249262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.3538249262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2726212825 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 178418355 ps |
| CPU time | 1.94 seconds |
| Started | Sep 18 09:26:59 PM UTC 24 |
| Finished | Sep 18 09:27:02 PM UTC 24 |
| Peak memory | 218668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2726212825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2726212825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1478259770 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 46090046 ps |
| CPU time | 2.12 seconds |
| Started | Sep 18 09:27:16 PM UTC 24 |
| Finished | Sep 18 09:27:19 PM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478259770 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_ intg_err.1478259770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.527930335 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 4958220536 ps |
| CPU time | 96.05 seconds |
| Started | Sep 18 09:23:02 PM UTC 24 |
| Finished | Sep 18 09:24:40 PM UTC 24 |
| Peak memory | 295388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527930335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.527930335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2240265190 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 121895810 ps |
| CPU time | 3.16 seconds |
| Started | Sep 18 09:27:04 PM UTC 24 |
| Finished | Sep 18 09:27:09 PM UTC 24 |
| Peak memory | 235684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240265190 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_ intg_err.2240265190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.1087070888 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 243042570 ps |
| CPU time | 11.78 seconds |
| Started | Sep 18 09:19:50 PM UTC 24 |
| Finished | Sep 18 09:20:03 PM UTC 24 |
| Peak memory | 229740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087070888 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1087070888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.1491949801 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 4469224994 ps |
| CPU time | 61.14 seconds |
| Started | Sep 18 09:23:27 PM UTC 24 |
| Finished | Sep 18 09:24:30 PM UTC 24 |
| Peak memory | 237760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491949801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.1491949801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.147849529 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 12232442162 ps |
| CPU time | 96.69 seconds |
| Started | Sep 18 09:19:52 PM UTC 24 |
| Finished | Sep 18 09:21:31 PM UTC 24 |
| Peak memory | 281020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=147849529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 1.lc_ctrl_stress_all.147849529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3920829799 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 32384574 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 09:19:18 PM UTC 24 |
| Finished | Sep 18 09:19:21 PM UTC 24 |
| Peak memory | 217912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920829799 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3920829799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3483680673 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 599636928 ps |
| CPU time | 3.78 seconds |
| Started | Sep 18 09:27:29 PM UTC 24 |
| Finished | Sep 18 09:27:34 PM UTC 24 |
| Peak memory | 229720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483680673 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl _intg_err.3483680673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.425015505 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 198916003 ps |
| CPU time | 3.83 seconds |
| Started | Sep 18 09:27:21 PM UTC 24 |
| Finished | Sep 18 09:27:26 PM UTC 24 |
| Peak memory | 229980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425015505 -asse rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_i ntg_err.425015505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.2448014791 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 34339366 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 09:20:02 PM UTC 24 |
| Finished | Sep 18 09:20:05 PM UTC 24 |
| Peak memory | 217912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448014791 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2448014791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4130201355 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 278022730 ps |
| CPU time | 2.95 seconds |
| Started | Sep 18 09:26:57 PM UTC 24 |
| Finished | Sep 18 09:27:01 PM UTC 24 |
| Peak memory | 221452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4130201355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.4130201355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2312770733 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 414234004 ps |
| CPU time | 2.95 seconds |
| Started | Sep 18 09:27:26 PM UTC 24 |
| Finished | Sep 18 09:27:30 PM UTC 24 |
| Peak memory | 235860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312770733 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl _intg_err.2312770733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3948470582 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 114790972 ps |
| CPU time | 4.39 seconds |
| Started | Sep 18 09:27:27 PM UTC 24 |
| Finished | Sep 18 09:27:33 PM UTC 24 |
| Peak memory | 229796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948470582 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl _intg_err.3948470582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2628208469 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 956009828 ps |
| CPU time | 3.09 seconds |
| Started | Sep 18 09:27:29 PM UTC 24 |
| Finished | Sep 18 09:27:34 PM UTC 24 |
| Peak memory | 230052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628208469 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl _intg_err.2628208469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2133834983 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 415912601 ps |
| CPU time | 4.1 seconds |
| Started | Sep 18 09:27:25 PM UTC 24 |
| Finished | Sep 18 09:27:30 PM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133834983 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_ intg_err.2133834983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.3365272291 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3425238662 ps |
| CPU time | 12.26 seconds |
| Started | Sep 18 09:25:41 PM UTC 24 |
| Finished | Sep 18 09:25:55 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365272291 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3365272291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.3690867922 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 4128612487 ps |
| CPU time | 126.44 seconds |
| Started | Sep 18 09:20:51 PM UTC 24 |
| Finished | Sep 18 09:22:59 PM UTC 24 |
| Peak memory | 262856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3690867922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 4.lc_ctrl_stress_all.3690867922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.3925785183 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 276454993 ps |
| CPU time | 22.03 seconds |
| Started | Sep 18 09:19:16 PM UTC 24 |
| Finished | Sep 18 09:19:39 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925785183 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3925785183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1649770131 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 23598263 ps |
| CPU time | 1.86 seconds |
| Started | Sep 18 09:27:01 PM UTC 24 |
| Finished | Sep 18 09:27:04 PM UTC 24 |
| Peak memory | 218784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649770131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_al iasing.1649770131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3209792025 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 72787651 ps |
| CPU time | 1.86 seconds |
| Started | Sep 18 09:27:01 PM UTC 24 |
| Finished | Sep 18 09:27:04 PM UTC 24 |
| Peak memory | 218664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209792025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bi t_bash.3209792025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.68842702 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 14547082 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 09:27:01 PM UTC 24 |
| Finished | Sep 18 09:27:03 PM UTC 24 |
| Peak memory | 220300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68842702 -assert n opostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_r eset.68842702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.22153424 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 209835205 ps |
| CPU time | 2.26 seconds |
| Started | Sep 18 09:27:01 PM UTC 24 |
| Finished | Sep 18 09:27:04 PM UTC 24 |
| Peak memory | 231832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=22153424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.22153424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2221801067 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 64922816 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 09:27:01 PM UTC 24 |
| Finished | Sep 18 09:27:03 PM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221801067 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2221801067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.802841656 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 73447154 ps |
| CPU time | 1.56 seconds |
| Started | Sep 18 09:27:01 PM UTC 24 |
| Finished | Sep 18 09:27:03 PM UTC 24 |
| Peak memory | 218896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=802841656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.lc_ctrl_jtag_alert_test.802841656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.940307491 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 586591706 ps |
| CPU time | 7.79 seconds |
| Started | Sep 18 09:26:59 PM UTC 24 |
| Finished | Sep 18 09:27:08 PM UTC 24 |
| Peak memory | 218972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=940307491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.940307491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1508256943 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 974297938 ps |
| CPU time | 11.46 seconds |
| Started | Sep 18 09:26:59 PM UTC 24 |
| Finished | Sep 18 09:27:11 PM UTC 24 |
| Peak memory | 219532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1508256943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1508256943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.4033595176 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 130985337 ps |
| CPU time | 2 seconds |
| Started | Sep 18 09:26:57 PM UTC 24 |
| Finished | Sep 18 09:27:00 PM UTC 24 |
| Peak memory | 218992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4033595176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 0.lc_ctrl_jtag_csr_rw.4033595176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1828826664 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 22799398 ps |
| CPU time | 1.88 seconds |
| Started | Sep 18 09:27:01 PM UTC 24 |
| Finished | Sep 18 09:27:04 PM UTC 24 |
| Peak memory | 220712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182882 6664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc _ctrl_same_csr_outstanding.1828826664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.4001267789 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 541318573 ps |
| CPU time | 4.36 seconds |
| Started | Sep 18 09:27:01 PM UTC 24 |
| Finished | Sep 18 09:27:06 PM UTC 24 |
| Peak memory | 229976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001267789 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.4001267789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1939792411 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 45994266 ps |
| CPU time | 1.14 seconds |
| Started | Sep 18 09:27:04 PM UTC 24 |
| Finished | Sep 18 09:27:07 PM UTC 24 |
| Peak memory | 218728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939792411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_al iasing.1939792411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3584163969 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 28648856 ps |
| CPU time | 1.7 seconds |
| Started | Sep 18 09:27:04 PM UTC 24 |
| Finished | Sep 18 09:27:07 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584163969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bi t_bash.3584163969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1145642514 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 66314746 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 09:27:04 PM UTC 24 |
| Finished | Sep 18 09:27:07 PM UTC 24 |
| Peak memory | 220292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145642514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw _reset.1145642514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3727201681 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 29777009 ps |
| CPU time | 1.66 seconds |
| Started | Sep 18 09:27:05 PM UTC 24 |
| Finished | Sep 18 09:27:08 PM UTC 24 |
| Peak memory | 232596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3727201681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3727201681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2106935050 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 39635931 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 09:27:04 PM UTC 24 |
| Finished | Sep 18 09:27:07 PM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106935050 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2106935050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1067675216 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 91726661 ps |
| CPU time | 2.54 seconds |
| Started | Sep 18 09:27:04 PM UTC 24 |
| Finished | Sep 18 09:27:08 PM UTC 24 |
| Peak memory | 219108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1067675216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1067675216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.938962974 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 187614027 ps |
| CPU time | 3.59 seconds |
| Started | Sep 18 09:27:02 PM UTC 24 |
| Finished | Sep 18 09:27:07 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=938962974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.938962974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1547576021 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 2071763994 ps |
| CPU time | 18.04 seconds |
| Started | Sep 18 09:27:02 PM UTC 24 |
| Finished | Sep 18 09:27:22 PM UTC 24 |
| Peak memory | 219180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1547576021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1547576021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2975048376 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 261906387 ps |
| CPU time | 3.05 seconds |
| Started | Sep 18 09:27:02 PM UTC 24 |
| Finished | Sep 18 09:27:07 PM UTC 24 |
| Peak memory | 221456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2975048376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2975048376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3891593040 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 362417085 ps |
| CPU time | 2.2 seconds |
| Started | Sep 18 09:27:04 PM UTC 24 |
| Finished | Sep 18 09:27:08 PM UTC 24 |
| Peak memory | 231676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891593040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3891593040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3901553276 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 69774059 ps |
| CPU time | 1.16 seconds |
| Started | Sep 18 09:27:02 PM UTC 24 |
| Finished | Sep 18 09:27:05 PM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3901553276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 1.lc_ctrl_jtag_csr_rw.3901553276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3245071491 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 91471633 ps |
| CPU time | 1.47 seconds |
| Started | Sep 18 09:27:02 PM UTC 24 |
| Finished | Sep 18 09:27:05 PM UTC 24 |
| Peak memory | 218732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3245071491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3245071491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3417370470 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 105752029 ps |
| CPU time | 1.2 seconds |
| Started | Sep 18 09:27:05 PM UTC 24 |
| Finished | Sep 18 09:27:08 PM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341737 0470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc _ctrl_same_csr_outstanding.3417370470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1274740128 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 111170078 ps |
| CPU time | 2.94 seconds |
| Started | Sep 18 09:27:04 PM UTC 24 |
| Finished | Sep 18 09:27:08 PM UTC 24 |
| Peak memory | 229760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274740128 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1274740128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3622147219 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 114178697 ps |
| CPU time | 1.35 seconds |
| Started | Sep 18 09:27:26 PM UTC 24 |
| Finished | Sep 18 09:27:29 PM UTC 24 |
| Peak memory | 228612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3622147219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3622147219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1363498576 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 44984274 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 09:27:26 PM UTC 24 |
| Finished | Sep 18 09:27:28 PM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363498576 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1363498576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1580461291 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 43892883 ps |
| CPU time | 1.93 seconds |
| Started | Sep 18 09:27:26 PM UTC 24 |
| Finished | Sep 18 09:27:29 PM UTC 24 |
| Peak memory | 218828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158046 1291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.l c_ctrl_same_csr_outstanding.1580461291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2509499449 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 159114100 ps |
| CPU time | 2.61 seconds |
| Started | Sep 18 09:27:26 PM UTC 24 |
| Finished | Sep 18 09:27:30 PM UTC 24 |
| Peak memory | 229716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509499449 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2509499449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1123051272 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 25993782 ps |
| CPU time | 1.62 seconds |
| Started | Sep 18 09:27:27 PM UTC 24 |
| Finished | Sep 18 09:27:30 PM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1123051272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1123051272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2649581542 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 35732137 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 09:27:27 PM UTC 24 |
| Finished | Sep 18 09:27:30 PM UTC 24 |
| Peak memory | 218452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649581542 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2649581542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1451581474 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 41792534 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 09:27:27 PM UTC 24 |
| Finished | Sep 18 09:27:30 PM UTC 24 |
| Peak memory | 218776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145158 1474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.l c_ctrl_same_csr_outstanding.1451581474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3908415507 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 81243520 ps |
| CPU time | 2.69 seconds |
| Started | Sep 18 09:27:26 PM UTC 24 |
| Finished | Sep 18 09:27:30 PM UTC 24 |
| Peak memory | 229716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908415507 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3908415507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.16643105 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 49102257 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 09:27:29 PM UTC 24 |
| Finished | Sep 18 09:27:31 PM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=16643105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.16643105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2093756541 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 17318941 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 09:27:28 PM UTC 24 |
| Finished | Sep 18 09:27:30 PM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093756541 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2093756541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3098881076 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 22561161 ps |
| CPU time | 1.65 seconds |
| Started | Sep 18 09:27:28 PM UTC 24 |
| Finished | Sep 18 09:27:31 PM UTC 24 |
| Peak memory | 218740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309888 1076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.l c_ctrl_same_csr_outstanding.3098881076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2856951710 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 331538552 ps |
| CPU time | 3.01 seconds |
| Started | Sep 18 09:27:28 PM UTC 24 |
| Finished | Sep 18 09:27:32 PM UTC 24 |
| Peak memory | 229988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856951710 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2856951710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4285844763 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 60278388 ps |
| CPU time | 1.92 seconds |
| Started | Sep 18 09:27:28 PM UTC 24 |
| Finished | Sep 18 09:27:31 PM UTC 24 |
| Peak memory | 232644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285844763 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl _intg_err.4285844763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3594574244 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 100110982 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 09:27:29 PM UTC 24 |
| Finished | Sep 18 09:27:32 PM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3594574244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3594574244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3942232502 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 63524066 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 09:27:29 PM UTC 24 |
| Finished | Sep 18 09:27:32 PM UTC 24 |
| Peak memory | 218696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942232502 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3942232502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.881754834 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 48211627 ps |
| CPU time | 1.09 seconds |
| Started | Sep 18 09:27:29 PM UTC 24 |
| Finished | Sep 18 09:27:32 PM UTC 24 |
| Peak memory | 218668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881754 834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc _ctrl_same_csr_outstanding.881754834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.70006946 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 45667585 ps |
| CPU time | 3.33 seconds |
| Started | Sep 18 09:27:29 PM UTC 24 |
| Finished | Sep 18 09:27:34 PM UTC 24 |
| Peak memory | 229728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70006946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.70006946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2532050855 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 21988606 ps |
| CPU time | 1.43 seconds |
| Started | Sep 18 09:27:31 PM UTC 24 |
| Finished | Sep 18 09:27:34 PM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2532050855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2532050855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.29153460 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 48195690 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 09:27:31 PM UTC 24 |
| Finished | Sep 18 09:27:33 PM UTC 24 |
| Peak memory | 218700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29153460 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.29153460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3645987626 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 27658761 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 09:27:31 PM UTC 24 |
| Finished | Sep 18 09:27:33 PM UTC 24 |
| Peak memory | 218432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364598 7626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.l c_ctrl_same_csr_outstanding.3645987626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2706287707 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 252368654 ps |
| CPU time | 2.08 seconds |
| Started | Sep 18 09:27:29 PM UTC 24 |
| Finished | Sep 18 09:27:33 PM UTC 24 |
| Peak memory | 229792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706287707 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2706287707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.35991144 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 66631388 ps |
| CPU time | 1.34 seconds |
| Started | Sep 18 09:27:31 PM UTC 24 |
| Finished | Sep 18 09:27:34 PM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=35991144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.35991144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4008664519 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 51563785 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 09:27:31 PM UTC 24 |
| Finished | Sep 18 09:27:34 PM UTC 24 |
| Peak memory | 218680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400866 4519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.l c_ctrl_same_csr_outstanding.4008664519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1662437689 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 331280356 ps |
| CPU time | 4.97 seconds |
| Started | Sep 18 09:27:31 PM UTC 24 |
| Finished | Sep 18 09:27:38 PM UTC 24 |
| Peak memory | 229988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662437689 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1662437689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.606570904 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 126301553 ps |
| CPU time | 2.81 seconds |
| Started | Sep 18 09:27:31 PM UTC 24 |
| Finished | Sep 18 09:27:35 PM UTC 24 |
| Peak memory | 229796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606570904 -asse rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_ intg_err.606570904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.512130835 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 121251693 ps |
| CPU time | 1.23 seconds |
| Started | Sep 18 09:27:31 PM UTC 24 |
| Finished | Sep 18 09:27:34 PM UTC 24 |
| Peak memory | 228500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=512130835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.512130835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2159929171 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 34837233 ps |
| CPU time | 1.11 seconds |
| Started | Sep 18 09:27:31 PM UTC 24 |
| Finished | Sep 18 09:27:34 PM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159929171 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2159929171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2419795455 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 45727495 ps |
| CPU time | 1.21 seconds |
| Started | Sep 18 09:27:31 PM UTC 24 |
| Finished | Sep 18 09:27:34 PM UTC 24 |
| Peak memory | 218492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241979 5455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.l c_ctrl_same_csr_outstanding.2419795455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3122245941 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 645549503 ps |
| CPU time | 3.8 seconds |
| Started | Sep 18 09:27:31 PM UTC 24 |
| Finished | Sep 18 09:27:36 PM UTC 24 |
| Peak memory | 229768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122245941 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3122245941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2280898503 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 374843503 ps |
| CPU time | 2.79 seconds |
| Started | Sep 18 09:27:31 PM UTC 24 |
| Finished | Sep 18 09:27:35 PM UTC 24 |
| Peak memory | 235940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280898503 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl _intg_err.2280898503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1439723070 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 36684419 ps |
| CPU time | 1.83 seconds |
| Started | Sep 18 09:27:33 PM UTC 24 |
| Finished | Sep 18 09:27:36 PM UTC 24 |
| Peak memory | 230544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1439723070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1439723070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.517155672 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 14508893 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 09:27:33 PM UTC 24 |
| Finished | Sep 18 09:27:35 PM UTC 24 |
| Peak memory | 218960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517155672 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.517155672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.465867973 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 42663827 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 09:27:33 PM UTC 24 |
| Finished | Sep 18 09:27:36 PM UTC 24 |
| Peak memory | 218728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465867 973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc _ctrl_same_csr_outstanding.465867973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4274785219 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 24801995 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 09:27:31 PM UTC 24 |
| Finished | Sep 18 09:27:35 PM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274785219 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.4274785219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.958623075 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 43613105 ps |
| CPU time | 1.87 seconds |
| Started | Sep 18 09:27:33 PM UTC 24 |
| Finished | Sep 18 09:27:36 PM UTC 24 |
| Peak memory | 234052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958623075 -asse rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_ intg_err.958623075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1322987258 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 122928900 ps |
| CPU time | 1.46 seconds |
| Started | Sep 18 09:27:34 PM UTC 24 |
| Finished | Sep 18 09:27:37 PM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1322987258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1322987258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2584782888 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 23358833 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 09:27:33 PM UTC 24 |
| Finished | Sep 18 09:27:36 PM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584782888 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2584782888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4215168813 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 31858053 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 09:27:33 PM UTC 24 |
| Finished | Sep 18 09:27:36 PM UTC 24 |
| Peak memory | 218720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421516 8813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.l c_ctrl_same_csr_outstanding.4215168813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2199220121 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 82640441 ps |
| CPU time | 1.99 seconds |
| Started | Sep 18 09:27:33 PM UTC 24 |
| Finished | Sep 18 09:27:36 PM UTC 24 |
| Peak memory | 228520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199220121 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2199220121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1872703447 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 110235267 ps |
| CPU time | 4.24 seconds |
| Started | Sep 18 09:27:33 PM UTC 24 |
| Finished | Sep 18 09:27:39 PM UTC 24 |
| Peak memory | 229932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872703447 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl _intg_err.1872703447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2897747235 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 20325630 ps |
| CPU time | 1.55 seconds |
| Started | Sep 18 09:27:35 PM UTC 24 |
| Finished | Sep 18 09:27:37 PM UTC 24 |
| Peak memory | 232592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2897747235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2897747235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.258241747 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 18587782 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 09:27:34 PM UTC 24 |
| Finished | Sep 18 09:27:37 PM UTC 24 |
| Peak memory | 218336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258241747 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.258241747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3245688608 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 43724445 ps |
| CPU time | 1.58 seconds |
| Started | Sep 18 09:27:35 PM UTC 24 |
| Finished | Sep 18 09:27:37 PM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324568 8608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.l c_ctrl_same_csr_outstanding.3245688608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1158829739 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 323300192 ps |
| CPU time | 5.44 seconds |
| Started | Sep 18 09:27:34 PM UTC 24 |
| Finished | Sep 18 09:27:41 PM UTC 24 |
| Peak memory | 229796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158829739 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1158829739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.153164119 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 48030246 ps |
| CPU time | 1.19 seconds |
| Started | Sep 18 09:27:08 PM UTC 24 |
| Finished | Sep 18 09:27:11 PM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153164119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_ali asing.153164119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3981882385 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 184307332 ps |
| CPU time | 1.61 seconds |
| Started | Sep 18 09:27:08 PM UTC 24 |
| Finished | Sep 18 09:27:11 PM UTC 24 |
| Peak memory | 218580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981882385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bi t_bash.3981882385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2643611154 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 55330193 ps |
| CPU time | 1.58 seconds |
| Started | Sep 18 09:27:07 PM UTC 24 |
| Finished | Sep 18 09:27:10 PM UTC 24 |
| Peak memory | 220292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643611154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw _reset.2643611154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3232735988 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 63795525 ps |
| CPU time | 2.37 seconds |
| Started | Sep 18 09:27:08 PM UTC 24 |
| Finished | Sep 18 09:27:12 PM UTC 24 |
| Peak memory | 230048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3232735988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3232735988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2190442899 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 93048505 ps |
| CPU time | 1.2 seconds |
| Started | Sep 18 09:27:08 PM UTC 24 |
| Finished | Sep 18 09:27:11 PM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190442899 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2190442899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.338956128 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 278409676 ps |
| CPU time | 1.66 seconds |
| Started | Sep 18 09:27:07 PM UTC 24 |
| Finished | Sep 18 09:27:10 PM UTC 24 |
| Peak memory | 218896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=338956128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.lc_ctrl_jtag_alert_test.338956128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1792861850 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 730126257 ps |
| CPU time | 15.27 seconds |
| Started | Sep 18 09:27:06 PM UTC 24 |
| Finished | Sep 18 09:27:22 PM UTC 24 |
| Peak memory | 218788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1792861850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1792861850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3803650880 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 3991418399 ps |
| CPU time | 23.14 seconds |
| Started | Sep 18 09:27:06 PM UTC 24 |
| Finished | Sep 18 09:27:30 PM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3803650880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3803650880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3829048516 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 171805977 ps |
| CPU time | 2.15 seconds |
| Started | Sep 18 09:27:06 PM UTC 24 |
| Finished | Sep 18 09:27:09 PM UTC 24 |
| Peak memory | 221472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3829048516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3829048516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1576028120 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 648130228 ps |
| CPU time | 2.94 seconds |
| Started | Sep 18 09:27:06 PM UTC 24 |
| Finished | Sep 18 09:27:10 PM UTC 24 |
| Peak memory | 233872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576028120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1576028120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1430378623 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 280615496 ps |
| CPU time | 2.73 seconds |
| Started | Sep 18 09:27:06 PM UTC 24 |
| Finished | Sep 18 09:27:09 PM UTC 24 |
| Peak memory | 219404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1430378623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 2.lc_ctrl_jtag_csr_rw.1430378623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4233264516 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 403951661 ps |
| CPU time | 1.65 seconds |
| Started | Sep 18 09:27:06 PM UTC 24 |
| Finished | Sep 18 09:27:08 PM UTC 24 |
| Peak memory | 220776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4233264516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4233264516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.837735484 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 171423765 ps |
| CPU time | 2.19 seconds |
| Started | Sep 18 09:27:08 PM UTC 24 |
| Finished | Sep 18 09:27:12 PM UTC 24 |
| Peak memory | 221908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837735 484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ ctrl_same_csr_outstanding.837735484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2491629377 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 127003059 ps |
| CPU time | 4.84 seconds |
| Started | Sep 18 09:27:07 PM UTC 24 |
| Finished | Sep 18 09:27:13 PM UTC 24 |
| Peak memory | 229992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491629377 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2491629377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2558114717 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 46487765 ps |
| CPU time | 1.79 seconds |
| Started | Sep 18 09:27:11 PM UTC 24 |
| Finished | Sep 18 09:27:15 PM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558114717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_al iasing.2558114717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3523945079 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 85983295 ps |
| CPU time | 1.87 seconds |
| Started | Sep 18 09:27:10 PM UTC 24 |
| Finished | Sep 18 09:27:14 PM UTC 24 |
| Peak memory | 218736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523945079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bi t_bash.3523945079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3996432151 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 232358716 ps |
| CPU time | 1.23 seconds |
| Started | Sep 18 09:27:10 PM UTC 24 |
| Finished | Sep 18 09:27:13 PM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996432151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw _reset.3996432151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.919996888 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 51947250 ps |
| CPU time | 1.35 seconds |
| Started | Sep 18 09:27:11 PM UTC 24 |
| Finished | Sep 18 09:27:14 PM UTC 24 |
| Peak memory | 232592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=919996888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.919996888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1052685291 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 31295457 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 09:27:10 PM UTC 24 |
| Finished | Sep 18 09:27:13 PM UTC 24 |
| Peak memory | 218540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052685291 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1052685291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2564887197 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 30580477 ps |
| CPU time | 1.01 seconds |
| Started | Sep 18 09:27:10 PM UTC 24 |
| Finished | Sep 18 09:27:13 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2564887197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2564887197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3720896048 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 1405345451 ps |
| CPU time | 9.61 seconds |
| Started | Sep 18 09:27:09 PM UTC 24 |
| Finished | Sep 18 09:27:21 PM UTC 24 |
| Peak memory | 218312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3720896048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3720896048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3110491282 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 4405256742 ps |
| CPU time | 12.87 seconds |
| Started | Sep 18 09:27:09 PM UTC 24 |
| Finished | Sep 18 09:27:24 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3110491282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3110491282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.706968495 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 390657763 ps |
| CPU time | 2 seconds |
| Started | Sep 18 09:27:08 PM UTC 24 |
| Finished | Sep 18 09:27:12 PM UTC 24 |
| Peak memory | 220652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=706968495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.706968495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1990704279 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 130091076 ps |
| CPU time | 2.26 seconds |
| Started | Sep 18 09:27:10 PM UTC 24 |
| Finished | Sep 18 09:27:14 PM UTC 24 |
| Peak memory | 231684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990704279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1990704279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.776745533 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 151652986 ps |
| CPU time | 2.49 seconds |
| Started | Sep 18 09:27:09 PM UTC 24 |
| Finished | Sep 18 09:27:13 PM UTC 24 |
| Peak memory | 219484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=776745533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.lc_ctrl_jtag_csr_rw.776745533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3066936309 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 21014106 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 09:27:10 PM UTC 24 |
| Finished | Sep 18 09:27:13 PM UTC 24 |
| Peak memory | 218072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3066936309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3066936309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.108949063 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 170901819 ps |
| CPU time | 2.08 seconds |
| Started | Sep 18 09:27:11 PM UTC 24 |
| Finished | Sep 18 09:27:15 PM UTC 24 |
| Peak memory | 221592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108949 063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ ctrl_same_csr_outstanding.108949063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.223636013 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 319254820 ps |
| CPU time | 3.5 seconds |
| Started | Sep 18 09:27:10 PM UTC 24 |
| Finished | Sep 18 09:27:16 PM UTC 24 |
| Peak memory | 229612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223636013 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.223636013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4093681121 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 179343806 ps |
| CPU time | 2.3 seconds |
| Started | Sep 18 09:27:10 PM UTC 24 |
| Finished | Sep 18 09:27:14 PM UTC 24 |
| Peak memory | 229792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093681121 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_ intg_err.4093681121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1020868783 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 75603364 ps |
| CPU time | 1.34 seconds |
| Started | Sep 18 09:27:14 PM UTC 24 |
| Finished | Sep 18 09:27:17 PM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020868783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_al iasing.1020868783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1017818568 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 68331737 ps |
| CPU time | 2.24 seconds |
| Started | Sep 18 09:27:14 PM UTC 24 |
| Finished | Sep 18 09:27:18 PM UTC 24 |
| Peak memory | 219424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017818568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bi t_bash.1017818568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2752901779 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 21003379 ps |
| CPU time | 1.35 seconds |
| Started | Sep 18 09:27:13 PM UTC 24 |
| Finished | Sep 18 09:27:16 PM UTC 24 |
| Peak memory | 220228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752901779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw _reset.2752901779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2302572878 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 59836565 ps |
| CPU time | 1.69 seconds |
| Started | Sep 18 09:27:14 PM UTC 24 |
| Finished | Sep 18 09:27:17 PM UTC 24 |
| Peak memory | 228260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2302572878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2302572878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3066386178 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 52867989 ps |
| CPU time | 1.32 seconds |
| Started | Sep 18 09:27:13 PM UTC 24 |
| Finished | Sep 18 09:27:16 PM UTC 24 |
| Peak memory | 228488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066386178 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3066386178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1259480719 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 123962442 ps |
| CPU time | 2.33 seconds |
| Started | Sep 18 09:27:13 PM UTC 24 |
| Finished | Sep 18 09:27:17 PM UTC 24 |
| Peak memory | 218376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1259480719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1259480719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2893315404 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 5205680783 ps |
| CPU time | 13 seconds |
| Started | Sep 18 09:27:13 PM UTC 24 |
| Finished | Sep 18 09:27:27 PM UTC 24 |
| Peak memory | 218860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2893315404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2893315404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.865218338 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 1042572397 ps |
| CPU time | 12.57 seconds |
| Started | Sep 18 09:27:13 PM UTC 24 |
| Finished | Sep 18 09:27:27 PM UTC 24 |
| Peak memory | 219612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=865218338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.865218338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3212972570 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 147005136 ps |
| CPU time | 2.23 seconds |
| Started | Sep 18 09:27:11 PM UTC 24 |
| Finished | Sep 18 09:27:15 PM UTC 24 |
| Peak memory | 221732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3212972570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3212972570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1100773579 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 392697198 ps |
| CPU time | 1.78 seconds |
| Started | Sep 18 09:27:13 PM UTC 24 |
| Finished | Sep 18 09:27:16 PM UTC 24 |
| Peak memory | 228492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100773579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1100773579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2143005670 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 368266547 ps |
| CPU time | 1.71 seconds |
| Started | Sep 18 09:27:12 PM UTC 24 |
| Finished | Sep 18 09:27:14 PM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2143005670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.lc_ctrl_jtag_csr_rw.2143005670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.193146613 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 148099707 ps |
| CPU time | 2.27 seconds |
| Started | Sep 18 09:27:13 PM UTC 24 |
| Finished | Sep 18 09:27:16 PM UTC 24 |
| Peak memory | 219708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=193146613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.193146613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1021863610 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 370930899 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 09:27:14 PM UTC 24 |
| Finished | Sep 18 09:27:17 PM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102186 3610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc _ctrl_same_csr_outstanding.1021863610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.892347892 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 109909743 ps |
| CPU time | 3.98 seconds |
| Started | Sep 18 09:27:13 PM UTC 24 |
| Finished | Sep 18 09:27:18 PM UTC 24 |
| Peak memory | 229712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892347892 -asse rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_i ntg_err.892347892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1521865290 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 62810622 ps |
| CPU time | 1.13 seconds |
| Started | Sep 18 09:27:17 PM UTC 24 |
| Finished | Sep 18 09:27:20 PM UTC 24 |
| Peak memory | 228500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1521865290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1521865290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1723703398 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 59617553 ps |
| CPU time | 1.18 seconds |
| Started | Sep 18 09:27:16 PM UTC 24 |
| Finished | Sep 18 09:27:18 PM UTC 24 |
| Peak memory | 218188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723703398 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1723703398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.405961868 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 13583599 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 09:27:16 PM UTC 24 |
| Finished | Sep 18 09:27:18 PM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=405961868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.lc_ctrl_jtag_alert_test.405961868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1131945283 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 1449786303 ps |
| CPU time | 26.48 seconds |
| Started | Sep 18 09:27:16 PM UTC 24 |
| Finished | Sep 18 09:27:44 PM UTC 24 |
| Peak memory | 219052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1131945283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1131945283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4108906848 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 1469689968 ps |
| CPU time | 5.52 seconds |
| Started | Sep 18 09:27:16 PM UTC 24 |
| Finished | Sep 18 09:27:23 PM UTC 24 |
| Peak memory | 219484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4108906848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4108906848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1976320304 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 246661175 ps |
| CPU time | 2.3 seconds |
| Started | Sep 18 09:27:14 PM UTC 24 |
| Finished | Sep 18 09:27:18 PM UTC 24 |
| Peak memory | 221392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1976320304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1976320304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.499197095 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 171975519 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 09:27:16 PM UTC 24 |
| Finished | Sep 18 09:27:19 PM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499197095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_ena bled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.499197095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3177454490 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 66765951 ps |
| CPU time | 1.13 seconds |
| Started | Sep 18 09:27:14 PM UTC 24 |
| Finished | Sep 18 09:27:17 PM UTC 24 |
| Peak memory | 218896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3177454490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 5.lc_ctrl_jtag_csr_rw.3177454490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2391429374 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 17253385 ps |
| CPU time | 1.3 seconds |
| Started | Sep 18 09:27:16 PM UTC 24 |
| Finished | Sep 18 09:27:18 PM UTC 24 |
| Peak memory | 218296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2391429374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2391429374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.291257697 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 152739783 ps |
| CPU time | 1.97 seconds |
| Started | Sep 18 09:27:17 PM UTC 24 |
| Finished | Sep 18 09:27:20 PM UTC 24 |
| Peak memory | 228996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291257 697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ ctrl_same_csr_outstanding.291257697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3343536278 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 51638052 ps |
| CPU time | 2.31 seconds |
| Started | Sep 18 09:27:16 PM UTC 24 |
| Finished | Sep 18 09:27:19 PM UTC 24 |
| Peak memory | 229712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343536278 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3343536278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1472575277 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 43773123 ps |
| CPU time | 1.79 seconds |
| Started | Sep 18 09:27:19 PM UTC 24 |
| Finished | Sep 18 09:27:22 PM UTC 24 |
| Peak memory | 232596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1472575277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1472575277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3358767075 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 14696416 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 09:27:18 PM UTC 24 |
| Finished | Sep 18 09:27:20 PM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358767075 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3358767075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2460181806 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 21281561 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 09:27:18 PM UTC 24 |
| Finished | Sep 18 09:27:20 PM UTC 24 |
| Peak memory | 218960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2460181806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2460181806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2864268031 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 5948893575 ps |
| CPU time | 24.44 seconds |
| Started | Sep 18 09:27:18 PM UTC 24 |
| Finished | Sep 18 09:27:43 PM UTC 24 |
| Peak memory | 219604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2864268031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2864268031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.717215289 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 694544760 ps |
| CPU time | 17.11 seconds |
| Started | Sep 18 09:27:18 PM UTC 24 |
| Finished | Sep 18 09:27:36 PM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=717215289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.717215289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4071523548 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 591351267 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 09:27:17 PM UTC 24 |
| Finished | Sep 18 09:27:20 PM UTC 24 |
| Peak memory | 220652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4071523548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4071523548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.91392933 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 1399790800 ps |
| CPU time | 1.96 seconds |
| Started | Sep 18 09:27:18 PM UTC 24 |
| Finished | Sep 18 09:27:21 PM UTC 24 |
| Peak memory | 230544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91392933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enab led-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.91392933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.954789579 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 213531538 ps |
| CPU time | 3.32 seconds |
| Started | Sep 18 09:27:17 PM UTC 24 |
| Finished | Sep 18 09:27:22 PM UTC 24 |
| Peak memory | 219740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=954789579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.lc_ctrl_jtag_csr_rw.954789579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4218629390 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 64637652 ps |
| CPU time | 1.55 seconds |
| Started | Sep 18 09:27:18 PM UTC 24 |
| Finished | Sep 18 09:27:20 PM UTC 24 |
| Peak memory | 218740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4218629390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.4218629390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2134279195 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 214097840 ps |
| CPU time | 1.48 seconds |
| Started | Sep 18 09:27:19 PM UTC 24 |
| Finished | Sep 18 09:27:21 PM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213427 9195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc _ctrl_same_csr_outstanding.2134279195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3197200286 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 126502176 ps |
| CPU time | 3.63 seconds |
| Started | Sep 18 09:27:18 PM UTC 24 |
| Finished | Sep 18 09:27:22 PM UTC 24 |
| Peak memory | 229976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197200286 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3197200286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.394983919 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 849685707 ps |
| CPU time | 2.41 seconds |
| Started | Sep 18 09:27:18 PM UTC 24 |
| Finished | Sep 18 09:27:21 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394983919 -asse rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_i ntg_err.394983919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.260800449 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 21967535 ps |
| CPU time | 1.68 seconds |
| Started | Sep 18 09:27:21 PM UTC 24 |
| Finished | Sep 18 09:27:24 PM UTC 24 |
| Peak memory | 228556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=260800449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.260800449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2390276601 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 14011210 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 09:27:21 PM UTC 24 |
| Finished | Sep 18 09:27:23 PM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390276601 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2390276601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2225648804 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 47737161 ps |
| CPU time | 1.47 seconds |
| Started | Sep 18 09:27:21 PM UTC 24 |
| Finished | Sep 18 09:27:23 PM UTC 24 |
| Peak memory | 218516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2225648804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2225648804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3037627574 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 1819903941 ps |
| CPU time | 10.5 seconds |
| Started | Sep 18 09:27:19 PM UTC 24 |
| Finished | Sep 18 09:27:31 PM UTC 24 |
| Peak memory | 219108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3037627574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3037627574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3770200991 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 356587460 ps |
| CPU time | 5.13 seconds |
| Started | Sep 18 09:27:19 PM UTC 24 |
| Finished | Sep 18 09:27:25 PM UTC 24 |
| Peak memory | 219316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3770200991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3770200991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.244672964 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 890435911 ps |
| CPU time | 2.69 seconds |
| Started | Sep 18 09:27:19 PM UTC 24 |
| Finished | Sep 18 09:27:23 PM UTC 24 |
| Peak memory | 221456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=244672964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.244672964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.248944905 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 393676358 ps |
| CPU time | 3.19 seconds |
| Started | Sep 18 09:27:19 PM UTC 24 |
| Finished | Sep 18 09:27:24 PM UTC 24 |
| Peak memory | 229856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248944905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_ena bled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.248944905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1374928509 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 76541255 ps |
| CPU time | 2.81 seconds |
| Started | Sep 18 09:27:19 PM UTC 24 |
| Finished | Sep 18 09:27:23 PM UTC 24 |
| Peak memory | 219420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1374928509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 7.lc_ctrl_jtag_csr_rw.1374928509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.799805866 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 123717618 ps |
| CPU time | 1.91 seconds |
| Started | Sep 18 09:27:19 PM UTC 24 |
| Finished | Sep 18 09:27:22 PM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=799805866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.799805866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2004013255 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 47422383 ps |
| CPU time | 1.46 seconds |
| Started | Sep 18 09:27:21 PM UTC 24 |
| Finished | Sep 18 09:27:23 PM UTC 24 |
| Peak memory | 218988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200401 3255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc _ctrl_same_csr_outstanding.2004013255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4286844817 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 28163109 ps |
| CPU time | 2.21 seconds |
| Started | Sep 18 09:27:21 PM UTC 24 |
| Finished | Sep 18 09:27:24 PM UTC 24 |
| Peak memory | 229728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286844817 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.4286844817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2245281711 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 72428795 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 09:27:24 PM UTC 24 |
| Finished | Sep 18 09:27:26 PM UTC 24 |
| Peak memory | 228500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2245281711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2245281711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3767449632 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 84024327 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 09:27:23 PM UTC 24 |
| Finished | Sep 18 09:27:25 PM UTC 24 |
| Peak memory | 218756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767449632 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3767449632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3078771349 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 106833679 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 09:27:22 PM UTC 24 |
| Finished | Sep 18 09:27:25 PM UTC 24 |
| Peak memory | 218764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3078771349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3078771349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4182001168 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 2520524524 ps |
| CPU time | 16.51 seconds |
| Started | Sep 18 09:27:22 PM UTC 24 |
| Finished | Sep 18 09:27:40 PM UTC 24 |
| Peak memory | 219184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4182001168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.4182001168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3367156299 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 838029921 ps |
| CPU time | 10.36 seconds |
| Started | Sep 18 09:27:21 PM UTC 24 |
| Finished | Sep 18 09:27:32 PM UTC 24 |
| Peak memory | 218708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3367156299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3367156299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3400861292 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 305543836 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 09:27:21 PM UTC 24 |
| Finished | Sep 18 09:27:23 PM UTC 24 |
| Peak memory | 220508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3400861292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3400861292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3974355485 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 743635913 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 09:27:22 PM UTC 24 |
| Finished | Sep 18 09:27:27 PM UTC 24 |
| Peak memory | 229416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974355485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3974355485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3947892555 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 174998256 ps |
| CPU time | 1.17 seconds |
| Started | Sep 18 09:27:21 PM UTC 24 |
| Finished | Sep 18 09:27:23 PM UTC 24 |
| Peak memory | 218704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3947892555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 8.lc_ctrl_jtag_csr_rw.3947892555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2081819313 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 44924166 ps |
| CPU time | 1.87 seconds |
| Started | Sep 18 09:27:22 PM UTC 24 |
| Finished | Sep 18 09:27:25 PM UTC 24 |
| Peak memory | 220768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2081819313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2081819313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.715682194 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 187661917 ps |
| CPU time | 1.84 seconds |
| Started | Sep 18 09:27:24 PM UTC 24 |
| Finished | Sep 18 09:27:27 PM UTC 24 |
| Peak memory | 220776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715682 194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ ctrl_same_csr_outstanding.715682194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1727507125 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 102529728 ps |
| CPU time | 2.94 seconds |
| Started | Sep 18 09:27:22 PM UTC 24 |
| Finished | Sep 18 09:27:27 PM UTC 24 |
| Peak memory | 229792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727507125 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1727507125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3519861509 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 163148406 ps |
| CPU time | 2.2 seconds |
| Started | Sep 18 09:27:23 PM UTC 24 |
| Finished | Sep 18 09:27:26 PM UTC 24 |
| Peak memory | 233944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519861509 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_ intg_err.3519861509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.82607889 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 30727691 ps |
| CPU time | 2.61 seconds |
| Started | Sep 18 09:27:26 PM UTC 24 |
| Finished | Sep 18 09:27:30 PM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=82607889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.82607889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1411034439 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 14376140 ps |
| CPU time | 1.11 seconds |
| Started | Sep 18 09:27:25 PM UTC 24 |
| Finished | Sep 18 09:27:27 PM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411034439 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1411034439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2076235145 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 202401125 ps |
| CPU time | 1.83 seconds |
| Started | Sep 18 09:27:24 PM UTC 24 |
| Finished | Sep 18 09:27:27 PM UTC 24 |
| Peak memory | 218900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2076235145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2076235145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.4066917053 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 1015662765 ps |
| CPU time | 24.53 seconds |
| Started | Sep 18 09:27:24 PM UTC 24 |
| Finished | Sep 18 09:27:50 PM UTC 24 |
| Peak memory | 219248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4066917053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.4066917053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4826600 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 9470227964 ps |
| CPU time | 30.82 seconds |
| Started | Sep 18 09:27:24 PM UTC 24 |
| Finished | Sep 18 09:27:56 PM UTC 24 |
| Peak memory | 218628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4826600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.4826600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2456881234 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 73175439 ps |
| CPU time | 2.58 seconds |
| Started | Sep 18 09:27:24 PM UTC 24 |
| Finished | Sep 18 09:27:28 PM UTC 24 |
| Peak memory | 221540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2456881234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2456881234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1151845379 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 253327148 ps |
| CPU time | 2.62 seconds |
| Started | Sep 18 09:27:24 PM UTC 24 |
| Finished | Sep 18 09:27:28 PM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151845379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1151845379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1049208584 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 532067917 ps |
| CPU time | 2.04 seconds |
| Started | Sep 18 09:27:24 PM UTC 24 |
| Finished | Sep 18 09:27:27 PM UTC 24 |
| Peak memory | 219428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1049208584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 9.lc_ctrl_jtag_csr_rw.1049208584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.245341812 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 179777644 ps |
| CPU time | 1.89 seconds |
| Started | Sep 18 09:27:24 PM UTC 24 |
| Finished | Sep 18 09:27:27 PM UTC 24 |
| Peak memory | 218664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=245341812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.245341812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.192634837 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 61045447 ps |
| CPU time | 1.43 seconds |
| Started | Sep 18 09:27:25 PM UTC 24 |
| Finished | Sep 18 09:27:27 PM UTC 24 |
| Peak memory | 220840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192634 837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ ctrl_same_csr_outstanding.192634837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2688525485 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 44140305 ps |
| CPU time | 3.78 seconds |
| Started | Sep 18 09:27:24 PM UTC 24 |
| Finished | Sep 18 09:27:29 PM UTC 24 |
| Peak memory | 229720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688525485 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2688525485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.4227542101 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 3042838348 ps |
| CPU time | 57.56 seconds |
| Started | Sep 18 09:19:22 PM UTC 24 |
| Finished | Sep 18 09:20:21 PM UTC 24 |
| Peak memory | 231844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227542101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jt ag_errors.4227542101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.2758268580 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 509969389 ps |
| CPU time | 15.97 seconds |
| Started | Sep 18 09:19:24 PM UTC 24 |
| Finished | Sep 18 09:19:42 PM UTC 24 |
| Peak memory | 229352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758268580 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_prior ity.2758268580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.4288308844 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1185776766 ps |
| CPU time | 7.1 seconds |
| Started | Sep 18 09:19:21 PM UTC 24 |
| Finished | Sep 18 09:19:29 PM UTC 24 |
| Peak memory | 229676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288308844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl _jtag_prog_failure.4288308844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3790753028 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 4616760304 ps |
| CPU time | 48.54 seconds |
| Started | Sep 18 09:19:25 PM UTC 24 |
| Finished | Sep 18 09:20:16 PM UTC 24 |
| Peak memory | 229600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790753028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ ctrl_jtag_regwen_during_op.3790753028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.3259397536 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 350648577 ps |
| CPU time | 4.27 seconds |
| Started | Sep 18 09:19:19 PM UTC 24 |
| Finished | Sep 18 09:19:25 PM UTC 24 |
| Peak memory | 229544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259397536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_s moke.3259397536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.369303017 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 214479984 ps |
| CPU time | 24.49 seconds |
| Started | Sep 18 09:19:29 PM UTC 24 |
| Finished | Sep 18 09:19:55 PM UTC 24 |
| Peak memory | 297860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369303017 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.369303017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.1982402504 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3186631413 ps |
| CPU time | 27.32 seconds |
| Started | Sep 18 09:19:27 PM UTC 24 |
| Finished | Sep 18 09:19:56 PM UTC 24 |
| Peak memory | 231856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982402504 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_tok en_digest.1982402504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.3896218105 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 113548036 ps |
| CPU time | 4.23 seconds |
| Started | Sep 18 09:19:10 PM UTC 24 |
| Finished | Sep 18 09:19:15 PM UTC 24 |
| Peak memory | 225496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896218105 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3896218105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1587145473 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 264808016 ps |
| CPU time | 44.67 seconds |
| Started | Sep 18 09:19:11 PM UTC 24 |
| Finished | Sep 18 09:19:57 PM UTC 24 |
| Peak memory | 262376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587145473 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1587145473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.3750377607 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 167528477 ps |
| CPU time | 11.07 seconds |
| Started | Sep 18 09:19:12 PM UTC 24 |
| Finished | Sep 18 09:19:24 PM UTC 24 |
| Peak memory | 262280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750377607 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3750377607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.222885580 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 13974702 ps |
| CPU time | 1.52 seconds |
| Started | Sep 18 09:19:11 PM UTC 24 |
| Finished | Sep 18 09:19:14 PM UTC 24 |
| Peak memory | 220508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222885580 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.l c_ctrl_volatile_unlock_smoke.222885580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.3887223796 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 32419178 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 09:19:54 PM UTC 24 |
| Finished | Sep 18 09:19:57 PM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887223796 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3887223796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.2925857282 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 17886179 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 09:19:39 PM UTC 24 |
| Finished | Sep 18 09:19:41 PM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925857282 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2925857282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.2267766326 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 236461738 ps |
| CPU time | 14.19 seconds |
| Started | Sep 18 09:19:37 PM UTC 24 |
| Finished | Sep 18 09:19:53 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267766326 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2267766326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2950187131 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 713664620 ps |
| CPU time | 4.69 seconds |
| Started | Sep 18 09:19:46 PM UTC 24 |
| Finished | Sep 18 09:19:52 PM UTC 24 |
| Peak memory | 228856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950187131 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2950187131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.3210299113 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 32652583041 ps |
| CPU time | 126.55 seconds |
| Started | Sep 18 09:19:44 PM UTC 24 |
| Finished | Sep 18 09:21:53 PM UTC 24 |
| Peak memory | 231944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210299113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jt ag_errors.3210299113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.1030050734 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 779184586 ps |
| CPU time | 7.8 seconds |
| Started | Sep 18 09:19:47 PM UTC 24 |
| Finished | Sep 18 09:19:57 PM UTC 24 |
| Peak memory | 229056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030050734 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_prior ity.1030050734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.3336586783 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 72749439 ps |
| CPU time | 2.52 seconds |
| Started | Sep 18 09:19:43 PM UTC 24 |
| Finished | Sep 18 09:19:47 PM UTC 24 |
| Peak memory | 233772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336586783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl _jtag_prog_failure.3336586783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.276035821 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 889320511 ps |
| CPU time | 28.89 seconds |
| Started | Sep 18 09:19:50 PM UTC 24 |
| Finished | Sep 18 09:20:20 PM UTC 24 |
| Peak memory | 223324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276035821 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_c trl_jtag_regwen_during_op.276035821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3039773015 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1272079012 ps |
| CPU time | 12.39 seconds |
| Started | Sep 18 09:19:40 PM UTC 24 |
| Finished | Sep 18 09:19:53 PM UTC 24 |
| Peak memory | 223460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039773015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_s moke.3039773015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.1333184382 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1695153855 ps |
| CPU time | 56.79 seconds |
| Started | Sep 18 09:19:41 PM UTC 24 |
| Finished | Sep 18 09:20:39 PM UTC 24 |
| Peak memory | 280784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333184382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr l_jtag_state_failure.1333184382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.2521844994 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 334060733 ps |
| CPU time | 21.96 seconds |
| Started | Sep 18 09:19:42 PM UTC 24 |
| Finished | Sep 18 09:20:05 PM UTC 24 |
| Peak memory | 262284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521844994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ ctrl_jtag_state_post_trans.2521844994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.608038172 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 119828616 ps |
| CPU time | 2.97 seconds |
| Started | Sep 18 09:19:35 PM UTC 24 |
| Finished | Sep 18 09:19:40 PM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608038172 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.608038172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.3639462565 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 633852803 ps |
| CPU time | 28.55 seconds |
| Started | Sep 18 09:19:39 PM UTC 24 |
| Finished | Sep 18 09:20:09 PM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639462565 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3639462565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.2135429260 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 907501889 ps |
| CPU time | 12.87 seconds |
| Started | Sep 18 09:19:52 PM UTC 24 |
| Finished | Sep 18 09:20:06 PM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135429260 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_tok en_digest.2135429260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.2551466729 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 262850408 ps |
| CPU time | 11.97 seconds |
| Started | Sep 18 09:19:51 PM UTC 24 |
| Finished | Sep 18 09:20:04 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551466729 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_ mux.2551466729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2296449326 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1577288954 ps |
| CPU time | 10.49 seconds |
| Started | Sep 18 09:19:37 PM UTC 24 |
| Finished | Sep 18 09:19:49 PM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296449326 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2296449326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1221356836 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 625500865 ps |
| CPU time | 23.24 seconds |
| Started | Sep 18 09:19:35 PM UTC 24 |
| Finished | Sep 18 09:20:00 PM UTC 24 |
| Peak memory | 262340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221356836 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1221356836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.2474966061 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 325991922 ps |
| CPU time | 9.09 seconds |
| Started | Sep 18 09:19:35 PM UTC 24 |
| Finished | Sep 18 09:19:46 PM UTC 24 |
| Peak memory | 262344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474966061 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2474966061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.3148851494 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 68232790 ps |
| CPU time | 1.53 seconds |
| Started | Sep 18 09:22:19 PM UTC 24 |
| Finished | Sep 18 09:22:22 PM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148851494 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3148851494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.4045073107 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 1238539524 ps |
| CPU time | 16.03 seconds |
| Started | Sep 18 09:22:12 PM UTC 24 |
| Finished | Sep 18 09:22:29 PM UTC 24 |
| Peak memory | 229768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045073107 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.4045073107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.2659890588 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 849743144 ps |
| CPU time | 4.49 seconds |
| Started | Sep 18 09:22:14 PM UTC 24 |
| Finished | Sep 18 09:22:20 PM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659890588 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2659890588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.38672528 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 3518944322 ps |
| CPU time | 29.55 seconds |
| Started | Sep 18 09:22:14 PM UTC 24 |
| Finished | Sep 18 09:22:45 PM UTC 24 |
| Peak memory | 231468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38672528 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta g_errors.38672528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.4175000063 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 757883647 ps |
| CPU time | 8.66 seconds |
| Started | Sep 18 09:22:14 PM UTC 24 |
| Finished | Sep 18 09:22:24 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175000063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctr l_jtag_prog_failure.4175000063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3913269032 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 128031388 ps |
| CPU time | 2.95 seconds |
| Started | Sep 18 09:22:13 PM UTC 24 |
| Finished | Sep 18 09:22:17 PM UTC 24 |
| Peak memory | 223396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913269032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_ smoke.3913269032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.590474898 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1213128754 ps |
| CPU time | 52.97 seconds |
| Started | Sep 18 09:22:13 PM UTC 24 |
| Finished | Sep 18 09:23:07 PM UTC 24 |
| Peak memory | 282852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590474898 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctr l_jtag_state_failure.590474898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.18175489 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 5200367622 ps |
| CPU time | 24.11 seconds |
| Started | Sep 18 09:22:13 PM UTC 24 |
| Finished | Sep 18 09:22:38 PM UTC 24 |
| Peak memory | 248148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18175489 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c trl_jtag_state_post_trans.18175489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.3977832537 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 47459033 ps |
| CPU time | 3.03 seconds |
| Started | Sep 18 09:22:12 PM UTC 24 |
| Finished | Sep 18 09:22:16 PM UTC 24 |
| Peak memory | 234180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977832537 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3977832537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3267490515 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 391525372 ps |
| CPU time | 12.08 seconds |
| Started | Sep 18 09:22:15 PM UTC 24 |
| Finished | Sep 18 09:22:29 PM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267490515 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3267490515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.2679231476 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 5943375226 ps |
| CPU time | 27.28 seconds |
| Started | Sep 18 09:22:17 PM UTC 24 |
| Finished | Sep 18 09:22:45 PM UTC 24 |
| Peak memory | 237880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679231476 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_to ken_digest.2679231476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.1697455483 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 330928732 ps |
| CPU time | 8.57 seconds |
| Started | Sep 18 09:22:17 PM UTC 24 |
| Finished | Sep 18 09:22:26 PM UTC 24 |
| Peak memory | 229824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697455483 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token _mux.1697455483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2528934763 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 43938436 ps |
| CPU time | 3.47 seconds |
| Started | Sep 18 09:22:07 PM UTC 24 |
| Finished | Sep 18 09:22:12 PM UTC 24 |
| Peak memory | 235692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528934763 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2528934763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.3263445160 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 345921987 ps |
| CPU time | 32.94 seconds |
| Started | Sep 18 09:22:09 PM UTC 24 |
| Finished | Sep 18 09:22:44 PM UTC 24 |
| Peak memory | 262344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263445160 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3263445160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.2209882386 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 99375665 ps |
| CPU time | 10.71 seconds |
| Started | Sep 18 09:22:09 PM UTC 24 |
| Finished | Sep 18 09:22:21 PM UTC 24 |
| Peak memory | 262348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209882386 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2209882386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.1230035793 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 21950314716 ps |
| CPU time | 246.45 seconds |
| Started | Sep 18 09:22:18 PM UTC 24 |
| Finished | Sep 18 09:26:28 PM UTC 24 |
| Peak memory | 291208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1230035793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 10.lc_ctrl_stress_all.1230035793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.216466598 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 564816293 ps |
| CPU time | 15.78 seconds |
| Started | Sep 18 09:22:18 PM UTC 24 |
| Finished | Sep 18 09:22:35 PM UTC 24 |
| Peak memory | 256516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216466598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.216466598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1293233990 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 33669596 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 09:22:08 PM UTC 24 |
| Finished | Sep 18 09:22:11 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293233990 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10 .lc_ctrl_volatile_unlock_smoke.1293233990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.1846508456 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 61883196 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 09:22:30 PM UTC 24 |
| Finished | Sep 18 09:22:32 PM UTC 24 |
| Peak memory | 218204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846508456 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1846508456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.3927303468 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 2380874462 ps |
| CPU time | 13.17 seconds |
| Started | Sep 18 09:22:23 PM UTC 24 |
| Finished | Sep 18 09:22:37 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927303468 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3927303468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.3817137422 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2379218285 ps |
| CPU time | 12.56 seconds |
| Started | Sep 18 09:22:27 PM UTC 24 |
| Finished | Sep 18 09:22:41 PM UTC 24 |
| Peak memory | 229380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817137422 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3817137422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.1163163561 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 19946946457 ps |
| CPU time | 39.92 seconds |
| Started | Sep 18 09:22:27 PM UTC 24 |
| Finished | Sep 18 09:23:09 PM UTC 24 |
| Peak memory | 231940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163163561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_j tag_errors.1163163561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.1069412897 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 452997264 ps |
| CPU time | 10.81 seconds |
| Started | Sep 18 09:22:26 PM UTC 24 |
| Finished | Sep 18 09:22:38 PM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069412897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctr l_jtag_prog_failure.1069412897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.905333881 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 554775556 ps |
| CPU time | 2.66 seconds |
| Started | Sep 18 09:22:24 PM UTC 24 |
| Finished | Sep 18 09:22:28 PM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905333881 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_s moke.905333881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.4098908528 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2048436309 ps |
| CPU time | 38.91 seconds |
| Started | Sep 18 09:22:24 PM UTC 24 |
| Finished | Sep 18 09:23:05 PM UTC 24 |
| Peak memory | 262348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098908528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct rl_jtag_state_failure.4098908528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.2247930025 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 634255262 ps |
| CPU time | 24.27 seconds |
| Started | Sep 18 09:22:24 PM UTC 24 |
| Finished | Sep 18 09:22:50 PM UTC 24 |
| Peak memory | 262284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247930025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc _ctrl_jtag_state_post_trans.2247930025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.127856773 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 25440585 ps |
| CPU time | 2.13 seconds |
| Started | Sep 18 09:22:23 PM UTC 24 |
| Finished | Sep 18 09:22:26 PM UTC 24 |
| Peak memory | 233908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127856773 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.127856773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.4205639121 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2705976023 ps |
| CPU time | 14.86 seconds |
| Started | Sep 18 09:22:27 PM UTC 24 |
| Finished | Sep 18 09:22:43 PM UTC 24 |
| Peak memory | 231996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205639121 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.4205639121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.4099553532 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 712634398 ps |
| CPU time | 24.56 seconds |
| Started | Sep 18 09:22:29 PM UTC 24 |
| Finished | Sep 18 09:22:55 PM UTC 24 |
| Peak memory | 237344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099553532 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_to ken_digest.4099553532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.698804057 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 766279110 ps |
| CPU time | 8.28 seconds |
| Started | Sep 18 09:22:29 PM UTC 24 |
| Finished | Sep 18 09:22:39 PM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698804057 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_ mux.698804057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.2840881327 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 678056378 ps |
| CPU time | 9.88 seconds |
| Started | Sep 18 09:22:24 PM UTC 24 |
| Finished | Sep 18 09:22:35 PM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840881327 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2840881327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.1654636877 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 139385934 ps |
| CPU time | 6.55 seconds |
| Started | Sep 18 09:22:20 PM UTC 24 |
| Finished | Sep 18 09:22:28 PM UTC 24 |
| Peak memory | 229844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654636877 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1654636877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.3414532146 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 656767314 ps |
| CPU time | 37.76 seconds |
| Started | Sep 18 09:22:21 PM UTC 24 |
| Finished | Sep 18 09:23:00 PM UTC 24 |
| Peak memory | 260304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414532146 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3414532146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.3007671918 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 54420536 ps |
| CPU time | 8.72 seconds |
| Started | Sep 18 09:22:23 PM UTC 24 |
| Finished | Sep 18 09:22:33 PM UTC 24 |
| Peak memory | 262368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007671918 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3007671918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.1270035226 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2659497705 ps |
| CPU time | 67.94 seconds |
| Started | Sep 18 09:22:30 PM UTC 24 |
| Finished | Sep 18 09:23:39 PM UTC 24 |
| Peak memory | 262464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1270035226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 11.lc_ctrl_stress_all.1270035226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2228668815 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 3910546811 ps |
| CPU time | 94.96 seconds |
| Started | Sep 18 09:22:30 PM UTC 24 |
| Finished | Sep 18 09:24:07 PM UTC 24 |
| Peak memory | 291604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228668815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.2228668815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4029462835 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 18477522 ps |
| CPU time | 1.37 seconds |
| Started | Sep 18 09:22:20 PM UTC 24 |
| Finished | Sep 18 09:22:23 PM UTC 24 |
| Peak memory | 217276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029462835 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11 .lc_ctrl_volatile_unlock_smoke.4029462835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.1646011024 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 18115948 ps |
| CPU time | 1.39 seconds |
| Started | Sep 18 09:22:42 PM UTC 24 |
| Finished | Sep 18 09:22:44 PM UTC 24 |
| Peak memory | 218200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646011024 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1646011024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.702248538 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 315655919 ps |
| CPU time | 11.91 seconds |
| Started | Sep 18 09:22:34 PM UTC 24 |
| Finished | Sep 18 09:22:47 PM UTC 24 |
| Peak memory | 229696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702248538 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.702248538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.114804806 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 221071357 ps |
| CPU time | 4.9 seconds |
| Started | Sep 18 09:22:39 PM UTC 24 |
| Finished | Sep 18 09:22:45 PM UTC 24 |
| Peak memory | 228744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114804806 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.114804806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.1835670199 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 25106512800 ps |
| CPU time | 39.38 seconds |
| Started | Sep 18 09:22:39 PM UTC 24 |
| Finished | Sep 18 09:23:20 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835670199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_j tag_errors.1835670199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.1619237752 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1832664072 ps |
| CPU time | 8.09 seconds |
| Started | Sep 18 09:22:38 PM UTC 24 |
| Finished | Sep 18 09:22:47 PM UTC 24 |
| Peak memory | 236172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619237752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctr l_jtag_prog_failure.1619237752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.23195756 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 948326841 ps |
| CPU time | 7.71 seconds |
| Started | Sep 18 09:22:36 PM UTC 24 |
| Finished | Sep 18 09:22:45 PM UTC 24 |
| Peak memory | 229492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23195756 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.23195756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.4073466611 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3366657158 ps |
| CPU time | 30.17 seconds |
| Started | Sep 18 09:22:37 PM UTC 24 |
| Finished | Sep 18 09:23:08 PM UTC 24 |
| Peak memory | 262800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073466611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct rl_jtag_state_failure.4073466611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.4185847117 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1202915355 ps |
| CPU time | 43.1 seconds |
| Started | Sep 18 09:22:37 PM UTC 24 |
| Finished | Sep 18 09:23:21 PM UTC 24 |
| Peak memory | 262284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185847117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc _ctrl_jtag_state_post_trans.4185847117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.3607247887 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 125357629 ps |
| CPU time | 4.04 seconds |
| Started | Sep 18 09:22:34 PM UTC 24 |
| Finished | Sep 18 09:22:39 PM UTC 24 |
| Peak memory | 233920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607247887 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3607247887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.2924998556 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 843728039 ps |
| CPU time | 11.92 seconds |
| Started | Sep 18 09:22:39 PM UTC 24 |
| Finished | Sep 18 09:22:52 PM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924998556 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2924998556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.4213790231 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1368025119 ps |
| CPU time | 10.98 seconds |
| Started | Sep 18 09:22:40 PM UTC 24 |
| Finished | Sep 18 09:22:52 PM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213790231 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_to ken_digest.4213790231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.2779864542 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 232378151 ps |
| CPU time | 10.1 seconds |
| Started | Sep 18 09:22:39 PM UTC 24 |
| Finished | Sep 18 09:22:51 PM UTC 24 |
| Peak memory | 229680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779864542 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token _mux.2779864542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.1475111098 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 285870058 ps |
| CPU time | 8.3 seconds |
| Started | Sep 18 09:22:35 PM UTC 24 |
| Finished | Sep 18 09:22:45 PM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475111098 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1475111098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.4168806426 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 48669332 ps |
| CPU time | 4.33 seconds |
| Started | Sep 18 09:22:30 PM UTC 24 |
| Finished | Sep 18 09:22:35 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168806426 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.4168806426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.1113676541 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 225642279 ps |
| CPU time | 22.63 seconds |
| Started | Sep 18 09:22:33 PM UTC 24 |
| Finished | Sep 18 09:22:57 PM UTC 24 |
| Peak memory | 262284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113676541 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1113676541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.1340820291 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 94374095 ps |
| CPU time | 9.19 seconds |
| Started | Sep 18 09:22:34 PM UTC 24 |
| Finished | Sep 18 09:22:44 PM UTC 24 |
| Peak memory | 262196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340820291 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1340820291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.1035850297 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 303185490 ps |
| CPU time | 14.71 seconds |
| Started | Sep 18 09:22:41 PM UTC 24 |
| Finished | Sep 18 09:22:57 PM UTC 24 |
| Peak memory | 262332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1035850297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 12.lc_ctrl_stress_all.1035850297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.1428560470 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 24538124522 ps |
| CPU time | 151.81 seconds |
| Started | Sep 18 09:22:41 PM UTC 24 |
| Finished | Sep 18 09:25:15 PM UTC 24 |
| Peak memory | 407988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428560470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.1428560470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4254966246 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 24705196 ps |
| CPU time | 1.18 seconds |
| Started | Sep 18 09:22:32 PM UTC 24 |
| Finished | Sep 18 09:22:34 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254966246 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12 .lc_ctrl_volatile_unlock_smoke.4254966246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.2410591921 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 125880532 ps |
| CPU time | 1.55 seconds |
| Started | Sep 18 09:22:52 PM UTC 24 |
| Finished | Sep 18 09:22:54 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410591921 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2410591921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.1818122398 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1565655417 ps |
| CPU time | 14 seconds |
| Started | Sep 18 09:22:46 PM UTC 24 |
| Finished | Sep 18 09:23:01 PM UTC 24 |
| Peak memory | 229764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818122398 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1818122398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.4213506634 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 685948968 ps |
| CPU time | 4.91 seconds |
| Started | Sep 18 09:22:48 PM UTC 24 |
| Finished | Sep 18 09:22:54 PM UTC 24 |
| Peak memory | 228768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213506634 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.4213506634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.1058224644 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 8139785987 ps |
| CPU time | 37.02 seconds |
| Started | Sep 18 09:22:48 PM UTC 24 |
| Finished | Sep 18 09:23:26 PM UTC 24 |
| Peak memory | 231936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058224644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_j tag_errors.1058224644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.5866210 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 698081632 ps |
| CPU time | 4.47 seconds |
| Started | Sep 18 09:22:47 PM UTC 24 |
| Finished | Sep 18 09:22:52 PM UTC 24 |
| Peak memory | 235976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5866210 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_j tag_prog_failure.5866210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.3792330153 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3902163591 ps |
| CPU time | 11.94 seconds |
| Started | Sep 18 09:22:46 PM UTC 24 |
| Finished | Sep 18 09:23:00 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792330153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_ smoke.3792330153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.1255712991 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 6747935358 ps |
| CPU time | 38.81 seconds |
| Started | Sep 18 09:22:46 PM UTC 24 |
| Finished | Sep 18 09:23:27 PM UTC 24 |
| Peak memory | 262396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255712991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct rl_jtag_state_failure.1255712991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.3865968780 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2870662100 ps |
| CPU time | 12.69 seconds |
| Started | Sep 18 09:22:46 PM UTC 24 |
| Finished | Sep 18 09:23:00 PM UTC 24 |
| Peak memory | 260356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865968780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc _ctrl_jtag_state_post_trans.3865968780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.978120308 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 92859891 ps |
| CPU time | 5.86 seconds |
| Started | Sep 18 09:22:46 PM UTC 24 |
| Finished | Sep 18 09:22:53 PM UTC 24 |
| Peak memory | 235968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978120308 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.978120308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.3108020635 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1228874553 ps |
| CPU time | 11.44 seconds |
| Started | Sep 18 09:22:48 PM UTC 24 |
| Finished | Sep 18 09:23:01 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108020635 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3108020635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.2983767805 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 648975158 ps |
| CPU time | 20.79 seconds |
| Started | Sep 18 09:22:49 PM UTC 24 |
| Finished | Sep 18 09:23:11 PM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983767805 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_to ken_digest.2983767805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.3064413320 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1713502060 ps |
| CPU time | 11.28 seconds |
| Started | Sep 18 09:22:48 PM UTC 24 |
| Finished | Sep 18 09:23:00 PM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064413320 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token _mux.3064413320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.1581846567 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 494370442 ps |
| CPU time | 11.47 seconds |
| Started | Sep 18 09:22:46 PM UTC 24 |
| Finished | Sep 18 09:22:59 PM UTC 24 |
| Peak memory | 229104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581846567 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1581846567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.2491872980 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 39004901 ps |
| CPU time | 2.89 seconds |
| Started | Sep 18 09:22:44 PM UTC 24 |
| Finished | Sep 18 09:22:48 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491872980 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2491872980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.20364647 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 541079301 ps |
| CPU time | 24.37 seconds |
| Started | Sep 18 09:22:45 PM UTC 24 |
| Finished | Sep 18 09:23:10 PM UTC 24 |
| Peak memory | 260432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20364647 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.20364647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.2720594324 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 194128097 ps |
| CPU time | 11.15 seconds |
| Started | Sep 18 09:22:46 PM UTC 24 |
| Finished | Sep 18 09:22:58 PM UTC 24 |
| Peak memory | 260188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720594324 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2720594324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.4095862584 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 8233269157 ps |
| CPU time | 192.48 seconds |
| Started | Sep 18 09:22:49 PM UTC 24 |
| Finished | Sep 18 09:26:05 PM UTC 24 |
| Peak memory | 282884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4095862584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 13.lc_ctrl_stress_all.4095862584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2929943850 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 24475387 ps |
| CPU time | 1.11 seconds |
| Started | Sep 18 09:22:44 PM UTC 24 |
| Finished | Sep 18 09:22:47 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929943850 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13 .lc_ctrl_volatile_unlock_smoke.2929943850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.382043572 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 73713347 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 09:23:02 PM UTC 24 |
| Finished | Sep 18 09:23:04 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382043572 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.382043572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_errors.3809546070 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1270567920 ps |
| CPU time | 15.47 seconds |
| Started | Sep 18 09:22:54 PM UTC 24 |
| Finished | Sep 18 09:23:11 PM UTC 24 |
| Peak memory | 229840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809546070 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3809546070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.783951903 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 468536897 ps |
| CPU time | 4.44 seconds |
| Started | Sep 18 09:22:58 PM UTC 24 |
| Finished | Sep 18 09:23:04 PM UTC 24 |
| Peak memory | 228780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783951903 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.783951903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.1544550691 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 4677255362 ps |
| CPU time | 40.76 seconds |
| Started | Sep 18 09:22:58 PM UTC 24 |
| Finished | Sep 18 09:23:40 PM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544550691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_j tag_errors.1544550691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.686409409 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 331503922 ps |
| CPU time | 6.08 seconds |
| Started | Sep 18 09:22:58 PM UTC 24 |
| Finished | Sep 18 09:23:05 PM UTC 24 |
| Peak memory | 235820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686409409 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl _jtag_prog_failure.686409409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.478682710 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 110524082 ps |
| CPU time | 5.47 seconds |
| Started | Sep 18 09:22:57 PM UTC 24 |
| Finished | Sep 18 09:23:03 PM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478682710 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_s moke.478682710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.4062988729 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 5289796405 ps |
| CPU time | 77.09 seconds |
| Started | Sep 18 09:22:57 PM UTC 24 |
| Finished | Sep 18 09:24:16 PM UTC 24 |
| Peak memory | 285000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062988729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct rl_jtag_state_failure.4062988729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.2804705144 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 1094695668 ps |
| CPU time | 31.26 seconds |
| Started | Sep 18 09:22:57 PM UTC 24 |
| Finished | Sep 18 09:23:29 PM UTC 24 |
| Peak memory | 262276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804705144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc _ctrl_jtag_state_post_trans.2804705144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.302536940 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 64452740 ps |
| CPU time | 3.55 seconds |
| Started | Sep 18 09:22:54 PM UTC 24 |
| Finished | Sep 18 09:22:59 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302536940 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.302536940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.1088309337 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1383305976 ps |
| CPU time | 8.98 seconds |
| Started | Sep 18 09:23:00 PM UTC 24 |
| Finished | Sep 18 09:23:10 PM UTC 24 |
| Peak memory | 237424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088309337 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1088309337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.3679307836 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1571938264 ps |
| CPU time | 12.13 seconds |
| Started | Sep 18 09:23:00 PM UTC 24 |
| Finished | Sep 18 09:23:13 PM UTC 24 |
| Peak memory | 229680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679307836 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_to ken_digest.3679307836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.507980045 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 224639243 ps |
| CPU time | 6.03 seconds |
| Started | Sep 18 09:23:00 PM UTC 24 |
| Finished | Sep 18 09:23:07 PM UTC 24 |
| Peak memory | 237512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507980045 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_ mux.507980045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.3025018871 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 5758968521 ps |
| CPU time | 14.7 seconds |
| Started | Sep 18 09:22:56 PM UTC 24 |
| Finished | Sep 18 09:23:11 PM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025018871 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3025018871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.207233237 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 20398330 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 09:22:53 PM UTC 24 |
| Finished | Sep 18 09:22:56 PM UTC 24 |
| Peak memory | 222252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207233237 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.207233237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.3759984863 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1148190654 ps |
| CPU time | 26.34 seconds |
| Started | Sep 18 09:22:53 PM UTC 24 |
| Finished | Sep 18 09:23:21 PM UTC 24 |
| Peak memory | 260696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759984863 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3759984863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.1895716763 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 86294151 ps |
| CPU time | 8.16 seconds |
| Started | Sep 18 09:22:53 PM UTC 24 |
| Finished | Sep 18 09:23:03 PM UTC 24 |
| Peak memory | 260292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895716763 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1895716763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.1308398251 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 747221777 ps |
| CPU time | 33.96 seconds |
| Started | Sep 18 09:23:00 PM UTC 24 |
| Finished | Sep 18 09:23:35 PM UTC 24 |
| Peak memory | 262340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1308398251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 14.lc_ctrl_stress_all.1308398251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1754402517 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 258924921 ps |
| CPU time | 1.49 seconds |
| Started | Sep 18 09:22:53 PM UTC 24 |
| Finished | Sep 18 09:22:56 PM UTC 24 |
| Peak memory | 222240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754402517 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14 .lc_ctrl_volatile_unlock_smoke.1754402517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.210877646 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 32623881 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 09:23:09 PM UTC 24 |
| Finished | Sep 18 09:23:11 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210877646 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.210877646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.729625988 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 500434963 ps |
| CPU time | 12.42 seconds |
| Started | Sep 18 09:23:03 PM UTC 24 |
| Finished | Sep 18 09:23:17 PM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729625988 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.729625988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.3615344912 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1588586069 ps |
| CPU time | 13.12 seconds |
| Started | Sep 18 09:23:06 PM UTC 24 |
| Finished | Sep 18 09:23:20 PM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615344912 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3615344912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.2843464742 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 7669842772 ps |
| CPU time | 31.96 seconds |
| Started | Sep 18 09:23:05 PM UTC 24 |
| Finished | Sep 18 09:23:38 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843464742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_j tag_errors.2843464742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.748082826 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 146270273 ps |
| CPU time | 3.61 seconds |
| Started | Sep 18 09:23:05 PM UTC 24 |
| Finished | Sep 18 09:23:09 PM UTC 24 |
| Peak memory | 230004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748082826 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl _jtag_prog_failure.748082826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.1372305370 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 645232787 ps |
| CPU time | 10.44 seconds |
| Started | Sep 18 09:23:04 PM UTC 24 |
| Finished | Sep 18 09:23:15 PM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372305370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_ smoke.1372305370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.2250519006 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 3623793855 ps |
| CPU time | 30.55 seconds |
| Started | Sep 18 09:23:05 PM UTC 24 |
| Finished | Sep 18 09:23:36 PM UTC 24 |
| Peak memory | 262332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250519006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct rl_jtag_state_failure.2250519006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.587107120 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1070963441 ps |
| CPU time | 22.62 seconds |
| Started | Sep 18 09:23:05 PM UTC 24 |
| Finished | Sep 18 09:23:29 PM UTC 24 |
| Peak memory | 262216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587107120 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ ctrl_jtag_state_post_trans.587107120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.2166135683 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 78065079 ps |
| CPU time | 3.3 seconds |
| Started | Sep 18 09:23:02 PM UTC 24 |
| Finished | Sep 18 09:23:06 PM UTC 24 |
| Peak memory | 229824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166135683 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2166135683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.3313659923 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 317999930 ps |
| CPU time | 12.35 seconds |
| Started | Sep 18 09:23:06 PM UTC 24 |
| Finished | Sep 18 09:23:20 PM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313659923 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3313659923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.49922599 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1274643677 ps |
| CPU time | 12.27 seconds |
| Started | Sep 18 09:23:07 PM UTC 24 |
| Finished | Sep 18 09:23:21 PM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49922599 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_toke n_digest.49922599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.4011505454 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 972951213 ps |
| CPU time | 16.67 seconds |
| Started | Sep 18 09:23:06 PM UTC 24 |
| Finished | Sep 18 09:23:24 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011505454 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token _mux.4011505454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.4146849024 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 607951733 ps |
| CPU time | 21.1 seconds |
| Started | Sep 18 09:23:04 PM UTC 24 |
| Finished | Sep 18 09:23:26 PM UTC 24 |
| Peak memory | 229760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146849024 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.4146849024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.128835127 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 20846585 ps |
| CPU time | 1.94 seconds |
| Started | Sep 18 09:23:02 PM UTC 24 |
| Finished | Sep 18 09:23:05 PM UTC 24 |
| Peak memory | 222252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128835127 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.128835127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.2383398019 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 358107104 ps |
| CPU time | 23.61 seconds |
| Started | Sep 18 09:23:02 PM UTC 24 |
| Finished | Sep 18 09:23:27 PM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383398019 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2383398019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.2269756662 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 402852681 ps |
| CPU time | 7.09 seconds |
| Started | Sep 18 09:23:02 PM UTC 24 |
| Finished | Sep 18 09:23:10 PM UTC 24 |
| Peak memory | 262224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269756662 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2269756662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.759381019 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 4343733869 ps |
| CPU time | 113.2 seconds |
| Started | Sep 18 09:23:07 PM UTC 24 |
| Finished | Sep 18 09:25:03 PM UTC 24 |
| Peak memory | 295232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=759381019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 15.lc_ctrl_stress_all.759381019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.389957531 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 14106553 ps |
| CPU time | 1.06 seconds |
| Started | Sep 18 09:23:20 PM UTC 24 |
| Finished | Sep 18 09:23:22 PM UTC 24 |
| Peak memory | 218080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389957531 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.389957531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.1763669260 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 544449776 ps |
| CPU time | 8.36 seconds |
| Started | Sep 18 09:23:12 PM UTC 24 |
| Finished | Sep 18 09:23:22 PM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763669260 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1763669260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.58229793 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1099338056 ps |
| CPU time | 7.77 seconds |
| Started | Sep 18 09:23:14 PM UTC 24 |
| Finished | Sep 18 09:23:22 PM UTC 24 |
| Peak memory | 228932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58229793 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.58229793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.444627124 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 7665620570 ps |
| CPU time | 60.42 seconds |
| Started | Sep 18 09:23:14 PM UTC 24 |
| Finished | Sep 18 09:24:16 PM UTC 24 |
| Peak memory | 234244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444627124 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt ag_errors.444627124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.2470070515 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 6981976856 ps |
| CPU time | 13.62 seconds |
| Started | Sep 18 09:23:12 PM UTC 24 |
| Finished | Sep 18 09:23:27 PM UTC 24 |
| Peak memory | 230156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470070515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctr l_jtag_prog_failure.2470070515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.3733880325 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2697974637 ps |
| CPU time | 9 seconds |
| Started | Sep 18 09:23:12 PM UTC 24 |
| Finished | Sep 18 09:23:22 PM UTC 24 |
| Peak memory | 223456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733880325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_ smoke.3733880325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.2286570962 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 1492461861 ps |
| CPU time | 47.22 seconds |
| Started | Sep 18 09:23:12 PM UTC 24 |
| Finished | Sep 18 09:24:01 PM UTC 24 |
| Peak memory | 262272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286570962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct rl_jtag_state_failure.2286570962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.2349441449 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 349460267 ps |
| CPU time | 16.42 seconds |
| Started | Sep 18 09:23:12 PM UTC 24 |
| Finished | Sep 18 09:23:30 PM UTC 24 |
| Peak memory | 262312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349441449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc _ctrl_jtag_state_post_trans.2349441449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.1694234099 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 74101212 ps |
| CPU time | 4.82 seconds |
| Started | Sep 18 09:23:11 PM UTC 24 |
| Finished | Sep 18 09:23:16 PM UTC 24 |
| Peak memory | 233924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694234099 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1694234099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.269960573 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 405868001 ps |
| CPU time | 26.31 seconds |
| Started | Sep 18 09:23:14 PM UTC 24 |
| Finished | Sep 18 09:23:41 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269960573 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.269960573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.1755550508 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 645562228 ps |
| CPU time | 14.49 seconds |
| Started | Sep 18 09:23:16 PM UTC 24 |
| Finished | Sep 18 09:23:31 PM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755550508 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_to ken_digest.1755550508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.1879101372 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 4603310597 ps |
| CPU time | 14.18 seconds |
| Started | Sep 18 09:23:15 PM UTC 24 |
| Finished | Sep 18 09:23:30 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879101372 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token _mux.1879101372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.1249014568 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 326431474 ps |
| CPU time | 12.43 seconds |
| Started | Sep 18 09:23:12 PM UTC 24 |
| Finished | Sep 18 09:23:26 PM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249014568 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1249014568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.2513826557 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 48816688 ps |
| CPU time | 4.04 seconds |
| Started | Sep 18 09:23:09 PM UTC 24 |
| Finished | Sep 18 09:23:14 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513826557 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2513826557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.3087418740 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 1103793125 ps |
| CPU time | 30.89 seconds |
| Started | Sep 18 09:23:10 PM UTC 24 |
| Finished | Sep 18 09:23:43 PM UTC 24 |
| Peak memory | 260304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087418740 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3087418740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.640549381 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 536991012 ps |
| CPU time | 8.5 seconds |
| Started | Sep 18 09:23:11 PM UTC 24 |
| Finished | Sep 18 09:23:20 PM UTC 24 |
| Peak memory | 262308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640549381 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.640549381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.977767576 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 22283074060 ps |
| CPU time | 89.26 seconds |
| Started | Sep 18 09:23:17 PM UTC 24 |
| Finished | Sep 18 09:24:48 PM UTC 24 |
| Peak memory | 295324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=977767576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 16.lc_ctrl_stress_all.977767576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2722917410 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 41168293 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 09:23:10 PM UTC 24 |
| Finished | Sep 18 09:23:13 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722917410 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16 .lc_ctrl_volatile_unlock_smoke.2722917410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.731368460 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 28905915 ps |
| CPU time | 1.15 seconds |
| Started | Sep 18 09:23:27 PM UTC 24 |
| Finished | Sep 18 09:23:30 PM UTC 24 |
| Peak memory | 218076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731368460 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.731368460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.3345760921 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 175876521 ps |
| CPU time | 11.03 seconds |
| Started | Sep 18 09:23:23 PM UTC 24 |
| Finished | Sep 18 09:23:35 PM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345760921 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3345760921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.735191188 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 708820255 ps |
| CPU time | 11.08 seconds |
| Started | Sep 18 09:23:26 PM UTC 24 |
| Finished | Sep 18 09:23:38 PM UTC 24 |
| Peak memory | 228912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735191188 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.735191188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.1685266939 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 4613547153 ps |
| CPU time | 37.2 seconds |
| Started | Sep 18 09:23:25 PM UTC 24 |
| Finished | Sep 18 09:24:03 PM UTC 24 |
| Peak memory | 232148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685266939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_j tag_errors.1685266939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.4050946379 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 958460842 ps |
| CPU time | 9.36 seconds |
| Started | Sep 18 09:23:24 PM UTC 24 |
| Finished | Sep 18 09:23:35 PM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050946379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctr l_jtag_prog_failure.4050946379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.442074666 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 1595558847 ps |
| CPU time | 16.26 seconds |
| Started | Sep 18 09:23:23 PM UTC 24 |
| Finished | Sep 18 09:23:41 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442074666 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_s moke.442074666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.3282981528 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 7088583128 ps |
| CPU time | 72.2 seconds |
| Started | Sep 18 09:23:23 PM UTC 24 |
| Finished | Sep 18 09:24:37 PM UTC 24 |
| Peak memory | 282812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282981528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct rl_jtag_state_failure.3282981528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.571544147 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 613383385 ps |
| CPU time | 15.94 seconds |
| Started | Sep 18 09:23:23 PM UTC 24 |
| Finished | Sep 18 09:23:40 PM UTC 24 |
| Peak memory | 262272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571544147 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ ctrl_jtag_state_post_trans.571544147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.3145359707 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 44342452 ps |
| CPU time | 3.26 seconds |
| Started | Sep 18 09:23:22 PM UTC 24 |
| Finished | Sep 18 09:23:26 PM UTC 24 |
| Peak memory | 233920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145359707 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3145359707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.1133087989 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1094031451 ps |
| CPU time | 17.47 seconds |
| Started | Sep 18 09:23:27 PM UTC 24 |
| Finished | Sep 18 09:23:46 PM UTC 24 |
| Peak memory | 231792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133087989 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1133087989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.2781717317 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2465944355 ps |
| CPU time | 19.61 seconds |
| Started | Sep 18 09:23:27 PM UTC 24 |
| Finished | Sep 18 09:23:48 PM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781717317 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_to ken_digest.2781717317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.1049537648 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 443942217 ps |
| CPU time | 10.37 seconds |
| Started | Sep 18 09:23:27 PM UTC 24 |
| Finished | Sep 18 09:23:39 PM UTC 24 |
| Peak memory | 229764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049537648 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token _mux.1049537648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.3532508912 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 768535451 ps |
| CPU time | 17.15 seconds |
| Started | Sep 18 09:23:23 PM UTC 24 |
| Finished | Sep 18 09:23:41 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532508912 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3532508912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.2121307631 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 105932908 ps |
| CPU time | 4.06 seconds |
| Started | Sep 18 09:23:22 PM UTC 24 |
| Finished | Sep 18 09:23:27 PM UTC 24 |
| Peak memory | 229568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121307631 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2121307631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.963647191 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 831891329 ps |
| CPU time | 27.65 seconds |
| Started | Sep 18 09:23:22 PM UTC 24 |
| Finished | Sep 18 09:23:51 PM UTC 24 |
| Peak memory | 262268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963647191 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.963647191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.541254268 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 220984230 ps |
| CPU time | 3.1 seconds |
| Started | Sep 18 09:23:22 PM UTC 24 |
| Finished | Sep 18 09:23:26 PM UTC 24 |
| Peak memory | 234260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541254268 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.541254268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.1426592355 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 6995377574 ps |
| CPU time | 204.12 seconds |
| Started | Sep 18 09:23:27 PM UTC 24 |
| Finished | Sep 18 09:26:54 PM UTC 24 |
| Peak memory | 432848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1426592355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 17.lc_ctrl_stress_all.1426592355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.319865845 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 97977054 ps |
| CPU time | 1.13 seconds |
| Started | Sep 18 09:23:22 PM UTC 24 |
| Finished | Sep 18 09:23:24 PM UTC 24 |
| Peak memory | 222240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319865845 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17. lc_ctrl_volatile_unlock_smoke.319865845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.1323662637 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 20730822 ps |
| CPU time | 1.45 seconds |
| Started | Sep 18 09:23:39 PM UTC 24 |
| Finished | Sep 18 09:23:41 PM UTC 24 |
| Peak memory | 218204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323662637 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1323662637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.261699058 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 2672976385 ps |
| CPU time | 12.01 seconds |
| Started | Sep 18 09:23:30 PM UTC 24 |
| Finished | Sep 18 09:23:43 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261699058 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.261699058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.3157134724 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 528390570 ps |
| CPU time | 3.85 seconds |
| Started | Sep 18 09:23:36 PM UTC 24 |
| Finished | Sep 18 09:23:41 PM UTC 24 |
| Peak memory | 228704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157134724 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3157134724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.787043194 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 4210802913 ps |
| CPU time | 30.85 seconds |
| Started | Sep 18 09:23:33 PM UTC 24 |
| Finished | Sep 18 09:24:05 PM UTC 24 |
| Peak memory | 230148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787043194 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt ag_errors.787043194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.838342180 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 870737228 ps |
| CPU time | 14.7 seconds |
| Started | Sep 18 09:23:33 PM UTC 24 |
| Finished | Sep 18 09:23:48 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838342180 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl _jtag_prog_failure.838342180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.2678878739 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 130748141 ps |
| CPU time | 3.12 seconds |
| Started | Sep 18 09:23:31 PM UTC 24 |
| Finished | Sep 18 09:23:36 PM UTC 24 |
| Peak memory | 223396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678878739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_ smoke.2678878739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.596621856 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 5971368516 ps |
| CPU time | 47.52 seconds |
| Started | Sep 18 09:23:31 PM UTC 24 |
| Finished | Sep 18 09:24:20 PM UTC 24 |
| Peak memory | 284932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596621856 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctr l_jtag_state_failure.596621856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.562007891 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 935946424 ps |
| CPU time | 30.05 seconds |
| Started | Sep 18 09:23:32 PM UTC 24 |
| Finished | Sep 18 09:24:03 PM UTC 24 |
| Peak memory | 262684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562007891 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ ctrl_jtag_state_post_trans.562007891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.651223796 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 311903514 ps |
| CPU time | 5.38 seconds |
| Started | Sep 18 09:23:30 PM UTC 24 |
| Finished | Sep 18 09:23:36 PM UTC 24 |
| Peak memory | 233532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651223796 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.651223796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.2559002924 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1492799372 ps |
| CPU time | 28.88 seconds |
| Started | Sep 18 09:23:36 PM UTC 24 |
| Finished | Sep 18 09:24:06 PM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559002924 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2559002924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.2525322383 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 387794893 ps |
| CPU time | 12.77 seconds |
| Started | Sep 18 09:23:36 PM UTC 24 |
| Finished | Sep 18 09:23:50 PM UTC 24 |
| Peak memory | 230072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525322383 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_to ken_digest.2525322383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.2663358936 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 179752391 ps |
| CPU time | 5.89 seconds |
| Started | Sep 18 09:23:36 PM UTC 24 |
| Finished | Sep 18 09:23:43 PM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663358936 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token _mux.2663358936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.1261569758 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 593772004 ps |
| CPU time | 8.43 seconds |
| Started | Sep 18 09:23:31 PM UTC 24 |
| Finished | Sep 18 09:23:41 PM UTC 24 |
| Peak memory | 229768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261569758 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1261569758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.3161037479 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 40236152 ps |
| CPU time | 2.43 seconds |
| Started | Sep 18 09:23:29 PM UTC 24 |
| Finished | Sep 18 09:23:32 PM UTC 24 |
| Peak memory | 229724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161037479 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3161037479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.2418527644 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 229027925 ps |
| CPU time | 36.89 seconds |
| Started | Sep 18 09:23:29 PM UTC 24 |
| Finished | Sep 18 09:24:07 PM UTC 24 |
| Peak memory | 262424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418527644 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2418527644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.2694880914 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 198956489 ps |
| CPU time | 10.86 seconds |
| Started | Sep 18 09:23:30 PM UTC 24 |
| Finished | Sep 18 09:23:42 PM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694880914 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2694880914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.936346682 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 779742237 ps |
| CPU time | 28.68 seconds |
| Started | Sep 18 09:23:37 PM UTC 24 |
| Finished | Sep 18 09:24:08 PM UTC 24 |
| Peak memory | 237360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=936346682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 18.lc_ctrl_stress_all.936346682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1525939477 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 25969922 ps |
| CPU time | 1.15 seconds |
| Started | Sep 18 09:23:29 PM UTC 24 |
| Finished | Sep 18 09:23:31 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525939477 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18 .lc_ctrl_volatile_unlock_smoke.1525939477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.792528245 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 40277942 ps |
| CPU time | 1.76 seconds |
| Started | Sep 18 09:23:47 PM UTC 24 |
| Finished | Sep 18 09:23:50 PM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792528245 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.792528245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.4051457102 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 655839512 ps |
| CPU time | 19.36 seconds |
| Started | Sep 18 09:23:42 PM UTC 24 |
| Finished | Sep 18 09:24:02 PM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051457102 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.4051457102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.2485776334 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1220173670 ps |
| CPU time | 5.79 seconds |
| Started | Sep 18 09:23:43 PM UTC 24 |
| Finished | Sep 18 09:23:51 PM UTC 24 |
| Peak memory | 229456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485776334 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2485776334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.2434634970 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1423489348 ps |
| CPU time | 42.9 seconds |
| Started | Sep 18 09:23:43 PM UTC 24 |
| Finished | Sep 18 09:24:28 PM UTC 24 |
| Peak memory | 229724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434634970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_j tag_errors.2434634970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.4178839629 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 471309788 ps |
| CPU time | 17.9 seconds |
| Started | Sep 18 09:23:43 PM UTC 24 |
| Finished | Sep 18 09:24:03 PM UTC 24 |
| Peak memory | 235816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178839629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctr l_jtag_prog_failure.4178839629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.3598589761 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 231315195 ps |
| CPU time | 4.82 seconds |
| Started | Sep 18 09:23:42 PM UTC 24 |
| Finished | Sep 18 09:23:48 PM UTC 24 |
| Peak memory | 223332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598589761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_ smoke.3598589761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.1536968332 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 2911053215 ps |
| CPU time | 60.65 seconds |
| Started | Sep 18 09:23:43 PM UTC 24 |
| Finished | Sep 18 09:24:46 PM UTC 24 |
| Peak memory | 283212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536968332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct rl_jtag_state_failure.1536968332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.125514469 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1156707956 ps |
| CPU time | 9.91 seconds |
| Started | Sep 18 09:23:43 PM UTC 24 |
| Finished | Sep 18 09:23:55 PM UTC 24 |
| Peak memory | 236268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125514469 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ ctrl_jtag_state_post_trans.125514469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.1253826575 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 109582073 ps |
| CPU time | 2.63 seconds |
| Started | Sep 18 09:23:41 PM UTC 24 |
| Finished | Sep 18 09:23:45 PM UTC 24 |
| Peak memory | 233920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253826575 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1253826575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.4207703318 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 669298109 ps |
| CPU time | 16.33 seconds |
| Started | Sep 18 09:23:44 PM UTC 24 |
| Finished | Sep 18 09:24:03 PM UTC 24 |
| Peak memory | 230996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207703318 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.4207703318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.32283321 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 351117789 ps |
| CPU time | 12.84 seconds |
| Started | Sep 18 09:23:45 PM UTC 24 |
| Finished | Sep 18 09:23:59 PM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32283321 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_toke n_digest.32283321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.2853055789 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 600227165 ps |
| CPU time | 8.53 seconds |
| Started | Sep 18 09:23:45 PM UTC 24 |
| Finished | Sep 18 09:23:55 PM UTC 24 |
| Peak memory | 228976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853055789 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token _mux.2853055789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.999459314 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 406526360 ps |
| CPU time | 12.61 seconds |
| Started | Sep 18 09:23:42 PM UTC 24 |
| Finished | Sep 18 09:23:56 PM UTC 24 |
| Peak memory | 229828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999459314 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.999459314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.847249426 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 92970934 ps |
| CPU time | 6.25 seconds |
| Started | Sep 18 09:23:39 PM UTC 24 |
| Finished | Sep 18 09:23:46 PM UTC 24 |
| Peak memory | 229636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847249426 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.847249426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.2113974265 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2927029943 ps |
| CPU time | 27.41 seconds |
| Started | Sep 18 09:23:40 PM UTC 24 |
| Finished | Sep 18 09:24:09 PM UTC 24 |
| Peak memory | 262532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113974265 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2113974265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.3215340258 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 82881750 ps |
| CPU time | 8.48 seconds |
| Started | Sep 18 09:23:41 PM UTC 24 |
| Finished | Sep 18 09:23:51 PM UTC 24 |
| Peak memory | 262328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215340258 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3215340258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.2845267771 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1197267511 ps |
| CPU time | 50.9 seconds |
| Started | Sep 18 09:23:47 PM UTC 24 |
| Finished | Sep 18 09:24:40 PM UTC 24 |
| Peak memory | 262520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2845267771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 19.lc_ctrl_stress_all.2845267771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.990367039 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 139385759 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 09:23:40 PM UTC 24 |
| Finished | Sep 18 09:23:42 PM UTC 24 |
| Peak memory | 217236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990367039 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19. lc_ctrl_volatile_unlock_smoke.990367039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.1278689497 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 22269003 ps |
| CPU time | 1.5 seconds |
| Started | Sep 18 09:20:17 PM UTC 24 |
| Finished | Sep 18 09:20:20 PM UTC 24 |
| Peak memory | 218268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278689497 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1278689497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1791093888 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 346860629 ps |
| CPU time | 13.73 seconds |
| Started | Sep 18 09:20:00 PM UTC 24 |
| Finished | Sep 18 09:20:15 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791093888 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1791093888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2221084673 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1795335303 ps |
| CPU time | 27.18 seconds |
| Started | Sep 18 09:20:06 PM UTC 24 |
| Finished | Sep 18 09:20:35 PM UTC 24 |
| Peak memory | 228988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221084673 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2221084673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.3408509816 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 2204714527 ps |
| CPU time | 67.06 seconds |
| Started | Sep 18 09:20:05 PM UTC 24 |
| Finished | Sep 18 09:21:14 PM UTC 24 |
| Peak memory | 231860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408509816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jt ag_errors.3408509816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.3549774727 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 367328863 ps |
| CPU time | 10.53 seconds |
| Started | Sep 18 09:20:07 PM UTC 24 |
| Finished | Sep 18 09:20:19 PM UTC 24 |
| Peak memory | 229340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549774727 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_prior ity.3549774727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.4180571415 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 206120322 ps |
| CPU time | 3.61 seconds |
| Started | Sep 18 09:20:05 PM UTC 24 |
| Finished | Sep 18 09:20:09 PM UTC 24 |
| Peak memory | 233768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180571415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl _jtag_prog_failure.4180571415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3141242078 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1003340891 ps |
| CPU time | 33.61 seconds |
| Started | Sep 18 09:20:07 PM UTC 24 |
| Finished | Sep 18 09:20:42 PM UTC 24 |
| Peak memory | 223324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141242078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ ctrl_jtag_regwen_during_op.3141242078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.631685771 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1738941676 ps |
| CPU time | 11.35 seconds |
| Started | Sep 18 09:20:04 PM UTC 24 |
| Finished | Sep 18 09:20:16 PM UTC 24 |
| Peak memory | 223324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631685771 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_sm oke.631685771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1158806779 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 5761523706 ps |
| CPU time | 15.53 seconds |
| Started | Sep 18 09:20:05 PM UTC 24 |
| Finished | Sep 18 09:20:22 PM UTC 24 |
| Peak memory | 262508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158806779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ ctrl_jtag_state_post_trans.1158806779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.740234361 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 224713781 ps |
| CPU time | 2.63 seconds |
| Started | Sep 18 09:19:59 PM UTC 24 |
| Finished | Sep 18 09:20:03 PM UTC 24 |
| Peak memory | 233924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740234361 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.740234361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.2760788067 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 273141374 ps |
| CPU time | 23.2 seconds |
| Started | Sep 18 09:20:01 PM UTC 24 |
| Finished | Sep 18 09:20:26 PM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760788067 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2760788067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.3598996317 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 144854629 ps |
| CPU time | 25.69 seconds |
| Started | Sep 18 09:20:17 PM UTC 24 |
| Finished | Sep 18 09:20:44 PM UTC 24 |
| Peak memory | 295872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598996317 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3598996317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.3043129787 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 475178617 ps |
| CPU time | 10.46 seconds |
| Started | Sep 18 09:20:10 PM UTC 24 |
| Finished | Sep 18 09:20:21 PM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043129787 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.3043129787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.2937738076 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 269205816 ps |
| CPU time | 10.3 seconds |
| Started | Sep 18 09:20:16 PM UTC 24 |
| Finished | Sep 18 09:20:27 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937738076 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_tok en_digest.2937738076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.1469483104 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 307237379 ps |
| CPU time | 11.08 seconds |
| Started | Sep 18 09:20:11 PM UTC 24 |
| Finished | Sep 18 09:20:23 PM UTC 24 |
| Peak memory | 229828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469483104 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_ mux.1469483104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1265323572 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 60945121 ps |
| CPU time | 4.01 seconds |
| Started | Sep 18 09:19:57 PM UTC 24 |
| Finished | Sep 18 09:20:02 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265323572 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1265323572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.4264847149 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 312816506 ps |
| CPU time | 32.81 seconds |
| Started | Sep 18 09:19:58 PM UTC 24 |
| Finished | Sep 18 09:20:32 PM UTC 24 |
| Peak memory | 260372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264847149 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.4264847149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.2132812907 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 141589665 ps |
| CPU time | 5.22 seconds |
| Started | Sep 18 09:19:58 PM UTC 24 |
| Finished | Sep 18 09:20:04 PM UTC 24 |
| Peak memory | 234256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132812907 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2132812907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.2630653900 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 3231184836 ps |
| CPU time | 114.29 seconds |
| Started | Sep 18 09:20:16 PM UTC 24 |
| Finished | Sep 18 09:22:13 PM UTC 24 |
| Peak memory | 258700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2630653900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 2.lc_ctrl_stress_all.2630653900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.448471932 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 108498769 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 09:19:58 PM UTC 24 |
| Finished | Sep 18 09:20:00 PM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448471932 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.l c_ctrl_volatile_unlock_smoke.448471932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.2133530933 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 84483441 ps |
| CPU time | 1.35 seconds |
| Started | Sep 18 09:23:57 PM UTC 24 |
| Finished | Sep 18 09:23:59 PM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133530933 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2133530933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.907185196 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 375960660 ps |
| CPU time | 14.92 seconds |
| Started | Sep 18 09:23:51 PM UTC 24 |
| Finished | Sep 18 09:24:07 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907185196 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.907185196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.3776095774 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 3704947377 ps |
| CPU time | 3.93 seconds |
| Started | Sep 18 09:23:52 PM UTC 24 |
| Finished | Sep 18 09:23:57 PM UTC 24 |
| Peak memory | 229244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776095774 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3776095774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.3991352702 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 84515951 ps |
| CPU time | 2.1 seconds |
| Started | Sep 18 09:23:51 PM UTC 24 |
| Finished | Sep 18 09:23:54 PM UTC 24 |
| Peak memory | 233848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991352702 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3991352702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.2717573162 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 205423506 ps |
| CPU time | 12.19 seconds |
| Started | Sep 18 09:23:52 PM UTC 24 |
| Finished | Sep 18 09:24:05 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717573162 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2717573162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.3592482553 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 264377445 ps |
| CPU time | 11.58 seconds |
| Started | Sep 18 09:23:54 PM UTC 24 |
| Finished | Sep 18 09:24:07 PM UTC 24 |
| Peak memory | 237424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592482553 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_to ken_digest.3592482553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.819581359 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 293379671 ps |
| CPU time | 12.53 seconds |
| Started | Sep 18 09:23:52 PM UTC 24 |
| Finished | Sep 18 09:24:06 PM UTC 24 |
| Peak memory | 237428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819581359 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_ mux.819581359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1257641769 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 571737252 ps |
| CPU time | 14.4 seconds |
| Started | Sep 18 09:23:52 PM UTC 24 |
| Finished | Sep 18 09:24:08 PM UTC 24 |
| Peak memory | 229700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257641769 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1257641769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.671958903 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 123192818 ps |
| CPU time | 5.97 seconds |
| Started | Sep 18 09:23:48 PM UTC 24 |
| Finished | Sep 18 09:23:55 PM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671958903 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.671958903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.2405295703 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 598474646 ps |
| CPU time | 15.17 seconds |
| Started | Sep 18 09:23:49 PM UTC 24 |
| Finished | Sep 18 09:24:06 PM UTC 24 |
| Peak memory | 260376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405295703 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2405295703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.645611480 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 508967027 ps |
| CPU time | 9.74 seconds |
| Started | Sep 18 09:23:50 PM UTC 24 |
| Finished | Sep 18 09:24:00 PM UTC 24 |
| Peak memory | 262276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645611480 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.645611480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.3043790870 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 21149125243 ps |
| CPU time | 130.51 seconds |
| Started | Sep 18 09:23:55 PM UTC 24 |
| Finished | Sep 18 09:26:09 PM UTC 24 |
| Peak memory | 234116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3043790870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 20.lc_ctrl_stress_all.3043790870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2213535614 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 19861308 ps |
| CPU time | 1.56 seconds |
| Started | Sep 18 09:23:48 PM UTC 24 |
| Finished | Sep 18 09:23:51 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213535614 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20 .lc_ctrl_volatile_unlock_smoke.2213535614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.3515938624 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 16982922 ps |
| CPU time | 1.3 seconds |
| Started | Sep 18 09:24:04 PM UTC 24 |
| Finished | Sep 18 09:24:07 PM UTC 24 |
| Peak memory | 217804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515938624 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3515938624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.1194093733 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 252766336 ps |
| CPU time | 9.75 seconds |
| Started | Sep 18 09:24:01 PM UTC 24 |
| Finished | Sep 18 09:24:12 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194093733 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1194093733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.3127900218 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 803589657 ps |
| CPU time | 22.73 seconds |
| Started | Sep 18 09:24:02 PM UTC 24 |
| Finished | Sep 18 09:24:26 PM UTC 24 |
| Peak memory | 228824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127900218 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3127900218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.1098158823 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 26670321 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 09:24:00 PM UTC 24 |
| Finished | Sep 18 09:24:03 PM UTC 24 |
| Peak memory | 231904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098158823 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1098158823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.3060570051 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 522270352 ps |
| CPU time | 22.48 seconds |
| Started | Sep 18 09:24:03 PM UTC 24 |
| Finished | Sep 18 09:24:27 PM UTC 24 |
| Peak memory | 231796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060570051 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3060570051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.3742470138 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 285331885 ps |
| CPU time | 12.35 seconds |
| Started | Sep 18 09:24:04 PM UTC 24 |
| Finished | Sep 18 09:24:18 PM UTC 24 |
| Peak memory | 229996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742470138 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_to ken_digest.3742470138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.719052052 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 715482487 ps |
| CPU time | 5.35 seconds |
| Started | Sep 18 09:24:03 PM UTC 24 |
| Finished | Sep 18 09:24:09 PM UTC 24 |
| Peak memory | 229892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719052052 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_ mux.719052052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.2646103343 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1537476857 ps |
| CPU time | 9.61 seconds |
| Started | Sep 18 09:24:01 PM UTC 24 |
| Finished | Sep 18 09:24:12 PM UTC 24 |
| Peak memory | 230004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646103343 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2646103343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.2906728417 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 156406191 ps |
| CPU time | 3.72 seconds |
| Started | Sep 18 09:23:57 PM UTC 24 |
| Finished | Sep 18 09:24:01 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906728417 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2906728417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.1177852909 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 941343743 ps |
| CPU time | 22.26 seconds |
| Started | Sep 18 09:23:59 PM UTC 24 |
| Finished | Sep 18 09:24:23 PM UTC 24 |
| Peak memory | 262424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177852909 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1177852909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.1889883040 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 742868244 ps |
| CPU time | 8.3 seconds |
| Started | Sep 18 09:24:00 PM UTC 24 |
| Finished | Sep 18 09:24:10 PM UTC 24 |
| Peak memory | 262624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889883040 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1889883040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.1373494916 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 4154212031 ps |
| CPU time | 116.68 seconds |
| Started | Sep 18 09:24:04 PM UTC 24 |
| Finished | Sep 18 09:26:03 PM UTC 24 |
| Peak memory | 430400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1373494916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 21.lc_ctrl_stress_all.1373494916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1218366477 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 33740097 ps |
| CPU time | 1.44 seconds |
| Started | Sep 18 09:23:58 PM UTC 24 |
| Finished | Sep 18 09:24:00 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218366477 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21 .lc_ctrl_volatile_unlock_smoke.1218366477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.954200326 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 31657694 ps |
| CPU time | 1.3 seconds |
| Started | Sep 18 09:24:09 PM UTC 24 |
| Finished | Sep 18 09:24:11 PM UTC 24 |
| Peak memory | 217776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954200326 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.954200326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.149398226 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 558844604 ps |
| CPU time | 29.74 seconds |
| Started | Sep 18 09:24:07 PM UTC 24 |
| Finished | Sep 18 09:24:38 PM UTC 24 |
| Peak memory | 229828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149398226 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.149398226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.1936291453 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 339668685 ps |
| CPU time | 10.35 seconds |
| Started | Sep 18 09:24:09 PM UTC 24 |
| Finished | Sep 18 09:24:20 PM UTC 24 |
| Peak memory | 228908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936291453 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1936291453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.2550545765 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 228677522 ps |
| CPU time | 3.54 seconds |
| Started | Sep 18 09:24:07 PM UTC 24 |
| Finished | Sep 18 09:24:12 PM UTC 24 |
| Peak memory | 230016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550545765 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2550545765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.442165772 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2236793013 ps |
| CPU time | 20.66 seconds |
| Started | Sep 18 09:24:09 PM UTC 24 |
| Finished | Sep 18 09:24:31 PM UTC 24 |
| Peak memory | 232264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442165772 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.442165772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.4239936339 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1382402539 ps |
| CPU time | 12.08 seconds |
| Started | Sep 18 09:24:09 PM UTC 24 |
| Finished | Sep 18 09:24:22 PM UTC 24 |
| Peak memory | 229680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239936339 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_to ken_digest.4239936339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.327237890 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 427626007 ps |
| CPU time | 10.26 seconds |
| Started | Sep 18 09:24:09 PM UTC 24 |
| Finished | Sep 18 09:24:20 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327237890 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_ mux.327237890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.3972561794 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 316569837 ps |
| CPU time | 7.92 seconds |
| Started | Sep 18 09:24:09 PM UTC 24 |
| Finished | Sep 18 09:24:18 PM UTC 24 |
| Peak memory | 230160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972561794 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3972561794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.2628812339 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 78218830 ps |
| CPU time | 1.57 seconds |
| Started | Sep 18 09:24:04 PM UTC 24 |
| Finished | Sep 18 09:24:07 PM UTC 24 |
| Peak memory | 228152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628812339 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2628812339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.2420744873 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1635862373 ps |
| CPU time | 25.62 seconds |
| Started | Sep 18 09:24:06 PM UTC 24 |
| Finished | Sep 18 09:24:33 PM UTC 24 |
| Peak memory | 262488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420744873 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2420744873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.3451889577 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 146860720 ps |
| CPU time | 8.81 seconds |
| Started | Sep 18 09:24:07 PM UTC 24 |
| Finished | Sep 18 09:24:17 PM UTC 24 |
| Peak memory | 260504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451889577 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3451889577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.3411735210 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 55089962062 ps |
| CPU time | 131.14 seconds |
| Started | Sep 18 09:24:09 PM UTC 24 |
| Finished | Sep 18 09:26:22 PM UTC 24 |
| Peak memory | 293260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3411735210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 22.lc_ctrl_stress_all.3411735210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.4223200296 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 4511721429 ps |
| CPU time | 61.96 seconds |
| Started | Sep 18 09:24:09 PM UTC 24 |
| Finished | Sep 18 09:25:12 PM UTC 24 |
| Peak memory | 272772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223200296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.4223200296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.404747884 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 32840499 ps |
| CPU time | 1.19 seconds |
| Started | Sep 18 09:24:04 PM UTC 24 |
| Finished | Sep 18 09:24:07 PM UTC 24 |
| Peak memory | 218204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404747884 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22. lc_ctrl_volatile_unlock_smoke.404747884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.2676539620 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 16092220 ps |
| CPU time | 1.04 seconds |
| Started | Sep 18 09:24:16 PM UTC 24 |
| Finished | Sep 18 09:24:18 PM UTC 24 |
| Peak memory | 218200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676539620 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2676539620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.3593901435 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 225302615 ps |
| CPU time | 13.04 seconds |
| Started | Sep 18 09:24:12 PM UTC 24 |
| Finished | Sep 18 09:24:27 PM UTC 24 |
| Peak memory | 229844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593901435 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3593901435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.2751032294 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1186034076 ps |
| CPU time | 9.61 seconds |
| Started | Sep 18 09:24:14 PM UTC 24 |
| Finished | Sep 18 09:24:24 PM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751032294 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2751032294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.629091049 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 20923741 ps |
| CPU time | 2.39 seconds |
| Started | Sep 18 09:24:11 PM UTC 24 |
| Finished | Sep 18 09:24:15 PM UTC 24 |
| Peak memory | 234256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629091049 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.629091049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.1349585490 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 836843499 ps |
| CPU time | 16.28 seconds |
| Started | Sep 18 09:24:14 PM UTC 24 |
| Finished | Sep 18 09:24:31 PM UTC 24 |
| Peak memory | 231728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349585490 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1349585490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.2012500574 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2382519217 ps |
| CPU time | 16.45 seconds |
| Started | Sep 18 09:24:15 PM UTC 24 |
| Finished | Sep 18 09:24:33 PM UTC 24 |
| Peak memory | 237880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012500574 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_to ken_digest.2012500574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.3576684930 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2688987946 ps |
| CPU time | 13.25 seconds |
| Started | Sep 18 09:24:14 PM UTC 24 |
| Finished | Sep 18 09:24:28 PM UTC 24 |
| Peak memory | 230012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576684930 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token _mux.3576684930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.231662373 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 4263132119 ps |
| CPU time | 10.36 seconds |
| Started | Sep 18 09:24:12 PM UTC 24 |
| Finished | Sep 18 09:24:24 PM UTC 24 |
| Peak memory | 229956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231662373 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.231662373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.724607316 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 242422962 ps |
| CPU time | 4.04 seconds |
| Started | Sep 18 09:24:09 PM UTC 24 |
| Finished | Sep 18 09:24:14 PM UTC 24 |
| Peak memory | 225612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724607316 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.724607316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.2248328629 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1019661995 ps |
| CPU time | 31.51 seconds |
| Started | Sep 18 09:24:10 PM UTC 24 |
| Finished | Sep 18 09:24:43 PM UTC 24 |
| Peak memory | 262456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248328629 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2248328629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.3950256745 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 74293402 ps |
| CPU time | 7.24 seconds |
| Started | Sep 18 09:24:10 PM UTC 24 |
| Finished | Sep 18 09:24:19 PM UTC 24 |
| Peak memory | 262344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950256745 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3950256745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.289987592 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 8249528871 ps |
| CPU time | 70.64 seconds |
| Started | Sep 18 09:24:16 PM UTC 24 |
| Finished | Sep 18 09:25:29 PM UTC 24 |
| Peak memory | 272812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=289987592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 23.lc_ctrl_stress_all.289987592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2251082957 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 8406318834 ps |
| CPU time | 56.35 seconds |
| Started | Sep 18 09:24:16 PM UTC 24 |
| Finished | Sep 18 09:25:14 PM UTC 24 |
| Peak memory | 262936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251082957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.2251082957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1719357811 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 16028734 ps |
| CPU time | 1.5 seconds |
| Started | Sep 18 09:24:10 PM UTC 24 |
| Finished | Sep 18 09:24:13 PM UTC 24 |
| Peak memory | 222240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719357811 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23 .lc_ctrl_volatile_unlock_smoke.1719357811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.4233298333 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 53034497 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 09:24:25 PM UTC 24 |
| Finished | Sep 18 09:24:28 PM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233298333 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.4233298333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.2711919381 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 999585981 ps |
| CPU time | 12.49 seconds |
| Started | Sep 18 09:24:21 PM UTC 24 |
| Finished | Sep 18 09:24:35 PM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711919381 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2711919381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.60599095 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1132788561 ps |
| CPU time | 9.96 seconds |
| Started | Sep 18 09:24:22 PM UTC 24 |
| Finished | Sep 18 09:24:33 PM UTC 24 |
| Peak memory | 229208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60599095 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.60599095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.1504861155 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 74226067 ps |
| CPU time | 3.82 seconds |
| Started | Sep 18 09:24:20 PM UTC 24 |
| Finished | Sep 18 09:24:25 PM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504861155 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1504861155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.2508360263 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 379157458 ps |
| CPU time | 12.08 seconds |
| Started | Sep 18 09:24:22 PM UTC 24 |
| Finished | Sep 18 09:24:35 PM UTC 24 |
| Peak memory | 237576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508360263 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2508360263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.4054380091 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 293938620 ps |
| CPU time | 10.65 seconds |
| Started | Sep 18 09:24:23 PM UTC 24 |
| Finished | Sep 18 09:24:35 PM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054380091 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_to ken_digest.4054380091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.854503441 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 432493065 ps |
| CPU time | 10.57 seconds |
| Started | Sep 18 09:24:22 PM UTC 24 |
| Finished | Sep 18 09:24:33 PM UTC 24 |
| Peak memory | 237224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854503441 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_ mux.854503441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.2661289225 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 325497002 ps |
| CPU time | 14.26 seconds |
| Started | Sep 18 09:24:22 PM UTC 24 |
| Finished | Sep 18 09:24:37 PM UTC 24 |
| Peak memory | 237516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661289225 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2661289225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.3561074067 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 84063559 ps |
| CPU time | 3.01 seconds |
| Started | Sep 18 09:24:17 PM UTC 24 |
| Finished | Sep 18 09:24:21 PM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561074067 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3561074067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.3292738277 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 515150172 ps |
| CPU time | 29.21 seconds |
| Started | Sep 18 09:24:19 PM UTC 24 |
| Finished | Sep 18 09:24:49 PM UTC 24 |
| Peak memory | 258584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292738277 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3292738277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.3652833564 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 545438957 ps |
| CPU time | 5.93 seconds |
| Started | Sep 18 09:24:19 PM UTC 24 |
| Finished | Sep 18 09:24:26 PM UTC 24 |
| Peak memory | 262340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652833564 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3652833564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.367657383 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 22140190483 ps |
| CPU time | 271.93 seconds |
| Started | Sep 18 09:24:23 PM UTC 24 |
| Finished | Sep 18 09:28:59 PM UTC 24 |
| Peak memory | 295596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=367657383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 24.lc_ctrl_stress_all.367657383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2682987832 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 43735495 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 09:24:19 PM UTC 24 |
| Finished | Sep 18 09:24:21 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682987832 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24 .lc_ctrl_volatile_unlock_smoke.2682987832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.482145806 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 29090609 ps |
| CPU time | 1.3 seconds |
| Started | Sep 18 09:24:32 PM UTC 24 |
| Finished | Sep 18 09:24:34 PM UTC 24 |
| Peak memory | 218080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482145806 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.482145806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.1329092535 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 1700059598 ps |
| CPU time | 15.1 seconds |
| Started | Sep 18 09:24:28 PM UTC 24 |
| Finished | Sep 18 09:24:44 PM UTC 24 |
| Peak memory | 229764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329092535 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1329092535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.4115360202 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1008779410 ps |
| CPU time | 5.78 seconds |
| Started | Sep 18 09:24:29 PM UTC 24 |
| Finished | Sep 18 09:24:36 PM UTC 24 |
| Peak memory | 228924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115360202 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.4115360202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.3223994710 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 593163041 ps |
| CPU time | 4.51 seconds |
| Started | Sep 18 09:24:28 PM UTC 24 |
| Finished | Sep 18 09:24:33 PM UTC 24 |
| Peak memory | 235900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223994710 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3223994710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.45396109 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 1088439376 ps |
| CPU time | 12.46 seconds |
| Started | Sep 18 09:24:29 PM UTC 24 |
| Finished | Sep 18 09:24:43 PM UTC 24 |
| Peak memory | 231660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45396109 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.45396109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.3505521870 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 391771906 ps |
| CPU time | 11.82 seconds |
| Started | Sep 18 09:24:29 PM UTC 24 |
| Finished | Sep 18 09:24:42 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505521870 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_to ken_digest.3505521870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.1212971960 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 900328926 ps |
| CPU time | 7.52 seconds |
| Started | Sep 18 09:24:29 PM UTC 24 |
| Finished | Sep 18 09:24:38 PM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212971960 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token _mux.1212971960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.2110179077 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 300944832 ps |
| CPU time | 7.55 seconds |
| Started | Sep 18 09:24:29 PM UTC 24 |
| Finished | Sep 18 09:24:38 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110179077 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2110179077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.994815009 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 21667924 ps |
| CPU time | 2.21 seconds |
| Started | Sep 18 09:24:25 PM UTC 24 |
| Finished | Sep 18 09:24:28 PM UTC 24 |
| Peak memory | 229432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994815009 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.994815009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.2393282282 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 779953078 ps |
| CPU time | 23.17 seconds |
| Started | Sep 18 09:24:26 PM UTC 24 |
| Finished | Sep 18 09:24:51 PM UTC 24 |
| Peak memory | 258264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393282282 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2393282282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.1045462657 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 334602881 ps |
| CPU time | 10.47 seconds |
| Started | Sep 18 09:24:27 PM UTC 24 |
| Finished | Sep 18 09:24:38 PM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045462657 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1045462657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.3636317885 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 6635088955 ps |
| CPU time | 143.3 seconds |
| Started | Sep 18 09:24:31 PM UTC 24 |
| Finished | Sep 18 09:26:56 PM UTC 24 |
| Peak memory | 262800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3636317885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 25.lc_ctrl_stress_all.3636317885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.2148505721 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 432680682 ps |
| CPU time | 13.15 seconds |
| Started | Sep 18 09:24:32 PM UTC 24 |
| Finished | Sep 18 09:24:46 PM UTC 24 |
| Peak memory | 237892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148505721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.2148505721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3749185279 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 16886080 ps |
| CPU time | 1.55 seconds |
| Started | Sep 18 09:24:25 PM UTC 24 |
| Finished | Sep 18 09:24:28 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749185279 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25 .lc_ctrl_volatile_unlock_smoke.3749185279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.3177049080 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 73645313 ps |
| CPU time | 1.68 seconds |
| Started | Sep 18 09:24:39 PM UTC 24 |
| Finished | Sep 18 09:24:42 PM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177049080 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3177049080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.1900705478 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 2605425697 ps |
| CPU time | 12.67 seconds |
| Started | Sep 18 09:24:36 PM UTC 24 |
| Finished | Sep 18 09:24:50 PM UTC 24 |
| Peak memory | 232272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900705478 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1900705478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.1217529293 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 4667026569 ps |
| CPU time | 19.99 seconds |
| Started | Sep 18 09:24:36 PM UTC 24 |
| Finished | Sep 18 09:24:57 PM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217529293 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1217529293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.3346866801 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 233217432 ps |
| CPU time | 2.36 seconds |
| Started | Sep 18 09:24:35 PM UTC 24 |
| Finished | Sep 18 09:24:38 PM UTC 24 |
| Peak memory | 233848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346866801 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3346866801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2489148926 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 392637602 ps |
| CPU time | 17.82 seconds |
| Started | Sep 18 09:24:36 PM UTC 24 |
| Finished | Sep 18 09:24:55 PM UTC 24 |
| Peak memory | 231796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489148926 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2489148926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.583227621 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 655833845 ps |
| CPU time | 8.6 seconds |
| Started | Sep 18 09:24:38 PM UTC 24 |
| Finished | Sep 18 09:24:47 PM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583227621 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_tok en_digest.583227621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.688685514 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 530213290 ps |
| CPU time | 8.59 seconds |
| Started | Sep 18 09:24:38 PM UTC 24 |
| Finished | Sep 18 09:24:47 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688685514 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_ mux.688685514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.4022660359 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 307286159 ps |
| CPU time | 12.9 seconds |
| Started | Sep 18 09:24:36 PM UTC 24 |
| Finished | Sep 18 09:24:50 PM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022660359 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.4022660359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.955383229 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 57725641 ps |
| CPU time | 3.29 seconds |
| Started | Sep 18 09:24:33 PM UTC 24 |
| Finished | Sep 18 09:24:37 PM UTC 24 |
| Peak memory | 223488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955383229 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.955383229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.2620494132 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 374307125 ps |
| CPU time | 16.03 seconds |
| Started | Sep 18 09:24:34 PM UTC 24 |
| Finished | Sep 18 09:24:52 PM UTC 24 |
| Peak memory | 262276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620494132 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2620494132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.1791615831 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 298515826 ps |
| CPU time | 8.4 seconds |
| Started | Sep 18 09:24:34 PM UTC 24 |
| Finished | Sep 18 09:24:44 PM UTC 24 |
| Peak memory | 262328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791615831 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1791615831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.138563642 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 5764253698 ps |
| CPU time | 87.71 seconds |
| Started | Sep 18 09:24:38 PM UTC 24 |
| Finished | Sep 18 09:26:07 PM UTC 24 |
| Peak memory | 285096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=138563642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 26.lc_ctrl_stress_all.138563642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1820022021 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 7061905912 ps |
| CPU time | 201.24 seconds |
| Started | Sep 18 09:24:39 PM UTC 24 |
| Finished | Sep 18 09:28:03 PM UTC 24 |
| Peak memory | 291352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820022021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.1820022021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3665776183 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 115164690 ps |
| CPU time | 1.58 seconds |
| Started | Sep 18 09:24:34 PM UTC 24 |
| Finished | Sep 18 09:24:37 PM UTC 24 |
| Peak memory | 222420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665776183 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26 .lc_ctrl_volatile_unlock_smoke.3665776183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.116795011 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 58891454 ps |
| CPU time | 1.32 seconds |
| Started | Sep 18 09:24:44 PM UTC 24 |
| Finished | Sep 18 09:24:46 PM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116795011 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.116795011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_errors.312229619 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 395505493 ps |
| CPU time | 9.21 seconds |
| Started | Sep 18 09:24:39 PM UTC 24 |
| Finished | Sep 18 09:24:50 PM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312229619 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.312229619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.676595663 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1028076619 ps |
| CPU time | 15.07 seconds |
| Started | Sep 18 09:24:41 PM UTC 24 |
| Finished | Sep 18 09:24:57 PM UTC 24 |
| Peak memory | 229324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676595663 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.676595663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.1426941974 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 30265700 ps |
| CPU time | 2.49 seconds |
| Started | Sep 18 09:24:39 PM UTC 24 |
| Finished | Sep 18 09:24:43 PM UTC 24 |
| Peak memory | 234180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426941974 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1426941974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.1645622679 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 281501125 ps |
| CPU time | 11.33 seconds |
| Started | Sep 18 09:24:41 PM UTC 24 |
| Finished | Sep 18 09:24:54 PM UTC 24 |
| Peak memory | 237292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645622679 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1645622679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.3791983305 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 831608216 ps |
| CPU time | 10.99 seconds |
| Started | Sep 18 09:24:42 PM UTC 24 |
| Finished | Sep 18 09:24:54 PM UTC 24 |
| Peak memory | 237868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791983305 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_to ken_digest.3791983305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.535320392 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1537487895 ps |
| CPU time | 16.45 seconds |
| Started | Sep 18 09:24:42 PM UTC 24 |
| Finished | Sep 18 09:25:00 PM UTC 24 |
| Peak memory | 230020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535320392 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_ mux.535320392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.2995851882 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1333499630 ps |
| CPU time | 14.03 seconds |
| Started | Sep 18 09:24:41 PM UTC 24 |
| Finished | Sep 18 09:24:56 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995851882 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2995851882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.3204952037 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 107247111 ps |
| CPU time | 1.82 seconds |
| Started | Sep 18 09:24:39 PM UTC 24 |
| Finished | Sep 18 09:24:42 PM UTC 24 |
| Peak memory | 228152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204952037 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3204952037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.2291534075 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 802501156 ps |
| CPU time | 22.9 seconds |
| Started | Sep 18 09:24:39 PM UTC 24 |
| Finished | Sep 18 09:25:04 PM UTC 24 |
| Peak memory | 262424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291534075 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2291534075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.4203623620 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 89951460 ps |
| CPU time | 4.64 seconds |
| Started | Sep 18 09:24:39 PM UTC 24 |
| Finished | Sep 18 09:24:45 PM UTC 24 |
| Peak memory | 229760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203623620 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.4203623620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.343084625 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 3565922078 ps |
| CPU time | 55.14 seconds |
| Started | Sep 18 09:24:44 PM UTC 24 |
| Finished | Sep 18 09:25:40 PM UTC 24 |
| Peak memory | 231512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=343084625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 27.lc_ctrl_stress_all.343084625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2037026122 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 7502027940 ps |
| CPU time | 79.79 seconds |
| Started | Sep 18 09:24:44 PM UTC 24 |
| Finished | Sep 18 09:26:05 PM UTC 24 |
| Peak memory | 260628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037026122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.2037026122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2103559758 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 17070933 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 09:24:39 PM UTC 24 |
| Finished | Sep 18 09:24:42 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103559758 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27 .lc_ctrl_volatile_unlock_smoke.2103559758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.948864700 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 32868854 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 09:24:51 PM UTC 24 |
| Finished | Sep 18 09:24:53 PM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948864700 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.948864700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.3791570411 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 343714335 ps |
| CPU time | 13.37 seconds |
| Started | Sep 18 09:24:47 PM UTC 24 |
| Finished | Sep 18 09:25:02 PM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791570411 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3791570411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.3397384418 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 181364991 ps |
| CPU time | 5.48 seconds |
| Started | Sep 18 09:24:48 PM UTC 24 |
| Finished | Sep 18 09:24:54 PM UTC 24 |
| Peak memory | 228704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397384418 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3397384418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.3580963043 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 644480175 ps |
| CPU time | 4.54 seconds |
| Started | Sep 18 09:24:46 PM UTC 24 |
| Finished | Sep 18 09:24:52 PM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580963043 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3580963043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.2189990764 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 804631916 ps |
| CPU time | 17.46 seconds |
| Started | Sep 18 09:24:49 PM UTC 24 |
| Finished | Sep 18 09:25:08 PM UTC 24 |
| Peak memory | 231728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189990764 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2189990764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.1519679388 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1351861657 ps |
| CPU time | 10.01 seconds |
| Started | Sep 18 09:24:49 PM UTC 24 |
| Finished | Sep 18 09:25:00 PM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519679388 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_to ken_digest.1519679388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.2361147200 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 439154348 ps |
| CPU time | 13.69 seconds |
| Started | Sep 18 09:24:49 PM UTC 24 |
| Finished | Sep 18 09:25:04 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361147200 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token _mux.2361147200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.534819232 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 440893038 ps |
| CPU time | 11.26 seconds |
| Started | Sep 18 09:24:47 PM UTC 24 |
| Finished | Sep 18 09:25:00 PM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534819232 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.534819232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.2383211366 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 37755342 ps |
| CPU time | 2.98 seconds |
| Started | Sep 18 09:24:44 PM UTC 24 |
| Finished | Sep 18 09:24:48 PM UTC 24 |
| Peak memory | 223556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383211366 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2383211366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.2690488695 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 5077174114 ps |
| CPU time | 31.12 seconds |
| Started | Sep 18 09:24:45 PM UTC 24 |
| Finished | Sep 18 09:25:18 PM UTC 24 |
| Peak memory | 260428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690488695 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2690488695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.2405112960 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 214707793 ps |
| CPU time | 9.78 seconds |
| Started | Sep 18 09:24:45 PM UTC 24 |
| Finished | Sep 18 09:24:56 PM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405112960 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2405112960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.4136698769 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 4887850212 ps |
| CPU time | 119.37 seconds |
| Started | Sep 18 09:24:49 PM UTC 24 |
| Finished | Sep 18 09:26:51 PM UTC 24 |
| Peak memory | 248128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4136698769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 28.lc_ctrl_stress_all.4136698769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.10687992 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 40526519 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 09:24:45 PM UTC 24 |
| Finished | Sep 18 09:24:47 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10687992 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.l c_ctrl_volatile_unlock_smoke.10687992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.3515449557 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 107444246 ps |
| CPU time | 1.75 seconds |
| Started | Sep 18 09:24:55 PM UTC 24 |
| Finished | Sep 18 09:24:58 PM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515449557 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3515449557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.1373548588 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 2415053673 ps |
| CPU time | 9.73 seconds |
| Started | Sep 18 09:24:52 PM UTC 24 |
| Finished | Sep 18 09:25:03 PM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373548588 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1373548588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.3586632724 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 264825329 ps |
| CPU time | 3.27 seconds |
| Started | Sep 18 09:24:54 PM UTC 24 |
| Finished | Sep 18 09:24:58 PM UTC 24 |
| Peak memory | 228576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586632724 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3586632724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.3169396991 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 197090659 ps |
| CPU time | 3.8 seconds |
| Started | Sep 18 09:24:52 PM UTC 24 |
| Finished | Sep 18 09:24:57 PM UTC 24 |
| Peak memory | 234176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169396991 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3169396991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.4012179349 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 989336824 ps |
| CPU time | 27.95 seconds |
| Started | Sep 18 09:24:54 PM UTC 24 |
| Finished | Sep 18 09:25:23 PM UTC 24 |
| Peak memory | 231792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012179349 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.4012179349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.1226540848 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 603449788 ps |
| CPU time | 12.49 seconds |
| Started | Sep 18 09:24:55 PM UTC 24 |
| Finished | Sep 18 09:25:09 PM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226540848 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_to ken_digest.1226540848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.3225840180 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 1130494355 ps |
| CPU time | 11.98 seconds |
| Started | Sep 18 09:24:54 PM UTC 24 |
| Finished | Sep 18 09:25:07 PM UTC 24 |
| Peak memory | 230100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225840180 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token _mux.3225840180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.2502265841 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 2250971054 ps |
| CPU time | 10.55 seconds |
| Started | Sep 18 09:24:52 PM UTC 24 |
| Finished | Sep 18 09:25:04 PM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502265841 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2502265841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.3052887343 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 157074804 ps |
| CPU time | 2.87 seconds |
| Started | Sep 18 09:24:51 PM UTC 24 |
| Finished | Sep 18 09:24:55 PM UTC 24 |
| Peak memory | 231644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052887343 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3052887343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.721084652 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 491315883 ps |
| CPU time | 31.94 seconds |
| Started | Sep 18 09:24:51 PM UTC 24 |
| Finished | Sep 18 09:25:24 PM UTC 24 |
| Peak memory | 260440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721084652 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.721084652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.1139467705 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 390646762 ps |
| CPU time | 7.34 seconds |
| Started | Sep 18 09:24:51 PM UTC 24 |
| Finished | Sep 18 09:24:59 PM UTC 24 |
| Peak memory | 262296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139467705 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1139467705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.3055176321 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 2450072996 ps |
| CPU time | 50.74 seconds |
| Started | Sep 18 09:24:55 PM UTC 24 |
| Finished | Sep 18 09:25:47 PM UTC 24 |
| Peak memory | 262800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3055176321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 29.lc_ctrl_stress_all.3055176321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.3971983150 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 40589056961 ps |
| CPU time | 62.16 seconds |
| Started | Sep 18 09:24:55 PM UTC 24 |
| Finished | Sep 18 09:25:59 PM UTC 24 |
| Peak memory | 262596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971983150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.3971983150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2277322821 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 12946746 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 09:24:51 PM UTC 24 |
| Finished | Sep 18 09:24:53 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277322821 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29 .lc_ctrl_volatile_unlock_smoke.2277322821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.2119766611 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 31504896 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 09:20:35 PM UTC 24 |
| Finished | Sep 18 09:20:38 PM UTC 24 |
| Peak memory | 218268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119766611 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2119766611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3124087736 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 12863485 ps |
| CPU time | 1.3 seconds |
| Started | Sep 18 09:20:22 PM UTC 24 |
| Finished | Sep 18 09:20:25 PM UTC 24 |
| Peak memory | 217912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124087736 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3124087736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.3400029175 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 654865953 ps |
| CPU time | 16.82 seconds |
| Started | Sep 18 09:20:22 PM UTC 24 |
| Finished | Sep 18 09:20:40 PM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400029175 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3400029175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.478481742 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 775521833 ps |
| CPU time | 13.29 seconds |
| Started | Sep 18 09:20:27 PM UTC 24 |
| Finished | Sep 18 09:20:42 PM UTC 24 |
| Peak memory | 229332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478481742 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.478481742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.4095919364 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3212768031 ps |
| CPU time | 38.76 seconds |
| Started | Sep 18 09:20:26 PM UTC 24 |
| Finished | Sep 18 09:21:06 PM UTC 24 |
| Peak memory | 231796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095919364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jt ag_errors.4095919364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.1053656973 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1651568135 ps |
| CPU time | 14.13 seconds |
| Started | Sep 18 09:20:28 PM UTC 24 |
| Finished | Sep 18 09:20:44 PM UTC 24 |
| Peak memory | 229580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053656973 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_prior ity.1053656973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.2014477085 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1619691755 ps |
| CPU time | 10.92 seconds |
| Started | Sep 18 09:20:25 PM UTC 24 |
| Finished | Sep 18 09:20:37 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014477085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl _jtag_prog_failure.2014477085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2888912286 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1872603710 ps |
| CPU time | 33.68 seconds |
| Started | Sep 18 09:20:29 PM UTC 24 |
| Finished | Sep 18 09:21:04 PM UTC 24 |
| Peak memory | 223332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888912286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ ctrl_jtag_regwen_during_op.2888912286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.1049426830 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1567848435 ps |
| CPU time | 9.12 seconds |
| Started | Sep 18 09:20:23 PM UTC 24 |
| Finished | Sep 18 09:20:33 PM UTC 24 |
| Peak memory | 223416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049426830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_s moke.1049426830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.1659715695 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 7872032610 ps |
| CPU time | 29.93 seconds |
| Started | Sep 18 09:20:24 PM UTC 24 |
| Finished | Sep 18 09:20:55 PM UTC 24 |
| Peak memory | 262544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659715695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr l_jtag_state_failure.1659715695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.524286481 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 966890568 ps |
| CPU time | 22.79 seconds |
| Started | Sep 18 09:20:25 PM UTC 24 |
| Finished | Sep 18 09:20:49 PM UTC 24 |
| Peak memory | 236248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524286481 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_c trl_jtag_state_post_trans.524286481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.99164015 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 100307302 ps |
| CPU time | 5 seconds |
| Started | Sep 18 09:20:21 PM UTC 24 |
| Finished | Sep 18 09:20:27 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99164015 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.99164015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.26708472 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 383845404 ps |
| CPU time | 11.18 seconds |
| Started | Sep 18 09:20:22 PM UTC 24 |
| Finished | Sep 18 09:20:35 PM UTC 24 |
| Peak memory | 225580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26708472 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.26708472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.2860515825 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 822455479 ps |
| CPU time | 46.06 seconds |
| Started | Sep 18 09:20:34 PM UTC 24 |
| Finished | Sep 18 09:21:22 PM UTC 24 |
| Peak memory | 291712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860515825 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2860515825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.1802423423 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 866779709 ps |
| CPU time | 25.51 seconds |
| Started | Sep 18 09:20:29 PM UTC 24 |
| Finished | Sep 18 09:20:55 PM UTC 24 |
| Peak memory | 237420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802423423 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1802423423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.4281318670 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1381914514 ps |
| CPU time | 15.46 seconds |
| Started | Sep 18 09:20:33 PM UTC 24 |
| Finished | Sep 18 09:20:50 PM UTC 24 |
| Peak memory | 237716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281318670 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_tok en_digest.4281318670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.1867602424 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 809276202 ps |
| CPU time | 7.12 seconds |
| Started | Sep 18 09:20:32 PM UTC 24 |
| Finished | Sep 18 09:20:40 PM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867602424 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_ mux.1867602424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.1112719060 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 429466012 ps |
| CPU time | 13.7 seconds |
| Started | Sep 18 09:20:22 PM UTC 24 |
| Finished | Sep 18 09:20:37 PM UTC 24 |
| Peak memory | 229760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112719060 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1112719060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.2637567698 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 455092149 ps |
| CPU time | 3.26 seconds |
| Started | Sep 18 09:20:18 PM UTC 24 |
| Finished | Sep 18 09:20:22 PM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637567698 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2637567698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.3194342601 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 671366598 ps |
| CPU time | 21.89 seconds |
| Started | Sep 18 09:20:20 PM UTC 24 |
| Finished | Sep 18 09:20:43 PM UTC 24 |
| Peak memory | 262752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194342601 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3194342601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.1315388296 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 234357624 ps |
| CPU time | 10.77 seconds |
| Started | Sep 18 09:20:21 PM UTC 24 |
| Finished | Sep 18 09:20:33 PM UTC 24 |
| Peak memory | 260228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315388296 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1315388296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.3275893139 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 12817946697 ps |
| CPU time | 434.69 seconds |
| Started | Sep 18 09:20:34 PM UTC 24 |
| Finished | Sep 18 09:27:54 PM UTC 24 |
| Peak memory | 291216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3275893139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 3.lc_ctrl_stress_all.3275893139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1738731658 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 41666170 ps |
| CPU time | 1.57 seconds |
| Started | Sep 18 09:20:19 PM UTC 24 |
| Finished | Sep 18 09:20:21 PM UTC 24 |
| Peak memory | 220196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738731658 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3. lc_ctrl_volatile_unlock_smoke.1738731658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.3698872052 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 64764661 ps |
| CPU time | 1.59 seconds |
| Started | Sep 18 09:25:03 PM UTC 24 |
| Finished | Sep 18 09:25:06 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698872052 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3698872052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_errors.1746352182 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 624079746 ps |
| CPU time | 12.58 seconds |
| Started | Sep 18 09:24:59 PM UTC 24 |
| Finished | Sep 18 09:25:12 PM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746352182 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1746352182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.2474464735 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1453153333 ps |
| CPU time | 7.63 seconds |
| Started | Sep 18 09:24:59 PM UTC 24 |
| Finished | Sep 18 09:25:08 PM UTC 24 |
| Peak memory | 229052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474464735 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2474464735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.2928769256 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 244115429 ps |
| CPU time | 3.21 seconds |
| Started | Sep 18 09:24:59 PM UTC 24 |
| Finished | Sep 18 09:25:03 PM UTC 24 |
| Peak memory | 233920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928769256 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2928769256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.3924963966 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 451851789 ps |
| CPU time | 11.36 seconds |
| Started | Sep 18 09:25:00 PM UTC 24 |
| Finished | Sep 18 09:25:12 PM UTC 24 |
| Peak memory | 237500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924963966 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3924963966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.2553155496 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 346048393 ps |
| CPU time | 11.89 seconds |
| Started | Sep 18 09:25:01 PM UTC 24 |
| Finished | Sep 18 09:25:15 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553155496 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_to ken_digest.2553155496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.1537992155 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 390739177 ps |
| CPU time | 10.48 seconds |
| Started | Sep 18 09:25:01 PM UTC 24 |
| Finished | Sep 18 09:25:13 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537992155 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token _mux.1537992155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.3417253829 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 426099966 ps |
| CPU time | 8.17 seconds |
| Started | Sep 18 09:24:59 PM UTC 24 |
| Finished | Sep 18 09:25:08 PM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417253829 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3417253829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.3860145279 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 177205067 ps |
| CPU time | 3.92 seconds |
| Started | Sep 18 09:24:56 PM UTC 24 |
| Finished | Sep 18 09:25:01 PM UTC 24 |
| Peak memory | 225480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860145279 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3860145279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.2054834147 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 284788969 ps |
| CPU time | 25.6 seconds |
| Started | Sep 18 09:24:58 PM UTC 24 |
| Finished | Sep 18 09:25:24 PM UTC 24 |
| Peak memory | 262700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054834147 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2054834147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.993251824 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 284910448 ps |
| CPU time | 9.05 seconds |
| Started | Sep 18 09:24:58 PM UTC 24 |
| Finished | Sep 18 09:25:08 PM UTC 24 |
| Peak memory | 262352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993251824 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.993251824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.1056125252 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3837261080 ps |
| CPU time | 82.5 seconds |
| Started | Sep 18 09:25:01 PM UTC 24 |
| Finished | Sep 18 09:26:26 PM UTC 24 |
| Peak memory | 262540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1056125252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 30.lc_ctrl_stress_all.1056125252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.638703726 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 13498668 ps |
| CPU time | 1.23 seconds |
| Started | Sep 18 09:24:57 PM UTC 24 |
| Finished | Sep 18 09:25:00 PM UTC 24 |
| Peak memory | 217300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638703726 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30. lc_ctrl_volatile_unlock_smoke.638703726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.2003389661 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 24449051 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 09:25:08 PM UTC 24 |
| Finished | Sep 18 09:25:10 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003389661 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2003389661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.2886083303 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 170427608 ps |
| CPU time | 9.47 seconds |
| Started | Sep 18 09:25:05 PM UTC 24 |
| Finished | Sep 18 09:25:16 PM UTC 24 |
| Peak memory | 229768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886083303 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2886083303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.1010914586 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1263380148 ps |
| CPU time | 5.11 seconds |
| Started | Sep 18 09:25:05 PM UTC 24 |
| Finished | Sep 18 09:25:12 PM UTC 24 |
| Peak memory | 228744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010914586 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1010914586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.1787794069 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 388794327 ps |
| CPU time | 5.02 seconds |
| Started | Sep 18 09:25:05 PM UTC 24 |
| Finished | Sep 18 09:25:11 PM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787794069 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1787794069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.368127620 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 2023711030 ps |
| CPU time | 15.06 seconds |
| Started | Sep 18 09:25:05 PM UTC 24 |
| Finished | Sep 18 09:25:22 PM UTC 24 |
| Peak memory | 231800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368127620 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.368127620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.889038750 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 2139764000 ps |
| CPU time | 15.78 seconds |
| Started | Sep 18 09:25:05 PM UTC 24 |
| Finished | Sep 18 09:25:22 PM UTC 24 |
| Peak memory | 237760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889038750 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_tok en_digest.889038750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.4126373526 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 186922482 ps |
| CPU time | 7.49 seconds |
| Started | Sep 18 09:25:05 PM UTC 24 |
| Finished | Sep 18 09:25:14 PM UTC 24 |
| Peak memory | 230144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126373526 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token _mux.4126373526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.3623684111 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 498315418 ps |
| CPU time | 8.08 seconds |
| Started | Sep 18 09:25:05 PM UTC 24 |
| Finished | Sep 18 09:25:14 PM UTC 24 |
| Peak memory | 229976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623684111 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3623684111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.3873421927 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 182638722 ps |
| CPU time | 3.53 seconds |
| Started | Sep 18 09:25:03 PM UTC 24 |
| Finished | Sep 18 09:25:08 PM UTC 24 |
| Peak memory | 225676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873421927 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3873421927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.4029462572 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 270728579 ps |
| CPU time | 26.94 seconds |
| Started | Sep 18 09:25:03 PM UTC 24 |
| Finished | Sep 18 09:25:31 PM UTC 24 |
| Peak memory | 262360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029462572 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.4029462572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.348329821 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 99444538 ps |
| CPU time | 7.89 seconds |
| Started | Sep 18 09:25:03 PM UTC 24 |
| Finished | Sep 18 09:25:12 PM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348329821 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.348329821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.3429275985 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 5379525026 ps |
| CPU time | 74.86 seconds |
| Started | Sep 18 09:25:07 PM UTC 24 |
| Finished | Sep 18 09:26:23 PM UTC 24 |
| Peak memory | 291472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3429275985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 31.lc_ctrl_stress_all.3429275985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.189460447 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 8872854302 ps |
| CPU time | 127.3 seconds |
| Started | Sep 18 09:25:07 PM UTC 24 |
| Finished | Sep 18 09:27:16 PM UTC 24 |
| Peak memory | 293604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189460447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.189460447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.4097148438 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 11580109 ps |
| CPU time | 1.21 seconds |
| Started | Sep 18 09:25:03 PM UTC 24 |
| Finished | Sep 18 09:25:05 PM UTC 24 |
| Peak memory | 217232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097148438 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31 .lc_ctrl_volatile_unlock_smoke.4097148438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.2653794170 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 126797876 ps |
| CPU time | 1.47 seconds |
| Started | Sep 18 09:25:14 PM UTC 24 |
| Finished | Sep 18 09:25:17 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653794170 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.2653794170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_errors.1777532499 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 889880063 ps |
| CPU time | 10.69 seconds |
| Started | Sep 18 09:25:09 PM UTC 24 |
| Finished | Sep 18 09:25:21 PM UTC 24 |
| Peak memory | 229972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777532499 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1777532499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.2255891745 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 11964158451 ps |
| CPU time | 8.83 seconds |
| Started | Sep 18 09:25:13 PM UTC 24 |
| Finished | Sep 18 09:25:23 PM UTC 24 |
| Peak memory | 229260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255891745 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2255891745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.4254717287 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 380378552 ps |
| CPU time | 4.53 seconds |
| Started | Sep 18 09:25:09 PM UTC 24 |
| Finished | Sep 18 09:25:15 PM UTC 24 |
| Peak memory | 235920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254717287 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.4254717287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.375440345 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 1348232391 ps |
| CPU time | 10.44 seconds |
| Started | Sep 18 09:25:13 PM UTC 24 |
| Finished | Sep 18 09:25:24 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375440345 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.375440345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.3569025363 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 2037714442 ps |
| CPU time | 17.57 seconds |
| Started | Sep 18 09:25:13 PM UTC 24 |
| Finished | Sep 18 09:25:32 PM UTC 24 |
| Peak memory | 229892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569025363 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_to ken_digest.3569025363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.875050593 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 4187834562 ps |
| CPU time | 12.11 seconds |
| Started | Sep 18 09:25:13 PM UTC 24 |
| Finished | Sep 18 09:25:26 PM UTC 24 |
| Peak memory | 237892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875050593 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_ mux.875050593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.542027858 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1037521050 ps |
| CPU time | 11.41 seconds |
| Started | Sep 18 09:25:10 PM UTC 24 |
| Finished | Sep 18 09:25:23 PM UTC 24 |
| Peak memory | 229760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542027858 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.542027858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.786345274 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 50645003 ps |
| CPU time | 2.64 seconds |
| Started | Sep 18 09:25:09 PM UTC 24 |
| Finished | Sep 18 09:25:13 PM UTC 24 |
| Peak memory | 223488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786345274 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.786345274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.1239582026 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 251157397 ps |
| CPU time | 23.86 seconds |
| Started | Sep 18 09:25:09 PM UTC 24 |
| Finished | Sep 18 09:25:35 PM UTC 24 |
| Peak memory | 262500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239582026 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1239582026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.3749541873 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 99288557 ps |
| CPU time | 3.73 seconds |
| Started | Sep 18 09:25:09 PM UTC 24 |
| Finished | Sep 18 09:25:14 PM UTC 24 |
| Peak memory | 234332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749541873 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3749541873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.3490366723 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 7296767850 ps |
| CPU time | 133 seconds |
| Started | Sep 18 09:25:14 PM UTC 24 |
| Finished | Sep 18 09:27:30 PM UTC 24 |
| Peak memory | 289020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3490366723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 32.lc_ctrl_stress_all.3490366723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2285344079 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 24441012 ps |
| CPU time | 1.28 seconds |
| Started | Sep 18 09:25:09 PM UTC 24 |
| Finished | Sep 18 09:25:12 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285344079 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32 .lc_ctrl_volatile_unlock_smoke.2285344079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.2258525415 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 35199320 ps |
| CPU time | 1.23 seconds |
| Started | Sep 18 09:25:19 PM UTC 24 |
| Finished | Sep 18 09:25:21 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258525415 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2258525415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.2742752277 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 423145498 ps |
| CPU time | 11.25 seconds |
| Started | Sep 18 09:25:17 PM UTC 24 |
| Finished | Sep 18 09:25:29 PM UTC 24 |
| Peak memory | 229768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742752277 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2742752277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.3981790506 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 70598837 ps |
| CPU time | 2.31 seconds |
| Started | Sep 18 09:25:17 PM UTC 24 |
| Finished | Sep 18 09:25:20 PM UTC 24 |
| Peak memory | 228692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981790506 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3981790506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.2542747709 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 68126333 ps |
| CPU time | 4.31 seconds |
| Started | Sep 18 09:25:17 PM UTC 24 |
| Finished | Sep 18 09:25:22 PM UTC 24 |
| Peak memory | 229736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542747709 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2542747709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.1549555738 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 453430603 ps |
| CPU time | 18.67 seconds |
| Started | Sep 18 09:25:17 PM UTC 24 |
| Finished | Sep 18 09:25:37 PM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549555738 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1549555738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.2150491720 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 737037762 ps |
| CPU time | 14.86 seconds |
| Started | Sep 18 09:25:18 PM UTC 24 |
| Finished | Sep 18 09:25:34 PM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150491720 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_to ken_digest.2150491720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.138204298 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 470085048 ps |
| CPU time | 9.73 seconds |
| Started | Sep 18 09:25:17 PM UTC 24 |
| Finished | Sep 18 09:25:28 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138204298 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_ mux.138204298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.3351899156 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 1690526746 ps |
| CPU time | 12.24 seconds |
| Started | Sep 18 09:25:17 PM UTC 24 |
| Finished | Sep 18 09:25:30 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351899156 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3351899156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.3121904462 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 35422284 ps |
| CPU time | 3.16 seconds |
| Started | Sep 18 09:25:14 PM UTC 24 |
| Finished | Sep 18 09:25:19 PM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121904462 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3121904462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.3033216431 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 840734437 ps |
| CPU time | 26.04 seconds |
| Started | Sep 18 09:25:15 PM UTC 24 |
| Finished | Sep 18 09:25:42 PM UTC 24 |
| Peak memory | 260376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033216431 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3033216431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.1333073361 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 75014057 ps |
| CPU time | 9.29 seconds |
| Started | Sep 18 09:25:17 PM UTC 24 |
| Finished | Sep 18 09:25:27 PM UTC 24 |
| Peak memory | 262424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333073361 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1333073361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.3233141385 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 3615945664 ps |
| CPU time | 141 seconds |
| Started | Sep 18 09:25:18 PM UTC 24 |
| Finished | Sep 18 09:27:42 PM UTC 24 |
| Peak memory | 295380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3233141385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 33.lc_ctrl_stress_all.3233141385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1348631784 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 17729882 ps |
| CPU time | 1.25 seconds |
| Started | Sep 18 09:25:15 PM UTC 24 |
| Finished | Sep 18 09:25:17 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348631784 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33 .lc_ctrl_volatile_unlock_smoke.1348631784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.1930404980 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 200381564 ps |
| CPU time | 1.57 seconds |
| Started | Sep 18 09:25:25 PM UTC 24 |
| Finished | Sep 18 09:25:28 PM UTC 24 |
| Peak memory | 218080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930404980 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1930404980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.1264356511 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 262897208 ps |
| CPU time | 9.76 seconds |
| Started | Sep 18 09:25:23 PM UTC 24 |
| Finished | Sep 18 09:25:34 PM UTC 24 |
| Peak memory | 229768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264356511 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1264356511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.3637533100 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 369651896 ps |
| CPU time | 6.1 seconds |
| Started | Sep 18 09:25:23 PM UTC 24 |
| Finished | Sep 18 09:25:31 PM UTC 24 |
| Peak memory | 229172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637533100 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3637533100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3165412113 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 72639247 ps |
| CPU time | 2.03 seconds |
| Started | Sep 18 09:25:22 PM UTC 24 |
| Finished | Sep 18 09:25:25 PM UTC 24 |
| Peak memory | 233920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165412113 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3165412113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.2323090672 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 2010092622 ps |
| CPU time | 12.5 seconds |
| Started | Sep 18 09:25:23 PM UTC 24 |
| Finished | Sep 18 09:25:37 PM UTC 24 |
| Peak memory | 229744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323090672 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2323090672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.2270820649 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 361938531 ps |
| CPU time | 9.7 seconds |
| Started | Sep 18 09:25:25 PM UTC 24 |
| Finished | Sep 18 09:25:36 PM UTC 24 |
| Peak memory | 229680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270820649 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_to ken_digest.2270820649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.2372000667 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 337651172 ps |
| CPU time | 7.63 seconds |
| Started | Sep 18 09:25:23 PM UTC 24 |
| Finished | Sep 18 09:25:32 PM UTC 24 |
| Peak memory | 230156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372000667 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token _mux.2372000667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.517851496 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 603503004 ps |
| CPU time | 15.15 seconds |
| Started | Sep 18 09:25:23 PM UTC 24 |
| Finished | Sep 18 09:25:40 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517851496 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.517851496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.3506492714 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 65168089 ps |
| CPU time | 2.47 seconds |
| Started | Sep 18 09:25:20 PM UTC 24 |
| Finished | Sep 18 09:25:23 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506492714 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3506492714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.2098009532 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 195499858 ps |
| CPU time | 21.02 seconds |
| Started | Sep 18 09:25:22 PM UTC 24 |
| Finished | Sep 18 09:25:44 PM UTC 24 |
| Peak memory | 262424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098009532 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2098009532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.2991246471 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 293899428 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 09:25:22 PM UTC 24 |
| Finished | Sep 18 09:25:26 PM UTC 24 |
| Peak memory | 234328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991246471 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2991246471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.1217581904 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 42640368014 ps |
| CPU time | 330.37 seconds |
| Started | Sep 18 09:25:25 PM UTC 24 |
| Finished | Sep 18 09:31:00 PM UTC 24 |
| Peak memory | 286972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1217581904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 34.lc_ctrl_stress_all.1217581904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3383706654 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 97262590 ps |
| CPU time | 0.99 seconds |
| Started | Sep 18 09:25:21 PM UTC 24 |
| Finished | Sep 18 09:25:23 PM UTC 24 |
| Peak memory | 218204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383706654 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34 .lc_ctrl_volatile_unlock_smoke.3383706654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.506517661 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 62878177 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 09:25:32 PM UTC 24 |
| Finished | Sep 18 09:25:35 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506517661 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.506517661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.887777790 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 229233917 ps |
| CPU time | 10.37 seconds |
| Started | Sep 18 09:25:28 PM UTC 24 |
| Finished | Sep 18 09:25:39 PM UTC 24 |
| Peak memory | 230148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887777790 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.887777790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.3071086450 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 326122024 ps |
| CPU time | 9.79 seconds |
| Started | Sep 18 09:25:30 PM UTC 24 |
| Finished | Sep 18 09:25:42 PM UTC 24 |
| Peak memory | 229028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071086450 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3071086450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.3455893929 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 208419341 ps |
| CPU time | 3.68 seconds |
| Started | Sep 18 09:25:27 PM UTC 24 |
| Finished | Sep 18 09:25:32 PM UTC 24 |
| Peak memory | 234240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455893929 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3455893929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.3335461074 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 334112782 ps |
| CPU time | 11.15 seconds |
| Started | Sep 18 09:25:30 PM UTC 24 |
| Finished | Sep 18 09:25:43 PM UTC 24 |
| Peak memory | 231732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335461074 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.3335461074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.3737712800 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 597770679 ps |
| CPU time | 9.85 seconds |
| Started | Sep 18 09:25:32 PM UTC 24 |
| Finished | Sep 18 09:25:43 PM UTC 24 |
| Peak memory | 236828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737712800 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_to ken_digest.3737712800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.4267291884 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 1115438623 ps |
| CPU time | 11.91 seconds |
| Started | Sep 18 09:25:30 PM UTC 24 |
| Finished | Sep 18 09:25:44 PM UTC 24 |
| Peak memory | 230012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267291884 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token _mux.4267291884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.1025563326 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 1649893773 ps |
| CPU time | 11.12 seconds |
| Started | Sep 18 09:25:28 PM UTC 24 |
| Finished | Sep 18 09:25:40 PM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025563326 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1025563326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.1248441936 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 602268867 ps |
| CPU time | 5.87 seconds |
| Started | Sep 18 09:25:25 PM UTC 24 |
| Finished | Sep 18 09:25:33 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248441936 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1248441936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.954684964 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 415686568 ps |
| CPU time | 25.69 seconds |
| Started | Sep 18 09:25:27 PM UTC 24 |
| Finished | Sep 18 09:25:54 PM UTC 24 |
| Peak memory | 262744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954684964 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.954684964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.2740959116 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 124098066 ps |
| CPU time | 9.87 seconds |
| Started | Sep 18 09:25:27 PM UTC 24 |
| Finished | Sep 18 09:25:38 PM UTC 24 |
| Peak memory | 262284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740959116 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2740959116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.3624371357 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 34696428411 ps |
| CPU time | 295.99 seconds |
| Started | Sep 18 09:25:32 PM UTC 24 |
| Finished | Sep 18 09:30:32 PM UTC 24 |
| Peak memory | 262472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3624371357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 35.lc_ctrl_stress_all.3624371357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1619745174 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 19981577 ps |
| CPU time | 1.42 seconds |
| Started | Sep 18 09:25:27 PM UTC 24 |
| Finished | Sep 18 09:25:29 PM UTC 24 |
| Peak memory | 222240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619745174 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35 .lc_ctrl_volatile_unlock_smoke.1619745174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.1636040254 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 62156486 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 09:25:39 PM UTC 24 |
| Finished | Sep 18 09:25:41 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636040254 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1636040254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.909442017 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 194869340 ps |
| CPU time | 13.02 seconds |
| Started | Sep 18 09:25:37 PM UTC 24 |
| Finished | Sep 18 09:25:51 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909442017 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.909442017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.1628893801 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 455674641 ps |
| CPU time | 6.64 seconds |
| Started | Sep 18 09:25:37 PM UTC 24 |
| Finished | Sep 18 09:25:45 PM UTC 24 |
| Peak memory | 229000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628893801 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1628893801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.3317406485 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 297715938 ps |
| CPU time | 4.46 seconds |
| Started | Sep 18 09:25:34 PM UTC 24 |
| Finished | Sep 18 09:25:40 PM UTC 24 |
| Peak memory | 234184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317406485 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3317406485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.1378587629 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 1086236246 ps |
| CPU time | 10.13 seconds |
| Started | Sep 18 09:25:37 PM UTC 24 |
| Finished | Sep 18 09:25:48 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378587629 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1378587629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.3944520322 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 1161759984 ps |
| CPU time | 17.74 seconds |
| Started | Sep 18 09:25:38 PM UTC 24 |
| Finished | Sep 18 09:25:57 PM UTC 24 |
| Peak memory | 230072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944520322 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_to ken_digest.3944520322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.3990008507 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 595041853 ps |
| CPU time | 11.17 seconds |
| Started | Sep 18 09:25:38 PM UTC 24 |
| Finished | Sep 18 09:25:51 PM UTC 24 |
| Peak memory | 229764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990008507 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token _mux.3990008507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.874866131 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 267694454 ps |
| CPU time | 9.04 seconds |
| Started | Sep 18 09:25:37 PM UTC 24 |
| Finished | Sep 18 09:25:47 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874866131 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.874866131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.2070133423 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 31621992 ps |
| CPU time | 2.19 seconds |
| Started | Sep 18 09:25:34 PM UTC 24 |
| Finished | Sep 18 09:25:38 PM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070133423 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2070133423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.2541496353 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 254393854 ps |
| CPU time | 29.05 seconds |
| Started | Sep 18 09:25:34 PM UTC 24 |
| Finished | Sep 18 09:26:05 PM UTC 24 |
| Peak memory | 262472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541496353 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2541496353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.730971243 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 165648719 ps |
| CPU time | 10.25 seconds |
| Started | Sep 18 09:25:34 PM UTC 24 |
| Finished | Sep 18 09:25:46 PM UTC 24 |
| Peak memory | 262276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730971243 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.730971243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.1165769040 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 19684134820 ps |
| CPU time | 206.55 seconds |
| Started | Sep 18 09:25:39 PM UTC 24 |
| Finished | Sep 18 09:29:08 PM UTC 24 |
| Peak memory | 273248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1165769040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 36.lc_ctrl_stress_all.1165769040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.819486845 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 17358662 ps |
| CPU time | 1.54 seconds |
| Started | Sep 18 09:25:34 PM UTC 24 |
| Finished | Sep 18 09:25:37 PM UTC 24 |
| Peak memory | 222244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819486845 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36. lc_ctrl_volatile_unlock_smoke.819486845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.3750298974 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 25637945 ps |
| CPU time | 1.21 seconds |
| Started | Sep 18 09:25:44 PM UTC 24 |
| Finished | Sep 18 09:25:46 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750298974 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3750298974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.1315459141 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 2159905395 ps |
| CPU time | 5.58 seconds |
| Started | Sep 18 09:25:42 PM UTC 24 |
| Finished | Sep 18 09:25:49 PM UTC 24 |
| Peak memory | 228892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315459141 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1315459141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.1982635230 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 235487240 ps |
| CPU time | 3.95 seconds |
| Started | Sep 18 09:25:41 PM UTC 24 |
| Finished | Sep 18 09:25:46 PM UTC 24 |
| Peak memory | 229824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982635230 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1982635230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.2770570352 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 837866630 ps |
| CPU time | 12.44 seconds |
| Started | Sep 18 09:25:43 PM UTC 24 |
| Finished | Sep 18 09:25:56 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770570352 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2770570352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.990655497 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 294497027 ps |
| CPU time | 11.81 seconds |
| Started | Sep 18 09:25:43 PM UTC 24 |
| Finished | Sep 18 09:25:56 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990655497 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_tok en_digest.990655497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.132790944 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 476786045 ps |
| CPU time | 10.98 seconds |
| Started | Sep 18 09:25:43 PM UTC 24 |
| Finished | Sep 18 09:25:55 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132790944 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_ mux.132790944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.2290732012 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2456482096 ps |
| CPU time | 7.52 seconds |
| Started | Sep 18 09:25:42 PM UTC 24 |
| Finished | Sep 18 09:25:51 PM UTC 24 |
| Peak memory | 229964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290732012 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2290732012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.1920295432 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 342849616 ps |
| CPU time | 3.56 seconds |
| Started | Sep 18 09:25:39 PM UTC 24 |
| Finished | Sep 18 09:25:43 PM UTC 24 |
| Peak memory | 225456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920295432 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1920295432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.3474926513 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 738939908 ps |
| CPU time | 25.4 seconds |
| Started | Sep 18 09:25:41 PM UTC 24 |
| Finished | Sep 18 09:26:08 PM UTC 24 |
| Peak memory | 262284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474926513 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3474926513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.3891341929 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 169059702 ps |
| CPU time | 6.95 seconds |
| Started | Sep 18 09:25:41 PM UTC 24 |
| Finished | Sep 18 09:25:49 PM UTC 24 |
| Peak memory | 262272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891341929 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3891341929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.2721296641 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 1123786910 ps |
| CPU time | 47.95 seconds |
| Started | Sep 18 09:25:44 PM UTC 24 |
| Finished | Sep 18 09:26:33 PM UTC 24 |
| Peak memory | 258448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2721296641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 37.lc_ctrl_stress_all.2721296641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.616815762 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 18794477870 ps |
| CPU time | 46.69 seconds |
| Started | Sep 18 09:25:44 PM UTC 24 |
| Finished | Sep 18 09:26:32 PM UTC 24 |
| Peak memory | 254412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616815762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.616815762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3405701529 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 20953285 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 09:25:40 PM UTC 24 |
| Finished | Sep 18 09:25:42 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405701529 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37 .lc_ctrl_volatile_unlock_smoke.3405701529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.95797019 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 59023038 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 09:25:51 PM UTC 24 |
| Finished | Sep 18 09:25:53 PM UTC 24 |
| Peak memory | 218080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95797019 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.95797019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.2398948242 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 6228423872 ps |
| CPU time | 11.52 seconds |
| Started | Sep 18 09:25:48 PM UTC 24 |
| Finished | Sep 18 09:26:01 PM UTC 24 |
| Peak memory | 232180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398948242 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2398948242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2299518458 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 1859811254 ps |
| CPU time | 4.54 seconds |
| Started | Sep 18 09:25:49 PM UTC 24 |
| Finished | Sep 18 09:25:55 PM UTC 24 |
| Peak memory | 228772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299518458 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2299518458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.3670285086 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 78072381 ps |
| CPU time | 3.49 seconds |
| Started | Sep 18 09:25:48 PM UTC 24 |
| Finished | Sep 18 09:25:52 PM UTC 24 |
| Peak memory | 233896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670285086 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3670285086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.3445665131 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 1310232200 ps |
| CPU time | 8.97 seconds |
| Started | Sep 18 09:25:49 PM UTC 24 |
| Finished | Sep 18 09:26:00 PM UTC 24 |
| Peak memory | 231792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445665131 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3445665131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.2975946292 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 663275434 ps |
| CPU time | 26.63 seconds |
| Started | Sep 18 09:25:50 PM UTC 24 |
| Finished | Sep 18 09:26:19 PM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975946292 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_to ken_digest.2975946292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.3107732679 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 338357759 ps |
| CPU time | 8.52 seconds |
| Started | Sep 18 09:25:49 PM UTC 24 |
| Finished | Sep 18 09:25:59 PM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107732679 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token _mux.3107732679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.4097490936 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 206097230 ps |
| CPU time | 8.02 seconds |
| Started | Sep 18 09:25:48 PM UTC 24 |
| Finished | Sep 18 09:25:57 PM UTC 24 |
| Peak memory | 229964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097490936 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.4097490936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.1426374006 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 21713542 ps |
| CPU time | 2.53 seconds |
| Started | Sep 18 09:25:45 PM UTC 24 |
| Finished | Sep 18 09:25:49 PM UTC 24 |
| Peak memory | 223476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426374006 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1426374006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.649491043 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 908239741 ps |
| CPU time | 23.69 seconds |
| Started | Sep 18 09:25:45 PM UTC 24 |
| Finished | Sep 18 09:26:11 PM UTC 24 |
| Peak memory | 262344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649491043 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.649491043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.2835454652 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 77229410 ps |
| CPU time | 9.51 seconds |
| Started | Sep 18 09:25:46 PM UTC 24 |
| Finished | Sep 18 09:25:57 PM UTC 24 |
| Peak memory | 262416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835454652 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2835454652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.670247823 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 31864535597 ps |
| CPU time | 167.73 seconds |
| Started | Sep 18 09:25:50 PM UTC 24 |
| Finished | Sep 18 09:28:41 PM UTC 24 |
| Peak memory | 321900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=670247823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 38.lc_ctrl_stress_all.670247823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1698487439 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 12950339 ps |
| CPU time | 1.08 seconds |
| Started | Sep 18 09:25:45 PM UTC 24 |
| Finished | Sep 18 09:25:48 PM UTC 24 |
| Peak memory | 217236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698487439 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38 .lc_ctrl_volatile_unlock_smoke.1698487439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.189987508 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 68151441 ps |
| CPU time | 1.49 seconds |
| Started | Sep 18 09:25:57 PM UTC 24 |
| Finished | Sep 18 09:26:00 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189987508 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.189987508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.4173677181 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 5737279892 ps |
| CPU time | 14.54 seconds |
| Started | Sep 18 09:25:54 PM UTC 24 |
| Finished | Sep 18 09:26:10 PM UTC 24 |
| Peak memory | 229892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173677181 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.4173677181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.4152397905 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 174744549 ps |
| CPU time | 3.75 seconds |
| Started | Sep 18 09:25:56 PM UTC 24 |
| Finished | Sep 18 09:26:00 PM UTC 24 |
| Peak memory | 228748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152397905 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.4152397905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.4051155952 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 103716854 ps |
| CPU time | 3.8 seconds |
| Started | Sep 18 09:25:54 PM UTC 24 |
| Finished | Sep 18 09:25:59 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051155952 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.4051155952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.740982243 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 2623904118 ps |
| CPU time | 13.98 seconds |
| Started | Sep 18 09:25:56 PM UTC 24 |
| Finished | Sep 18 09:26:11 PM UTC 24 |
| Peak memory | 231928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740982243 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.740982243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.2039440823 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 742611460 ps |
| CPU time | 22.14 seconds |
| Started | Sep 18 09:25:57 PM UTC 24 |
| Finished | Sep 18 09:26:21 PM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039440823 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_to ken_digest.2039440823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.1910133169 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 356757854 ps |
| CPU time | 9.71 seconds |
| Started | Sep 18 09:25:56 PM UTC 24 |
| Finished | Sep 18 09:26:07 PM UTC 24 |
| Peak memory | 229844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910133169 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token _mux.1910133169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.1135357360 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1067641161 ps |
| CPU time | 16.1 seconds |
| Started | Sep 18 09:25:56 PM UTC 24 |
| Finished | Sep 18 09:26:13 PM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135357360 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1135357360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.299184111 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 24981784 ps |
| CPU time | 2.34 seconds |
| Started | Sep 18 09:25:52 PM UTC 24 |
| Finished | Sep 18 09:25:55 PM UTC 24 |
| Peak memory | 223488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299184111 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.299184111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.2982921129 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 300630048 ps |
| CPU time | 22.03 seconds |
| Started | Sep 18 09:25:52 PM UTC 24 |
| Finished | Sep 18 09:26:15 PM UTC 24 |
| Peak memory | 258260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982921129 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2982921129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.3884448556 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 343552273 ps |
| CPU time | 6.76 seconds |
| Started | Sep 18 09:25:53 PM UTC 24 |
| Finished | Sep 18 09:26:01 PM UTC 24 |
| Peak memory | 262268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884448556 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3884448556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.3667323998 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 7758928151 ps |
| CPU time | 59.35 seconds |
| Started | Sep 18 09:25:57 PM UTC 24 |
| Finished | Sep 18 09:26:58 PM UTC 24 |
| Peak memory | 258568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3667323998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 39.lc_ctrl_stress_all.3667323998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.669389319 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 11347789 ps |
| CPU time | 1.03 seconds |
| Started | Sep 18 09:25:52 PM UTC 24 |
| Finished | Sep 18 09:25:54 PM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669389319 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39. lc_ctrl_volatile_unlock_smoke.669389319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.986708106 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 83327070 ps |
| CPU time | 1.55 seconds |
| Started | Sep 18 09:20:53 PM UTC 24 |
| Finished | Sep 18 09:20:56 PM UTC 24 |
| Peak memory | 218200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986708106 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.986708106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.1244777122 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 19345126 ps |
| CPU time | 1.37 seconds |
| Started | Sep 18 09:20:42 PM UTC 24 |
| Finished | Sep 18 09:20:45 PM UTC 24 |
| Peak memory | 217748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244777122 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1244777122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.3221520606 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 510378788 ps |
| CPU time | 9.98 seconds |
| Started | Sep 18 09:20:41 PM UTC 24 |
| Finished | Sep 18 09:20:52 PM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221520606 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3221520606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.3051112865 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 541101426 ps |
| CPU time | 13.81 seconds |
| Started | Sep 18 09:20:45 PM UTC 24 |
| Finished | Sep 18 09:21:00 PM UTC 24 |
| Peak memory | 229076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051112865 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3051112865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.4284508989 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 13956203718 ps |
| CPU time | 43.07 seconds |
| Started | Sep 18 09:20:45 PM UTC 24 |
| Finished | Sep 18 09:21:30 PM UTC 24 |
| Peak memory | 229664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284508989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jt ag_errors.4284508989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.1401485009 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2154988927 ps |
| CPU time | 6.72 seconds |
| Started | Sep 18 09:20:45 PM UTC 24 |
| Finished | Sep 18 09:20:53 PM UTC 24 |
| Peak memory | 229140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401485009 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_prior ity.1401485009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.644637841 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 587417271 ps |
| CPU time | 10.82 seconds |
| Started | Sep 18 09:20:44 PM UTC 24 |
| Finished | Sep 18 09:20:56 PM UTC 24 |
| Peak memory | 233880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644637841 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_prog_failure.644637841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3275587110 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 4755805276 ps |
| CPU time | 34.32 seconds |
| Started | Sep 18 09:20:45 PM UTC 24 |
| Finished | Sep 18 09:21:21 PM UTC 24 |
| Peak memory | 223460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275587110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ ctrl_jtag_regwen_during_op.3275587110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.425141744 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 223438400 ps |
| CPU time | 4.66 seconds |
| Started | Sep 18 09:20:43 PM UTC 24 |
| Finished | Sep 18 09:20:48 PM UTC 24 |
| Peak memory | 229544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425141744 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_sm oke.425141744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.1451177709 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 7201173837 ps |
| CPU time | 55.24 seconds |
| Started | Sep 18 09:20:44 PM UTC 24 |
| Finished | Sep 18 09:21:40 PM UTC 24 |
| Peak memory | 283280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451177709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr l_jtag_state_failure.1451177709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.1391675608 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 445658505 ps |
| CPU time | 12.83 seconds |
| Started | Sep 18 09:20:44 PM UTC 24 |
| Finished | Sep 18 09:20:58 PM UTC 24 |
| Peak memory | 236248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391675608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ ctrl_jtag_state_post_trans.1391675608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.3480799593 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 101086871 ps |
| CPU time | 2.55 seconds |
| Started | Sep 18 09:20:40 PM UTC 24 |
| Finished | Sep 18 09:20:44 PM UTC 24 |
| Peak memory | 229688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480799593 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3480799593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2204965589 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 388581816 ps |
| CPU time | 13.23 seconds |
| Started | Sep 18 09:20:41 PM UTC 24 |
| Finished | Sep 18 09:20:56 PM UTC 24 |
| Peak memory | 223724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204965589 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2204965589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.2508718587 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 462012271 ps |
| CPU time | 21.02 seconds |
| Started | Sep 18 09:20:53 PM UTC 24 |
| Finished | Sep 18 09:21:15 PM UTC 24 |
| Peak memory | 296072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508718587 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2508718587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.3699790675 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 998201212 ps |
| CPU time | 19.78 seconds |
| Started | Sep 18 09:20:46 PM UTC 24 |
| Finished | Sep 18 09:21:07 PM UTC 24 |
| Peak memory | 237432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699790675 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3699790675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.3696887754 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 916003252 ps |
| CPU time | 11.55 seconds |
| Started | Sep 18 09:20:51 PM UTC 24 |
| Finished | Sep 18 09:21:03 PM UTC 24 |
| Peak memory | 237424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696887754 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_tok en_digest.3696887754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.725683670 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 341641553 ps |
| CPU time | 9.01 seconds |
| Started | Sep 18 09:20:49 PM UTC 24 |
| Finished | Sep 18 09:20:59 PM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725683670 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.725683670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.405986810 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 776652272 ps |
| CPU time | 8.87 seconds |
| Started | Sep 18 09:20:41 PM UTC 24 |
| Finished | Sep 18 09:20:51 PM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405986810 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.405986810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.68005066 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 58631170 ps |
| CPU time | 4.89 seconds |
| Started | Sep 18 09:20:35 PM UTC 24 |
| Finished | Sep 18 09:20:41 PM UTC 24 |
| Peak memory | 229608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68005066 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.68005066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.3117668363 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1542304922 ps |
| CPU time | 26.18 seconds |
| Started | Sep 18 09:20:39 PM UTC 24 |
| Finished | Sep 18 09:21:06 PM UTC 24 |
| Peak memory | 262548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117668363 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3117668363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.332871684 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 249729686 ps |
| CPU time | 3.92 seconds |
| Started | Sep 18 09:20:39 PM UTC 24 |
| Finished | Sep 18 09:20:44 PM UTC 24 |
| Peak memory | 234180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332871684 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.332871684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1119496316 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 44166715 ps |
| CPU time | 1.22 seconds |
| Started | Sep 18 09:20:38 PM UTC 24 |
| Finished | Sep 18 09:20:40 PM UTC 24 |
| Peak memory | 217360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119496316 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4. lc_ctrl_volatile_unlock_smoke.1119496316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.477862264 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 19806376 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 09:26:03 PM UTC 24 |
| Finished | Sep 18 09:26:06 PM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477862264 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.477862264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.3037122592 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 340946485 ps |
| CPU time | 13.85 seconds |
| Started | Sep 18 09:26:00 PM UTC 24 |
| Finished | Sep 18 09:26:15 PM UTC 24 |
| Peak memory | 229772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037122592 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3037122592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.1054847583 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 267659487 ps |
| CPU time | 5.03 seconds |
| Started | Sep 18 09:26:02 PM UTC 24 |
| Finished | Sep 18 09:26:08 PM UTC 24 |
| Peak memory | 229132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054847583 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1054847583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.868533463 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 483133940 ps |
| CPU time | 6.66 seconds |
| Started | Sep 18 09:26:00 PM UTC 24 |
| Finished | Sep 18 09:26:08 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868533463 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.868533463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.893706369 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 1006460812 ps |
| CPU time | 11 seconds |
| Started | Sep 18 09:26:02 PM UTC 24 |
| Finished | Sep 18 09:26:14 PM UTC 24 |
| Peak memory | 231880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893706369 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.893706369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.4550609 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 607386208 ps |
| CPU time | 16.3 seconds |
| Started | Sep 18 09:26:02 PM UTC 24 |
| Finished | Sep 18 09:26:19 PM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4550609 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token _digest.4550609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.492826688 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 2083142861 ps |
| CPU time | 14.09 seconds |
| Started | Sep 18 09:26:02 PM UTC 24 |
| Finished | Sep 18 09:26:17 PM UTC 24 |
| Peak memory | 229828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492826688 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_ mux.492826688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.3979553690 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 690365250 ps |
| CPU time | 10 seconds |
| Started | Sep 18 09:26:00 PM UTC 24 |
| Finished | Sep 18 09:26:11 PM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979553690 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3979553690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.4074850947 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 38672541 ps |
| CPU time | 1.64 seconds |
| Started | Sep 18 09:25:59 PM UTC 24 |
| Finished | Sep 18 09:26:01 PM UTC 24 |
| Peak memory | 222244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074850947 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.4074850947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.3556464812 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 1127883693 ps |
| CPU time | 31.31 seconds |
| Started | Sep 18 09:25:59 PM UTC 24 |
| Finished | Sep 18 09:26:32 PM UTC 24 |
| Peak memory | 258656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556464812 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3556464812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.2292606752 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 140952935 ps |
| CPU time | 10.66 seconds |
| Started | Sep 18 09:26:00 PM UTC 24 |
| Finished | Sep 18 09:26:12 PM UTC 24 |
| Peak memory | 262428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292606752 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2292606752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.1321926862 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 17294144759 ps |
| CPU time | 139.05 seconds |
| Started | Sep 18 09:26:02 PM UTC 24 |
| Finished | Sep 18 09:28:23 PM UTC 24 |
| Peak memory | 283276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1321926862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 40.lc_ctrl_stress_all.1321926862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3279367786 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 856675646 ps |
| CPU time | 30.31 seconds |
| Started | Sep 18 09:26:03 PM UTC 24 |
| Finished | Sep 18 09:26:35 PM UTC 24 |
| Peak memory | 262476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279367786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.3279367786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1648287926 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 84653089 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 09:25:59 PM UTC 24 |
| Finished | Sep 18 09:26:01 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648287926 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40 .lc_ctrl_volatile_unlock_smoke.1648287926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.3361124438 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 29806531 ps |
| CPU time | 1.31 seconds |
| Started | Sep 18 09:26:12 PM UTC 24 |
| Finished | Sep 18 09:26:14 PM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361124438 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3361124438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.3275318635 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1662296073 ps |
| CPU time | 15.55 seconds |
| Started | Sep 18 09:26:07 PM UTC 24 |
| Finished | Sep 18 09:26:24 PM UTC 24 |
| Peak memory | 237560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275318635 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3275318635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.3676231525 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 722399256 ps |
| CPU time | 19.5 seconds |
| Started | Sep 18 09:26:09 PM UTC 24 |
| Finished | Sep 18 09:26:30 PM UTC 24 |
| Peak memory | 228820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676231525 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3676231525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.1868307530 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 84802071 ps |
| CPU time | 2.53 seconds |
| Started | Sep 18 09:26:06 PM UTC 24 |
| Finished | Sep 18 09:26:10 PM UTC 24 |
| Peak memory | 229688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868307530 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1868307530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.326485531 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 728639843 ps |
| CPU time | 15.84 seconds |
| Started | Sep 18 09:26:09 PM UTC 24 |
| Finished | Sep 18 09:26:26 PM UTC 24 |
| Peak memory | 231736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326485531 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.326485531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.2645094599 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 720751041 ps |
| CPU time | 10.4 seconds |
| Started | Sep 18 09:26:09 PM UTC 24 |
| Finished | Sep 18 09:26:21 PM UTC 24 |
| Peak memory | 229680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645094599 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_to ken_digest.2645094599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.4173655 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 981849537 ps |
| CPU time | 9.05 seconds |
| Started | Sep 18 09:26:09 PM UTC 24 |
| Finished | Sep 18 09:26:19 PM UTC 24 |
| Peak memory | 230136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173655 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.4173655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.557203612 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 2675785805 ps |
| CPU time | 9.09 seconds |
| Started | Sep 18 09:26:09 PM UTC 24 |
| Finished | Sep 18 09:26:19 PM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557203612 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.557203612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.2027623143 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 132865683 ps |
| CPU time | 5.64 seconds |
| Started | Sep 18 09:26:05 PM UTC 24 |
| Finished | Sep 18 09:26:11 PM UTC 24 |
| Peak memory | 229688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027623143 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2027623143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.2400940328 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 373766316 ps |
| CPU time | 32.39 seconds |
| Started | Sep 18 09:26:06 PM UTC 24 |
| Finished | Sep 18 09:26:40 PM UTC 24 |
| Peak memory | 260380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400940328 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2400940328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.521068099 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 89036685 ps |
| CPU time | 9.03 seconds |
| Started | Sep 18 09:26:06 PM UTC 24 |
| Finished | Sep 18 09:26:16 PM UTC 24 |
| Peak memory | 260576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521068099 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.521068099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.1765958803 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 2069163506 ps |
| CPU time | 35.64 seconds |
| Started | Sep 18 09:26:10 PM UTC 24 |
| Finished | Sep 18 09:26:47 PM UTC 24 |
| Peak memory | 256188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1765958803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 41.lc_ctrl_stress_all.1765958803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.1016879158 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1100035890 ps |
| CPU time | 22.25 seconds |
| Started | Sep 18 09:26:10 PM UTC 24 |
| Finished | Sep 18 09:26:34 PM UTC 24 |
| Peak memory | 262544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016879158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.1016879158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2317999849 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 41869600 ps |
| CPU time | 1.41 seconds |
| Started | Sep 18 09:26:06 PM UTC 24 |
| Finished | Sep 18 09:26:09 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317999849 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41 .lc_ctrl_volatile_unlock_smoke.2317999849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.3110915550 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 33110044 ps |
| CPU time | 1.63 seconds |
| Started | Sep 18 09:26:18 PM UTC 24 |
| Finished | Sep 18 09:26:20 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110915550 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3110915550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.4204181662 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 758243469 ps |
| CPU time | 17.2 seconds |
| Started | Sep 18 09:26:14 PM UTC 24 |
| Finished | Sep 18 09:26:33 PM UTC 24 |
| Peak memory | 229840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204181662 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.4204181662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.1866723343 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 980059918 ps |
| CPU time | 5.43 seconds |
| Started | Sep 18 09:26:15 PM UTC 24 |
| Finished | Sep 18 09:26:21 PM UTC 24 |
| Peak memory | 228720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866723343 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1866723343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.1559342084 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 81884987 ps |
| CPU time | 2.76 seconds |
| Started | Sep 18 09:26:13 PM UTC 24 |
| Finished | Sep 18 09:26:17 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559342084 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1559342084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.1542345226 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 1399562583 ps |
| CPU time | 14.21 seconds |
| Started | Sep 18 09:26:16 PM UTC 24 |
| Finished | Sep 18 09:26:31 PM UTC 24 |
| Peak memory | 231872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542345226 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1542345226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.2501866165 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 2439497910 ps |
| CPU time | 17.14 seconds |
| Started | Sep 18 09:26:16 PM UTC 24 |
| Finished | Sep 18 09:26:35 PM UTC 24 |
| Peak memory | 230200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501866165 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_to ken_digest.2501866165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.3983371358 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 4726076324 ps |
| CPU time | 14.71 seconds |
| Started | Sep 18 09:26:16 PM UTC 24 |
| Finished | Sep 18 09:26:32 PM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983371358 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token _mux.3983371358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.4235619221 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 392462193 ps |
| CPU time | 9.4 seconds |
| Started | Sep 18 09:26:15 PM UTC 24 |
| Finished | Sep 18 09:26:25 PM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235619221 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.4235619221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.4190057182 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 511077275 ps |
| CPU time | 6.36 seconds |
| Started | Sep 18 09:26:12 PM UTC 24 |
| Finished | Sep 18 09:26:19 PM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190057182 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.4190057182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.636799702 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 418523713 ps |
| CPU time | 19.66 seconds |
| Started | Sep 18 09:26:12 PM UTC 24 |
| Finished | Sep 18 09:26:33 PM UTC 24 |
| Peak memory | 262352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636799702 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.636799702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.2206503353 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 217636231 ps |
| CPU time | 8.56 seconds |
| Started | Sep 18 09:26:13 PM UTC 24 |
| Finished | Sep 18 09:26:23 PM UTC 24 |
| Peak memory | 262744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206503353 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2206503353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.2837692802 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 6876826385 ps |
| CPU time | 238.35 seconds |
| Started | Sep 18 09:26:16 PM UTC 24 |
| Finished | Sep 18 09:30:18 PM UTC 24 |
| Peak memory | 289168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2837692802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 42.lc_ctrl_stress_all.2837692802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.293700712 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5357992765 ps |
| CPU time | 83.66 seconds |
| Started | Sep 18 09:26:17 PM UTC 24 |
| Finished | Sep 18 09:27:43 PM UTC 24 |
| Peak memory | 285140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293700712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.293700712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3823551083 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 22506557 ps |
| CPU time | 1.61 seconds |
| Started | Sep 18 09:26:12 PM UTC 24 |
| Finished | Sep 18 09:26:14 PM UTC 24 |
| Peak memory | 222420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823551083 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42 .lc_ctrl_volatile_unlock_smoke.3823551083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.3844883445 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 38264881 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 09:26:23 PM UTC 24 |
| Finished | Sep 18 09:26:26 PM UTC 24 |
| Peak memory | 218084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844883445 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3844883445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.474404554 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1130723793 ps |
| CPU time | 16.06 seconds |
| Started | Sep 18 09:26:20 PM UTC 24 |
| Finished | Sep 18 09:26:38 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474404554 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.474404554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.1089491051 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 3600724908 ps |
| CPU time | 10.52 seconds |
| Started | Sep 18 09:26:22 PM UTC 24 |
| Finished | Sep 18 09:26:33 PM UTC 24 |
| Peak memory | 229200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089491051 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1089491051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.4062465887 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 122365477 ps |
| CPU time | 3.85 seconds |
| Started | Sep 18 09:26:20 PM UTC 24 |
| Finished | Sep 18 09:26:25 PM UTC 24 |
| Peak memory | 229824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062465887 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.4062465887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.4289239818 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 2322892884 ps |
| CPU time | 14.82 seconds |
| Started | Sep 18 09:26:22 PM UTC 24 |
| Finished | Sep 18 09:26:38 PM UTC 24 |
| Peak memory | 232000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289239818 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.4289239818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.3299035017 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 1274032037 ps |
| CPU time | 10.42 seconds |
| Started | Sep 18 09:26:22 PM UTC 24 |
| Finished | Sep 18 09:26:33 PM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299035017 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_to ken_digest.3299035017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.4278206216 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 1619679933 ps |
| CPU time | 25.67 seconds |
| Started | Sep 18 09:26:22 PM UTC 24 |
| Finished | Sep 18 09:26:49 PM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278206216 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token _mux.4278206216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.3893821220 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 1077505531 ps |
| CPU time | 11.9 seconds |
| Started | Sep 18 09:26:22 PM UTC 24 |
| Finished | Sep 18 09:26:35 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893821220 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.3893821220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.3768874001 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 23935942 ps |
| CPU time | 1.92 seconds |
| Started | Sep 18 09:26:18 PM UTC 24 |
| Finished | Sep 18 09:26:20 PM UTC 24 |
| Peak memory | 222008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768874001 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3768874001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.3987063087 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 650055439 ps |
| CPU time | 21.56 seconds |
| Started | Sep 18 09:26:20 PM UTC 24 |
| Finished | Sep 18 09:26:43 PM UTC 24 |
| Peak memory | 262352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987063087 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3987063087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.431300414 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 1070684185 ps |
| CPU time | 8.57 seconds |
| Started | Sep 18 09:26:20 PM UTC 24 |
| Finished | Sep 18 09:26:30 PM UTC 24 |
| Peak memory | 262612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431300414 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.431300414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.3657768827 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 194895572371 ps |
| CPU time | 603.75 seconds |
| Started | Sep 18 09:26:23 PM UTC 24 |
| Finished | Sep 18 09:36:35 PM UTC 24 |
| Peak memory | 262464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3657768827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 43.lc_ctrl_stress_all.3657768827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.829564194 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 3202069216 ps |
| CPU time | 76.07 seconds |
| Started | Sep 18 09:26:23 PM UTC 24 |
| Finished | Sep 18 09:27:41 PM UTC 24 |
| Peak memory | 272776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829564194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.829564194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1116124517 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 104839432 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 09:26:20 PM UTC 24 |
| Finished | Sep 18 09:26:22 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116124517 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43 .lc_ctrl_volatile_unlock_smoke.1116124517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.2621916949 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 41861022 ps |
| CPU time | 1.36 seconds |
| Started | Sep 18 09:26:31 PM UTC 24 |
| Finished | Sep 18 09:26:33 PM UTC 24 |
| Peak memory | 217904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621916949 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2621916949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.1986775377 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 315141992 ps |
| CPU time | 18.47 seconds |
| Started | Sep 18 09:26:26 PM UTC 24 |
| Finished | Sep 18 09:26:46 PM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986775377 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1986775377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.2805078938 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 1458142611 ps |
| CPU time | 5.39 seconds |
| Started | Sep 18 09:26:28 PM UTC 24 |
| Finished | Sep 18 09:26:34 PM UTC 24 |
| Peak memory | 229020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805078938 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2805078938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.1745426323 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 163277816 ps |
| CPU time | 3.95 seconds |
| Started | Sep 18 09:26:26 PM UTC 24 |
| Finished | Sep 18 09:26:31 PM UTC 24 |
| Peak memory | 229964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745426323 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1745426323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.3225866081 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 678472187 ps |
| CPU time | 13.59 seconds |
| Started | Sep 18 09:26:28 PM UTC 24 |
| Finished | Sep 18 09:26:43 PM UTC 24 |
| Peak memory | 231728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225866081 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3225866081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2057458941 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 242802065 ps |
| CPU time | 9.83 seconds |
| Started | Sep 18 09:26:29 PM UTC 24 |
| Finished | Sep 18 09:26:40 PM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057458941 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_to ken_digest.2057458941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.3976214907 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1372663881 ps |
| CPU time | 9.29 seconds |
| Started | Sep 18 09:26:28 PM UTC 24 |
| Finished | Sep 18 09:26:38 PM UTC 24 |
| Peak memory | 230140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976214907 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token _mux.3976214907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.3937596477 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 808225871 ps |
| CPU time | 8.56 seconds |
| Started | Sep 18 09:26:26 PM UTC 24 |
| Finished | Sep 18 09:26:36 PM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937596477 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3937596477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.840126325 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 630103100 ps |
| CPU time | 3.89 seconds |
| Started | Sep 18 09:26:23 PM UTC 24 |
| Finished | Sep 18 09:26:28 PM UTC 24 |
| Peak memory | 225464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840126325 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.840126325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.1890594855 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1020026278 ps |
| CPU time | 22.48 seconds |
| Started | Sep 18 09:26:25 PM UTC 24 |
| Finished | Sep 18 09:26:49 PM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890594855 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1890594855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.646272904 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 397561124 ps |
| CPU time | 12.82 seconds |
| Started | Sep 18 09:26:25 PM UTC 24 |
| Finished | Sep 18 09:26:39 PM UTC 24 |
| Peak memory | 262276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646272904 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.646272904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.1282018651 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 14144299835 ps |
| CPU time | 107.93 seconds |
| Started | Sep 18 09:26:29 PM UTC 24 |
| Finished | Sep 18 09:28:19 PM UTC 24 |
| Peak memory | 295436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1282018651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 44.lc_ctrl_stress_all.1282018651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.334572777 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 62490743 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 09:26:25 PM UTC 24 |
| Finished | Sep 18 09:26:27 PM UTC 24 |
| Peak memory | 220196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334572777 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44. lc_ctrl_volatile_unlock_smoke.334572777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.3335516630 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 48121219 ps |
| CPU time | 1.24 seconds |
| Started | Sep 18 09:26:36 PM UTC 24 |
| Finished | Sep 18 09:26:38 PM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335516630 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3335516630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.1771568158 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 866088329 ps |
| CPU time | 11.17 seconds |
| Started | Sep 18 09:26:33 PM UTC 24 |
| Finished | Sep 18 09:26:46 PM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771568158 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1771568158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.2431434156 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 2542026962 ps |
| CPU time | 8.59 seconds |
| Started | Sep 18 09:26:35 PM UTC 24 |
| Finished | Sep 18 09:26:45 PM UTC 24 |
| Peak memory | 229804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431434156 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2431434156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.898103350 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 224561389 ps |
| CPU time | 2.42 seconds |
| Started | Sep 18 09:26:33 PM UTC 24 |
| Finished | Sep 18 09:26:37 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898103350 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.898103350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.1350824633 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 769683047 ps |
| CPU time | 8.87 seconds |
| Started | Sep 18 09:26:35 PM UTC 24 |
| Finished | Sep 18 09:26:45 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350824633 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1350824633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.2847625315 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 246034876 ps |
| CPU time | 10.21 seconds |
| Started | Sep 18 09:26:35 PM UTC 24 |
| Finished | Sep 18 09:26:47 PM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847625315 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_to ken_digest.2847625315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.2198438370 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 545550243 ps |
| CPU time | 22.79 seconds |
| Started | Sep 18 09:26:35 PM UTC 24 |
| Finished | Sep 18 09:26:59 PM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198438370 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token _mux.2198438370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.2055664705 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 1057000044 ps |
| CPU time | 9.63 seconds |
| Started | Sep 18 09:26:35 PM UTC 24 |
| Finished | Sep 18 09:26:46 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055664705 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2055664705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.2032979354 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 99348844 ps |
| CPU time | 2.39 seconds |
| Started | Sep 18 09:26:32 PM UTC 24 |
| Finished | Sep 18 09:26:35 PM UTC 24 |
| Peak memory | 223736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032979354 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2032979354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.4004970538 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 965351269 ps |
| CPU time | 23.82 seconds |
| Started | Sep 18 09:26:33 PM UTC 24 |
| Finished | Sep 18 09:26:58 PM UTC 24 |
| Peak memory | 260236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004970538 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.4004970538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.3681810789 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 113477002 ps |
| CPU time | 11.54 seconds |
| Started | Sep 18 09:26:33 PM UTC 24 |
| Finished | Sep 18 09:26:46 PM UTC 24 |
| Peak memory | 262404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681810789 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3681810789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.1238520150 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 5232304693 ps |
| CPU time | 38.88 seconds |
| Started | Sep 18 09:26:35 PM UTC 24 |
| Finished | Sep 18 09:27:16 PM UTC 24 |
| Peak memory | 262860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1238520150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 45.lc_ctrl_stress_all.1238520150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2519082119 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 5970955128 ps |
| CPU time | 39.59 seconds |
| Started | Sep 18 09:26:35 PM UTC 24 |
| Finished | Sep 18 09:27:17 PM UTC 24 |
| Peak memory | 237684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519082119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2519082119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3550690502 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 41664715 ps |
| CPU time | 0.84 seconds |
| Started | Sep 18 09:26:33 PM UTC 24 |
| Finished | Sep 18 09:26:35 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550690502 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45 .lc_ctrl_volatile_unlock_smoke.3550690502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.3128515472 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 75021783 ps |
| CPU time | 1.8 seconds |
| Started | Sep 18 09:26:41 PM UTC 24 |
| Finished | Sep 18 09:26:44 PM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128515472 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3128515472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.2218533649 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 730683373 ps |
| CPU time | 9.57 seconds |
| Started | Sep 18 09:26:37 PM UTC 24 |
| Finished | Sep 18 09:26:48 PM UTC 24 |
| Peak memory | 229840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218533649 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2218533649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.956053759 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 757916316 ps |
| CPU time | 3.64 seconds |
| Started | Sep 18 09:26:38 PM UTC 24 |
| Finished | Sep 18 09:26:43 PM UTC 24 |
| Peak memory | 228720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956053759 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.956053759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.1052324889 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 120972157 ps |
| CPU time | 3.28 seconds |
| Started | Sep 18 09:26:37 PM UTC 24 |
| Finished | Sep 18 09:26:41 PM UTC 24 |
| Peak memory | 233920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052324889 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1052324889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.1257953700 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 775514536 ps |
| CPU time | 17.34 seconds |
| Started | Sep 18 09:26:38 PM UTC 24 |
| Finished | Sep 18 09:26:57 PM UTC 24 |
| Peak memory | 231868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257953700 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1257953700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.3088326724 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 323519766 ps |
| CPU time | 10.56 seconds |
| Started | Sep 18 09:26:38 PM UTC 24 |
| Finished | Sep 18 09:26:50 PM UTC 24 |
| Peak memory | 229828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088326724 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_to ken_digest.3088326724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.3383632669 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 524700333 ps |
| CPU time | 12.21 seconds |
| Started | Sep 18 09:26:38 PM UTC 24 |
| Finished | Sep 18 09:26:52 PM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383632669 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token _mux.3383632669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.2600560559 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 561048672 ps |
| CPU time | 7.65 seconds |
| Started | Sep 18 09:26:38 PM UTC 24 |
| Finished | Sep 18 09:26:47 PM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600560559 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2600560559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.3443516631 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 256580235 ps |
| CPU time | 4.51 seconds |
| Started | Sep 18 09:26:36 PM UTC 24 |
| Finished | Sep 18 09:26:41 PM UTC 24 |
| Peak memory | 225452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443516631 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3443516631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.1012404300 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 686995138 ps |
| CPU time | 19.01 seconds |
| Started | Sep 18 09:26:37 PM UTC 24 |
| Finished | Sep 18 09:26:57 PM UTC 24 |
| Peak memory | 262488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012404300 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1012404300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.4102247278 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 287642322 ps |
| CPU time | 10.53 seconds |
| Started | Sep 18 09:26:37 PM UTC 24 |
| Finished | Sep 18 09:26:48 PM UTC 24 |
| Peak memory | 260292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102247278 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.4102247278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.66687393 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 71191583057 ps |
| CPU time | 185.11 seconds |
| Started | Sep 18 09:26:40 PM UTC 24 |
| Finished | Sep 18 09:29:48 PM UTC 24 |
| Peak memory | 301416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=66687393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 46.lc_ctrl_stress_all.66687393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.804718057 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 43089763 ps |
| CPU time | 1.13 seconds |
| Started | Sep 18 09:26:36 PM UTC 24 |
| Finished | Sep 18 09:26:38 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804718057 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46. lc_ctrl_volatile_unlock_smoke.804718057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.3161261609 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 58601080 ps |
| CPU time | 0.97 seconds |
| Started | Sep 18 09:26:48 PM UTC 24 |
| Finished | Sep 18 09:26:50 PM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161261609 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.3161261609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.2949338559 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 502798127 ps |
| CPU time | 11.56 seconds |
| Started | Sep 18 09:26:44 PM UTC 24 |
| Finished | Sep 18 09:26:56 PM UTC 24 |
| Peak memory | 229768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949338559 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2949338559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.191817737 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 2972854773 ps |
| CPU time | 17.3 seconds |
| Started | Sep 18 09:26:46 PM UTC 24 |
| Finished | Sep 18 09:27:04 PM UTC 24 |
| Peak memory | 229272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191817737 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.191817737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.4192642370 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 40731596 ps |
| CPU time | 3.14 seconds |
| Started | Sep 18 09:26:44 PM UTC 24 |
| Finished | Sep 18 09:26:48 PM UTC 24 |
| Peak memory | 229904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192642370 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.4192642370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.3260904787 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 368871592 ps |
| CPU time | 12.95 seconds |
| Started | Sep 18 09:26:46 PM UTC 24 |
| Finished | Sep 18 09:27:00 PM UTC 24 |
| Peak memory | 237828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260904787 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3260904787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.1687844503 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 179869204 ps |
| CPU time | 8.34 seconds |
| Started | Sep 18 09:26:46 PM UTC 24 |
| Finished | Sep 18 09:26:55 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687844503 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_to ken_digest.1687844503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.1276866672 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 4343728461 ps |
| CPU time | 7.88 seconds |
| Started | Sep 18 09:26:46 PM UTC 24 |
| Finished | Sep 18 09:26:55 PM UTC 24 |
| Peak memory | 230268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276866672 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token _mux.1276866672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.3387069370 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 690368686 ps |
| CPU time | 12.55 seconds |
| Started | Sep 18 09:26:45 PM UTC 24 |
| Finished | Sep 18 09:26:58 PM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387069370 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3387069370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.3087953708 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 49432784 ps |
| CPU time | 2.96 seconds |
| Started | Sep 18 09:26:41 PM UTC 24 |
| Finished | Sep 18 09:26:45 PM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087953708 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3087953708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.2603887810 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 403619904 ps |
| CPU time | 19.64 seconds |
| Started | Sep 18 09:26:42 PM UTC 24 |
| Finished | Sep 18 09:27:03 PM UTC 24 |
| Peak memory | 262356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603887810 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2603887810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.3129279778 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 113561830 ps |
| CPU time | 8.25 seconds |
| Started | Sep 18 09:26:43 PM UTC 24 |
| Finished | Sep 18 09:26:53 PM UTC 24 |
| Peak memory | 262416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129279778 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3129279778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.3579068475 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 26621254869 ps |
| CPU time | 532.48 seconds |
| Started | Sep 18 09:26:48 PM UTC 24 |
| Finished | Sep 18 09:35:47 PM UTC 24 |
| Peak memory | 295228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3579068475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 47.lc_ctrl_stress_all.3579068475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2739069394 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 14022080 ps |
| CPU time | 1.5 seconds |
| Started | Sep 18 09:26:42 PM UTC 24 |
| Finished | Sep 18 09:26:45 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739069394 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47 .lc_ctrl_volatile_unlock_smoke.2739069394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.3584684590 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 21331386 ps |
| CPU time | 1.33 seconds |
| Started | Sep 18 09:26:52 PM UTC 24 |
| Finished | Sep 18 09:26:55 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584684590 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3584684590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.2103162965 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 836282463 ps |
| CPU time | 8.38 seconds |
| Started | Sep 18 09:26:49 PM UTC 24 |
| Finished | Sep 18 09:26:59 PM UTC 24 |
| Peak memory | 230096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103162965 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2103162965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.1091617842 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 5344086704 ps |
| CPU time | 6.52 seconds |
| Started | Sep 18 09:26:49 PM UTC 24 |
| Finished | Sep 18 09:26:57 PM UTC 24 |
| Peak memory | 229372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091617842 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1091617842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.130382323 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 39276176 ps |
| CPU time | 2.31 seconds |
| Started | Sep 18 09:26:49 PM UTC 24 |
| Finished | Sep 18 09:26:53 PM UTC 24 |
| Peak memory | 233784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130382323 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.130382323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.727042477 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 895649759 ps |
| CPU time | 9.02 seconds |
| Started | Sep 18 09:26:51 PM UTC 24 |
| Finished | Sep 18 09:27:01 PM UTC 24 |
| Peak memory | 229828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727042477 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.727042477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.4163508239 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 254084521 ps |
| CPU time | 10.42 seconds |
| Started | Sep 18 09:26:51 PM UTC 24 |
| Finished | Sep 18 09:27:02 PM UTC 24 |
| Peak memory | 237500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163508239 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_to ken_digest.4163508239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.3465133902 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 491999508 ps |
| CPU time | 11.91 seconds |
| Started | Sep 18 09:26:51 PM UTC 24 |
| Finished | Sep 18 09:27:04 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465133902 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token _mux.3465133902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.1624896498 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 829611125 ps |
| CPU time | 9.45 seconds |
| Started | Sep 18 09:26:49 PM UTC 24 |
| Finished | Sep 18 09:27:00 PM UTC 24 |
| Peak memory | 229760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624896498 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1624896498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.4040033635 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 149744445 ps |
| CPU time | 2.81 seconds |
| Started | Sep 18 09:26:48 PM UTC 24 |
| Finished | Sep 18 09:26:52 PM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040033635 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.4040033635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.2843633315 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 1451027103 ps |
| CPU time | 20.74 seconds |
| Started | Sep 18 09:26:48 PM UTC 24 |
| Finished | Sep 18 09:27:10 PM UTC 24 |
| Peak memory | 262820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843633315 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2843633315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.490188269 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 921922216 ps |
| CPU time | 6.89 seconds |
| Started | Sep 18 09:26:49 PM UTC 24 |
| Finished | Sep 18 09:26:57 PM UTC 24 |
| Peak memory | 262276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490188269 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.490188269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.2531879827 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 22127944346 ps |
| CPU time | 111.34 seconds |
| Started | Sep 18 09:26:51 PM UTC 24 |
| Finished | Sep 18 09:28:44 PM UTC 24 |
| Peak memory | 293268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2531879827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 48.lc_ctrl_stress_all.2531879827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2975465621 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 9694298666 ps |
| CPU time | 96.8 seconds |
| Started | Sep 18 09:26:52 PM UTC 24 |
| Finished | Sep 18 09:28:31 PM UTC 24 |
| Peak memory | 295720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975465621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.2975465621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1141384470 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 12538696 ps |
| CPU time | 1.6 seconds |
| Started | Sep 18 09:26:48 PM UTC 24 |
| Finished | Sep 18 09:26:50 PM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141384470 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48 .lc_ctrl_volatile_unlock_smoke.1141384470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.134306487 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 40929970 ps |
| CPU time | 1.43 seconds |
| Started | Sep 18 09:26:57 PM UTC 24 |
| Finished | Sep 18 09:27:00 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134306487 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.134306487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.971756024 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 347267209 ps |
| CPU time | 13.95 seconds |
| Started | Sep 18 09:26:54 PM UTC 24 |
| Finished | Sep 18 09:27:09 PM UTC 24 |
| Peak memory | 230020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971756024 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.971756024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.1563603369 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 259243197 ps |
| CPU time | 2.29 seconds |
| Started | Sep 18 09:26:56 PM UTC 24 |
| Finished | Sep 18 09:26:59 PM UTC 24 |
| Peak memory | 228444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563603369 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1563603369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.2667719225 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 75525702 ps |
| CPU time | 3.76 seconds |
| Started | Sep 18 09:26:54 PM UTC 24 |
| Finished | Sep 18 09:26:59 PM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667719225 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2667719225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.2451539015 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 3620949248 ps |
| CPU time | 15.28 seconds |
| Started | Sep 18 09:26:56 PM UTC 24 |
| Finished | Sep 18 09:27:12 PM UTC 24 |
| Peak memory | 231692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451539015 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2451539015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.2089645468 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 385684764 ps |
| CPU time | 13.45 seconds |
| Started | Sep 18 09:26:56 PM UTC 24 |
| Finished | Sep 18 09:27:10 PM UTC 24 |
| Peak memory | 230076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089645468 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_to ken_digest.2089645468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.1031284040 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 215866947 ps |
| CPU time | 6.93 seconds |
| Started | Sep 18 09:26:56 PM UTC 24 |
| Finished | Sep 18 09:27:04 PM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031284040 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token _mux.1031284040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.3038423502 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 225583188 ps |
| CPU time | 6.8 seconds |
| Started | Sep 18 09:26:56 PM UTC 24 |
| Finished | Sep 18 09:27:03 PM UTC 24 |
| Peak memory | 229840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038423502 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3038423502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.997239086 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 18989483 ps |
| CPU time | 1.82 seconds |
| Started | Sep 18 09:26:52 PM UTC 24 |
| Finished | Sep 18 09:26:55 PM UTC 24 |
| Peak memory | 227996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997239086 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.997239086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.810372485 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 321339212 ps |
| CPU time | 23.78 seconds |
| Started | Sep 18 09:26:54 PM UTC 24 |
| Finished | Sep 18 09:27:19 PM UTC 24 |
| Peak memory | 262416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810372485 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.810372485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.744745924 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 71260739 ps |
| CPU time | 7.64 seconds |
| Started | Sep 18 09:26:54 PM UTC 24 |
| Finished | Sep 18 09:27:03 PM UTC 24 |
| Peak memory | 260440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744745924 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.744745924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.609916076 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 22964895909 ps |
| CPU time | 117.6 seconds |
| Started | Sep 18 09:26:56 PM UTC 24 |
| Finished | Sep 18 09:28:56 PM UTC 24 |
| Peak memory | 262568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=609916076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 49.lc_ctrl_stress_all.609916076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2542970422 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 36480741 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 09:26:52 PM UTC 24 |
| Finished | Sep 18 09:26:55 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542970422 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49 .lc_ctrl_volatile_unlock_smoke.2542970422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.1718527054 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 16210115 ps |
| CPU time | 1.46 seconds |
| Started | Sep 18 09:21:07 PM UTC 24 |
| Finished | Sep 18 09:21:10 PM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718527054 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1718527054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.442496383 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 13358997 ps |
| CPU time | 1.29 seconds |
| Started | Sep 18 09:20:57 PM UTC 24 |
| Finished | Sep 18 09:21:00 PM UTC 24 |
| Peak memory | 218580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442496383 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.442496383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.55433455 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 581428965 ps |
| CPU time | 20.37 seconds |
| Started | Sep 18 09:20:56 PM UTC 24 |
| Finished | Sep 18 09:21:18 PM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55433455 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.55433455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.719187337 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1536020984 ps |
| CPU time | 7.7 seconds |
| Started | Sep 18 09:21:01 PM UTC 24 |
| Finished | Sep 18 09:21:10 PM UTC 24 |
| Peak memory | 228772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719187337 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.719187337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.1797879228 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8571245809 ps |
| CPU time | 37.83 seconds |
| Started | Sep 18 09:21:00 PM UTC 24 |
| Finished | Sep 18 09:21:39 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797879228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jt ag_errors.1797879228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.1127374095 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 406397885 ps |
| CPU time | 10.39 seconds |
| Started | Sep 18 09:21:01 PM UTC 24 |
| Finished | Sep 18 09:21:13 PM UTC 24 |
| Peak memory | 229376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127374095 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_prior ity.1127374095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.3009684897 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 480259964 ps |
| CPU time | 6.36 seconds |
| Started | Sep 18 09:21:00 PM UTC 24 |
| Finished | Sep 18 09:21:07 PM UTC 24 |
| Peak memory | 233768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009684897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl _jtag_prog_failure.3009684897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3865559614 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 3911305622 ps |
| CPU time | 13.12 seconds |
| Started | Sep 18 09:21:04 PM UTC 24 |
| Finished | Sep 18 09:21:19 PM UTC 24 |
| Peak memory | 229608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865559614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ ctrl_jtag_regwen_during_op.3865559614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.1210773634 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1582179950 ps |
| CPU time | 6.42 seconds |
| Started | Sep 18 09:20:57 PM UTC 24 |
| Finished | Sep 18 09:21:05 PM UTC 24 |
| Peak memory | 223328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210773634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_s moke.1210773634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.2668793373 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 7931585016 ps |
| CPU time | 87.81 seconds |
| Started | Sep 18 09:20:59 PM UTC 24 |
| Finished | Sep 18 09:22:28 PM UTC 24 |
| Peak memory | 285008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668793373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr l_jtag_state_failure.2668793373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1402977099 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 807577747 ps |
| CPU time | 21.09 seconds |
| Started | Sep 18 09:20:59 PM UTC 24 |
| Finished | Sep 18 09:21:21 PM UTC 24 |
| Peak memory | 262284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402977099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ ctrl_jtag_state_post_trans.1402977099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.3754181995 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 43238648 ps |
| CPU time | 3.3 seconds |
| Started | Sep 18 09:20:56 PM UTC 24 |
| Finished | Sep 18 09:21:00 PM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754181995 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3754181995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.133090662 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 622872210 ps |
| CPU time | 16 seconds |
| Started | Sep 18 09:20:57 PM UTC 24 |
| Finished | Sep 18 09:21:14 PM UTC 24 |
| Peak memory | 225108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133090662 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.133090662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.833298039 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1042565527 ps |
| CPU time | 14.27 seconds |
| Started | Sep 18 09:21:05 PM UTC 24 |
| Finished | Sep 18 09:21:20 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833298039 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.833298039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.2602134025 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 626612365 ps |
| CPU time | 12.72 seconds |
| Started | Sep 18 09:21:06 PM UTC 24 |
| Finished | Sep 18 09:21:19 PM UTC 24 |
| Peak memory | 230136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602134025 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_tok en_digest.2602134025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.4078647038 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 486149999 ps |
| CPU time | 11.33 seconds |
| Started | Sep 18 09:21:05 PM UTC 24 |
| Finished | Sep 18 09:21:17 PM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078647038 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_ mux.4078647038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.1938964766 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 270831765 ps |
| CPU time | 11.6 seconds |
| Started | Sep 18 09:20:57 PM UTC 24 |
| Finished | Sep 18 09:21:10 PM UTC 24 |
| Peak memory | 229612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938964766 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1938964766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.197774439 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 34947325 ps |
| CPU time | 2.25 seconds |
| Started | Sep 18 09:20:53 PM UTC 24 |
| Finished | Sep 18 09:20:57 PM UTC 24 |
| Peak memory | 223480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197774439 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.197774439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.780856341 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 645840005 ps |
| CPU time | 26.95 seconds |
| Started | Sep 18 09:20:55 PM UTC 24 |
| Finished | Sep 18 09:21:23 PM UTC 24 |
| Peak memory | 262420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780856341 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.780856341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.4122850597 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 190509794 ps |
| CPU time | 8.36 seconds |
| Started | Sep 18 09:20:56 PM UTC 24 |
| Finished | Sep 18 09:21:05 PM UTC 24 |
| Peak memory | 262356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122850597 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.4122850597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.2898003595 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 239296595496 ps |
| CPU time | 578.83 seconds |
| Started | Sep 18 09:21:07 PM UTC 24 |
| Finished | Sep 18 09:30:53 PM UTC 24 |
| Peak memory | 237556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2898003595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 5.lc_ctrl_stress_all.2898003595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.738840143 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 43228520 ps |
| CPU time | 1.26 seconds |
| Started | Sep 18 09:20:53 PM UTC 24 |
| Finished | Sep 18 09:20:56 PM UTC 24 |
| Peak memory | 222420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738840143 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.l c_ctrl_volatile_unlock_smoke.738840143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.1003127100 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 45915278 ps |
| CPU time | 1.19 seconds |
| Started | Sep 18 09:21:24 PM UTC 24 |
| Finished | Sep 18 09:21:27 PM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003127100 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1003127100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.3558553489 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 13953552 ps |
| CPU time | 1.56 seconds |
| Started | Sep 18 09:21:15 PM UTC 24 |
| Finished | Sep 18 09:21:18 PM UTC 24 |
| Peak memory | 217748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558553489 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3558553489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.1029531486 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 328080518 ps |
| CPU time | 17.58 seconds |
| Started | Sep 18 09:21:12 PM UTC 24 |
| Finished | Sep 18 09:21:30 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029531486 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1029531486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.2969675168 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1343630698 ps |
| CPU time | 8.46 seconds |
| Started | Sep 18 09:21:19 PM UTC 24 |
| Finished | Sep 18 09:21:29 PM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969675168 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2969675168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.2350624924 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1319686755 ps |
| CPU time | 28.74 seconds |
| Started | Sep 18 09:21:19 PM UTC 24 |
| Finished | Sep 18 09:21:49 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350624924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jt ag_errors.2350624924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.2809671373 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 672589377 ps |
| CPU time | 5.72 seconds |
| Started | Sep 18 09:21:20 PM UTC 24 |
| Finished | Sep 18 09:21:27 PM UTC 24 |
| Peak memory | 229500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809671373 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_prior ity.2809671373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3209669925 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2625431956 ps |
| CPU time | 19.93 seconds |
| Started | Sep 18 09:21:19 PM UTC 24 |
| Finished | Sep 18 09:21:40 PM UTC 24 |
| Peak memory | 237536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209669925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl _jtag_prog_failure.3209669925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.203551350 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 4919919710 ps |
| CPU time | 17.46 seconds |
| Started | Sep 18 09:21:21 PM UTC 24 |
| Finished | Sep 18 09:21:40 PM UTC 24 |
| Peak memory | 223452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203551350 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_c trl_jtag_regwen_during_op.203551350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.1314417289 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 298646639 ps |
| CPU time | 9.93 seconds |
| Started | Sep 18 09:21:16 PM UTC 24 |
| Finished | Sep 18 09:21:27 PM UTC 24 |
| Peak memory | 223400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314417289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_s moke.1314417289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.3972575257 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 8543704248 ps |
| CPU time | 64.05 seconds |
| Started | Sep 18 09:21:16 PM UTC 24 |
| Finished | Sep 18 09:22:22 PM UTC 24 |
| Peak memory | 264776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972575257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr l_jtag_state_failure.3972575257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.459611312 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1906530790 ps |
| CPU time | 12.97 seconds |
| Started | Sep 18 09:21:18 PM UTC 24 |
| Finished | Sep 18 09:21:33 PM UTC 24 |
| Peak memory | 260104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459611312 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_c trl_jtag_state_post_trans.459611312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.39036503 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 268458197 ps |
| CPU time | 3.98 seconds |
| Started | Sep 18 09:21:11 PM UTC 24 |
| Finished | Sep 18 09:21:16 PM UTC 24 |
| Peak memory | 233924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39036503 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.39036503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.1208807668 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 497635111 ps |
| CPU time | 9.39 seconds |
| Started | Sep 18 09:21:15 PM UTC 24 |
| Finished | Sep 18 09:21:25 PM UTC 24 |
| Peak memory | 223468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208807668 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1208807668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3130291862 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 278754298 ps |
| CPU time | 12.22 seconds |
| Started | Sep 18 09:21:21 PM UTC 24 |
| Finished | Sep 18 09:21:34 PM UTC 24 |
| Peak memory | 237500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130291862 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3130291862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.1811868850 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 456339370 ps |
| CPU time | 11.24 seconds |
| Started | Sep 18 09:21:22 PM UTC 24 |
| Finished | Sep 18 09:21:34 PM UTC 24 |
| Peak memory | 237424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811868850 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_tok en_digest.1811868850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.4181614836 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 189775929 ps |
| CPU time | 8.76 seconds |
| Started | Sep 18 09:21:22 PM UTC 24 |
| Finished | Sep 18 09:21:32 PM UTC 24 |
| Peak memory | 229828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181614836 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_ mux.4181614836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.461144229 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 519072909 ps |
| CPU time | 11.32 seconds |
| Started | Sep 18 09:21:14 PM UTC 24 |
| Finished | Sep 18 09:21:26 PM UTC 24 |
| Peak memory | 237764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461144229 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.461144229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2861141134 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 104248849 ps |
| CPU time | 7.61 seconds |
| Started | Sep 18 09:21:08 PM UTC 24 |
| Finished | Sep 18 09:21:17 PM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861141134 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2861141134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.2179408166 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1242883847 ps |
| CPU time | 33.46 seconds |
| Started | Sep 18 09:21:11 PM UTC 24 |
| Finished | Sep 18 09:21:45 PM UTC 24 |
| Peak memory | 262420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179408166 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2179408166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.2862506709 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 76475748 ps |
| CPU time | 10.9 seconds |
| Started | Sep 18 09:21:11 PM UTC 24 |
| Finished | Sep 18 09:21:23 PM UTC 24 |
| Peak memory | 255936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862506709 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2862506709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.925519719 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 581497466 ps |
| CPU time | 31.5 seconds |
| Started | Sep 18 09:21:24 PM UTC 24 |
| Finished | Sep 18 09:21:57 PM UTC 24 |
| Peak memory | 262544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=925519719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 6.lc_ctrl_stress_all.925519719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.4047071217 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 256648573 ps |
| CPU time | 7.42 seconds |
| Started | Sep 18 09:21:24 PM UTC 24 |
| Finished | Sep 18 09:21:33 PM UTC 24 |
| Peak memory | 237564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047071217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.4047071217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2150713703 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 11151905 ps |
| CPU time | 0.96 seconds |
| Started | Sep 18 09:21:08 PM UTC 24 |
| Finished | Sep 18 09:21:10 PM UTC 24 |
| Peak memory | 217300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150713703 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6. lc_ctrl_volatile_unlock_smoke.2150713703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.3715207781 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 15575429 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 09:21:37 PM UTC 24 |
| Finished | Sep 18 09:21:40 PM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715207781 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3715207781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.2234119521 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 12018827 ps |
| CPU time | 1.27 seconds |
| Started | Sep 18 09:21:29 PM UTC 24 |
| Finished | Sep 18 09:21:32 PM UTC 24 |
| Peak memory | 217912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234119521 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2234119521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.1220615517 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 709280635 ps |
| CPU time | 8.98 seconds |
| Started | Sep 18 09:21:28 PM UTC 24 |
| Finished | Sep 18 09:21:38 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220615517 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1220615517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1902342309 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 32714678 ps |
| CPU time | 1.9 seconds |
| Started | Sep 18 09:21:34 PM UTC 24 |
| Finished | Sep 18 09:21:37 PM UTC 24 |
| Peak memory | 226668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902342309 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1902342309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.1207240345 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 5719473955 ps |
| CPU time | 47.76 seconds |
| Started | Sep 18 09:21:33 PM UTC 24 |
| Finished | Sep 18 09:22:23 PM UTC 24 |
| Peak memory | 231860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207240345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jt ag_errors.1207240345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.4252227915 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 909624919 ps |
| CPU time | 6.17 seconds |
| Started | Sep 18 09:21:34 PM UTC 24 |
| Finished | Sep 18 09:21:41 PM UTC 24 |
| Peak memory | 228992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252227915 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_prior ity.4252227915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1016602091 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 367378657 ps |
| CPU time | 11.63 seconds |
| Started | Sep 18 09:21:32 PM UTC 24 |
| Finished | Sep 18 09:21:45 PM UTC 24 |
| Peak memory | 235756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016602091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl _jtag_prog_failure.1016602091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.673299521 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2256610891 ps |
| CPU time | 13.6 seconds |
| Started | Sep 18 09:21:34 PM UTC 24 |
| Finished | Sep 18 09:21:49 PM UTC 24 |
| Peak memory | 229600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673299521 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_c trl_jtag_regwen_during_op.673299521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.1108185411 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 63446399 ps |
| CPU time | 3.72 seconds |
| Started | Sep 18 09:21:31 PM UTC 24 |
| Finished | Sep 18 09:21:36 PM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108185411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_s moke.1108185411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.244613823 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 11346236284 ps |
| CPU time | 59.46 seconds |
| Started | Sep 18 09:21:32 PM UTC 24 |
| Finished | Sep 18 09:22:34 PM UTC 24 |
| Peak memory | 291072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244613823 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl _jtag_state_failure.244613823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.1435046322 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 456328357 ps |
| CPU time | 20.02 seconds |
| Started | Sep 18 09:21:32 PM UTC 24 |
| Finished | Sep 18 09:21:54 PM UTC 24 |
| Peak memory | 262620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435046322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ ctrl_jtag_state_post_trans.1435046322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.2527612346 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 98861469 ps |
| CPU time | 3.16 seconds |
| Started | Sep 18 09:21:28 PM UTC 24 |
| Finished | Sep 18 09:21:33 PM UTC 24 |
| Peak memory | 230036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527612346 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.2527612346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.3568541152 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 791972101 ps |
| CPU time | 13.13 seconds |
| Started | Sep 18 09:21:29 PM UTC 24 |
| Finished | Sep 18 09:21:44 PM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568541152 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3568541152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.2530979948 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 658287284 ps |
| CPU time | 26.7 seconds |
| Started | Sep 18 09:21:34 PM UTC 24 |
| Finished | Sep 18 09:22:02 PM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530979948 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2530979948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.4130009658 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 285347633 ps |
| CPU time | 14.34 seconds |
| Started | Sep 18 09:21:35 PM UTC 24 |
| Finished | Sep 18 09:21:51 PM UTC 24 |
| Peak memory | 237752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130009658 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_tok en_digest.4130009658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.3920720096 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 807697842 ps |
| CPU time | 26.25 seconds |
| Started | Sep 18 09:21:35 PM UTC 24 |
| Finished | Sep 18 09:22:03 PM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920720096 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_ mux.3920720096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1057308621 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1194695895 ps |
| CPU time | 11.48 seconds |
| Started | Sep 18 09:21:29 PM UTC 24 |
| Finished | Sep 18 09:21:42 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057308621 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1057308621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3735852205 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 203650831 ps |
| CPU time | 2.84 seconds |
| Started | Sep 18 09:21:24 PM UTC 24 |
| Finished | Sep 18 09:21:29 PM UTC 24 |
| Peak memory | 225532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735852205 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3735852205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.466133104 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 970539022 ps |
| CPU time | 21.14 seconds |
| Started | Sep 18 09:21:27 PM UTC 24 |
| Finished | Sep 18 09:21:50 PM UTC 24 |
| Peak memory | 262484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466133104 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.466133104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.1781152175 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 52975801 ps |
| CPU time | 8.22 seconds |
| Started | Sep 18 09:21:27 PM UTC 24 |
| Finished | Sep 18 09:21:37 PM UTC 24 |
| Peak memory | 262276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781152175 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1781152175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.3882717428 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 12397414608 ps |
| CPU time | 60.91 seconds |
| Started | Sep 18 09:21:36 PM UTC 24 |
| Finished | Sep 18 09:22:39 PM UTC 24 |
| Peak memory | 262684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3882717428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 7.lc_ctrl_stress_all.3882717428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.944013205 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 10726426009 ps |
| CPU time | 64 seconds |
| Started | Sep 18 09:21:37 PM UTC 24 |
| Finished | Sep 18 09:22:43 PM UTC 24 |
| Peak memory | 281192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944013205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.944013205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.988211719 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 33362915 ps |
| CPU time | 1.35 seconds |
| Started | Sep 18 09:21:26 PM UTC 24 |
| Finished | Sep 18 09:21:29 PM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988211719 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.l c_ctrl_volatile_unlock_smoke.988211719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.862082148 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 16966765 ps |
| CPU time | 1.7 seconds |
| Started | Sep 18 09:21:50 PM UTC 24 |
| Finished | Sep 18 09:21:53 PM UTC 24 |
| Peak memory | 217840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862082148 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.862082148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2449607017 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 12991244 ps |
| CPU time | 1.51 seconds |
| Started | Sep 18 09:21:43 PM UTC 24 |
| Finished | Sep 18 09:21:45 PM UTC 24 |
| Peak memory | 217748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449607017 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2449607017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.3799578267 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 693065823 ps |
| CPU time | 14.25 seconds |
| Started | Sep 18 09:21:41 PM UTC 24 |
| Finished | Sep 18 09:21:57 PM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799578267 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3799578267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.3211703839 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1092902862 ps |
| CPU time | 8.31 seconds |
| Started | Sep 18 09:21:46 PM UTC 24 |
| Finished | Sep 18 09:21:56 PM UTC 24 |
| Peak memory | 228980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211703839 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3211703839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.2285255730 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 3965865119 ps |
| CPU time | 69.42 seconds |
| Started | Sep 18 09:21:45 PM UTC 24 |
| Finished | Sep 18 09:22:57 PM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285255730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jt ag_errors.2285255730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.2003421169 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3902628968 ps |
| CPU time | 8.3 seconds |
| Started | Sep 18 09:21:46 PM UTC 24 |
| Finished | Sep 18 09:21:56 PM UTC 24 |
| Peak memory | 229720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003421169 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_prior ity.2003421169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.3791381915 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 291590408 ps |
| CPU time | 3.46 seconds |
| Started | Sep 18 09:21:44 PM UTC 24 |
| Finished | Sep 18 09:21:49 PM UTC 24 |
| Peak memory | 233840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791381915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl _jtag_prog_failure.3791381915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2941030251 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1378534897 ps |
| CPU time | 12.84 seconds |
| Started | Sep 18 09:21:46 PM UTC 24 |
| Finished | Sep 18 09:22:00 PM UTC 24 |
| Peak memory | 229408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941030251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ ctrl_jtag_regwen_during_op.2941030251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.484377753 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 488992854 ps |
| CPU time | 4.05 seconds |
| Started | Sep 18 09:21:43 PM UTC 24 |
| Finished | Sep 18 09:21:48 PM UTC 24 |
| Peak memory | 223420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484377753 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_sm oke.484377753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.1001003446 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 11310177789 ps |
| CPU time | 60.16 seconds |
| Started | Sep 18 09:21:44 PM UTC 24 |
| Finished | Sep 18 09:22:46 PM UTC 24 |
| Peak memory | 289020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001003446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr l_jtag_state_failure.1001003446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.2007376009 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 401919917 ps |
| CPU time | 13.05 seconds |
| Started | Sep 18 09:21:44 PM UTC 24 |
| Finished | Sep 18 09:21:58 PM UTC 24 |
| Peak memory | 262684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007376009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ ctrl_jtag_state_post_trans.2007376009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.3445972551 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 26125744 ps |
| CPU time | 3.03 seconds |
| Started | Sep 18 09:21:41 PM UTC 24 |
| Finished | Sep 18 09:21:46 PM UTC 24 |
| Peak memory | 233928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445972551 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3445972551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.3846965868 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 397823701 ps |
| CPU time | 30 seconds |
| Started | Sep 18 09:21:41 PM UTC 24 |
| Finished | Sep 18 09:22:13 PM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846965868 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3846965868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.975826547 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3022284790 ps |
| CPU time | 14.01 seconds |
| Started | Sep 18 09:21:46 PM UTC 24 |
| Finished | Sep 18 09:22:02 PM UTC 24 |
| Peak memory | 232000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975826547 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.975826547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.3246984029 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 307789340 ps |
| CPU time | 10.11 seconds |
| Started | Sep 18 09:21:50 PM UTC 24 |
| Finished | Sep 18 09:22:01 PM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246984029 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_tok en_digest.3246984029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.550464834 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 535281043 ps |
| CPU time | 8.22 seconds |
| Started | Sep 18 09:21:49 PM UTC 24 |
| Finished | Sep 18 09:21:58 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550464834 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.550464834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.3129308464 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 277642982 ps |
| CPU time | 11.47 seconds |
| Started | Sep 18 09:21:41 PM UTC 24 |
| Finished | Sep 18 09:21:54 PM UTC 24 |
| Peak memory | 229772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129308464 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3129308464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.3572667264 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 55551957 ps |
| CPU time | 2.02 seconds |
| Started | Sep 18 09:21:38 PM UTC 24 |
| Finished | Sep 18 09:21:42 PM UTC 24 |
| Peak memory | 223808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572667264 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3572667264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3112957526 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 240087959 ps |
| CPU time | 25.52 seconds |
| Started | Sep 18 09:21:40 PM UTC 24 |
| Finished | Sep 18 09:22:07 PM UTC 24 |
| Peak memory | 260404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112957526 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3112957526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.2174555025 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 648792296 ps |
| CPU time | 7.12 seconds |
| Started | Sep 18 09:21:40 PM UTC 24 |
| Finished | Sep 18 09:21:49 PM UTC 24 |
| Peak memory | 260300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174555025 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2174555025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.4217313306 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3447451878 ps |
| CPU time | 32.59 seconds |
| Started | Sep 18 09:21:50 PM UTC 24 |
| Finished | Sep 18 09:22:24 PM UTC 24 |
| Peak memory | 258700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4217313306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 8.lc_ctrl_stress_all.4217313306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.232565327 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 11667126 ps |
| CPU time | 1.38 seconds |
| Started | Sep 18 09:21:40 PM UTC 24 |
| Finished | Sep 18 09:21:43 PM UTC 24 |
| Peak memory | 218204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232565327 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.l c_ctrl_volatile_unlock_smoke.232565327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3657226258 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 68990986 ps |
| CPU time | 1.37 seconds |
| Started | Sep 18 09:22:06 PM UTC 24 |
| Finished | Sep 18 09:22:08 PM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657226258 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3657226258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.1418003148 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 52840937 ps |
| CPU time | 1.1 seconds |
| Started | Sep 18 09:21:57 PM UTC 24 |
| Finished | Sep 18 09:21:59 PM UTC 24 |
| Peak memory | 217912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418003148 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1418003148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.1107971003 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 998856430 ps |
| CPU time | 16.57 seconds |
| Started | Sep 18 09:21:55 PM UTC 24 |
| Finished | Sep 18 09:22:12 PM UTC 24 |
| Peak memory | 229756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107971003 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1107971003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.64348207 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4733746186 ps |
| CPU time | 10.5 seconds |
| Started | Sep 18 09:22:00 PM UTC 24 |
| Finished | Sep 18 09:22:11 PM UTC 24 |
| Peak memory | 229404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64348207 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.64348207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.3585114091 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 6588148706 ps |
| CPU time | 50.37 seconds |
| Started | Sep 18 09:21:59 PM UTC 24 |
| Finished | Sep 18 09:22:51 PM UTC 24 |
| Peak memory | 232004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585114091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jt ag_errors.3585114091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.3911300879 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1019704672 ps |
| CPU time | 8.75 seconds |
| Started | Sep 18 09:22:02 PM UTC 24 |
| Finished | Sep 18 09:22:12 PM UTC 24 |
| Peak memory | 229612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911300879 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_prior ity.3911300879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.2577609146 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 596676329 ps |
| CPU time | 15.2 seconds |
| Started | Sep 18 09:21:58 PM UTC 24 |
| Finished | Sep 18 09:22:15 PM UTC 24 |
| Peak memory | 235888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577609146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl _jtag_prog_failure.2577609146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2534348983 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1343089284 ps |
| CPU time | 27.44 seconds |
| Started | Sep 18 09:22:02 PM UTC 24 |
| Finished | Sep 18 09:22:31 PM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534348983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ ctrl_jtag_regwen_during_op.2534348983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.4039640538 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 679522573 ps |
| CPU time | 13.52 seconds |
| Started | Sep 18 09:21:57 PM UTC 24 |
| Finished | Sep 18 09:22:12 PM UTC 24 |
| Peak memory | 223332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039640538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_s moke.4039640538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.3658104359 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 11248710019 ps |
| CPU time | 67.18 seconds |
| Started | Sep 18 09:21:58 PM UTC 24 |
| Finished | Sep 18 09:23:07 PM UTC 24 |
| Peak memory | 295172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658104359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr l_jtag_state_failure.3658104359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1058960179 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 855200617 ps |
| CPU time | 33.73 seconds |
| Started | Sep 18 09:21:58 PM UTC 24 |
| Finished | Sep 18 09:22:33 PM UTC 24 |
| Peak memory | 229956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058960179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ ctrl_jtag_state_post_trans.1058960179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.1038334086 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 205061135 ps |
| CPU time | 5.96 seconds |
| Started | Sep 18 09:21:55 PM UTC 24 |
| Finished | Sep 18 09:22:02 PM UTC 24 |
| Peak memory | 233924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038334086 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1038334086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.4237568990 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 324530736 ps |
| CPU time | 20.78 seconds |
| Started | Sep 18 09:21:56 PM UTC 24 |
| Finished | Sep 18 09:22:18 PM UTC 24 |
| Peak memory | 223392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237568990 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.4237568990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.1947042662 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1265569910 ps |
| CPU time | 15.29 seconds |
| Started | Sep 18 09:22:03 PM UTC 24 |
| Finished | Sep 18 09:22:20 PM UTC 24 |
| Peak memory | 231788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947042662 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1947042662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2652670471 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 1169331201 ps |
| CPU time | 7.02 seconds |
| Started | Sep 18 09:22:03 PM UTC 24 |
| Finished | Sep 18 09:22:11 PM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652670471 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_tok en_digest.2652670471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.1629351637 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1557587988 ps |
| CPU time | 11.63 seconds |
| Started | Sep 18 09:22:03 PM UTC 24 |
| Finished | Sep 18 09:22:16 PM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629351637 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_ mux.1629351637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.2222045834 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 479160052 ps |
| CPU time | 11.45 seconds |
| Started | Sep 18 09:21:56 PM UTC 24 |
| Finished | Sep 18 09:22:08 PM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222045834 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2222045834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.1324673077 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 113821683 ps |
| CPU time | 3.04 seconds |
| Started | Sep 18 09:21:51 PM UTC 24 |
| Finished | Sep 18 09:21:55 PM UTC 24 |
| Peak memory | 223416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324673077 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1324673077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.3210789959 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 811739562 ps |
| CPU time | 25.21 seconds |
| Started | Sep 18 09:21:53 PM UTC 24 |
| Finished | Sep 18 09:22:20 PM UTC 24 |
| Peak memory | 262420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210789959 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3210789959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.1570425121 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 131391099 ps |
| CPU time | 6.54 seconds |
| Started | Sep 18 09:21:55 PM UTC 24 |
| Finished | Sep 18 09:22:02 PM UTC 24 |
| Peak memory | 260140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570425121 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1570425121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.2012875561 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 3230265422 ps |
| CPU time | 80.02 seconds |
| Started | Sep 18 09:22:03 PM UTC 24 |
| Finished | Sep 18 09:23:25 PM UTC 24 |
| Peak memory | 280892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2012875561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 9.lc_ctrl_stress_all.2012875561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.2350430790 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1807561815 ps |
| CPU time | 84.25 seconds |
| Started | Sep 18 09:22:04 PM UTC 24 |
| Finished | Sep 18 09:23:31 PM UTC 24 |
| Peak memory | 262484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350430790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.2350430790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2013662498 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 13400003 ps |
| CPU time | 1.19 seconds |
| Started | Sep 18 09:21:51 PM UTC 24 |
| Finished | Sep 18 09:21:53 PM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013662498 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9. lc_ctrl_volatile_unlock_smoke.2013662498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_volatile_unlock_smoke/latest |
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