| T31 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.2760331571 |
|
|
Oct 09 10:58:01 PM UTC 24 |
Oct 09 10:58:16 PM UTC 24 |
4217181341 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.256672607 |
|
|
Oct 09 10:58:01 PM UTC 24 |
Oct 09 10:58:17 PM UTC 24 |
1959440230 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.3684947929 |
|
|
Oct 09 10:58:08 PM UTC 24 |
Oct 09 10:58:17 PM UTC 24 |
365357171 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.2504194012 |
|
|
Oct 09 10:58:13 PM UTC 24 |
Oct 09 10:58:18 PM UTC 24 |
69833073 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.1464354863 |
|
|
Oct 09 10:58:10 PM UTC 24 |
Oct 09 10:58:19 PM UTC 24 |
270378288 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.2887286949 |
|
|
Oct 09 10:58:11 PM UTC 24 |
Oct 09 10:58:20 PM UTC 24 |
758548587 ps |
| T32 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.1424640799 |
|
|
Oct 09 10:58:10 PM UTC 24 |
Oct 09 10:58:20 PM UTC 24 |
1148216058 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.3590018732 |
|
|
Oct 09 10:57:59 PM UTC 24 |
Oct 09 10:58:20 PM UTC 24 |
989984071 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.3983562736 |
|
|
Oct 09 10:56:39 PM UTC 24 |
Oct 09 10:58:21 PM UTC 24 |
11739995362 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.2692141577 |
|
|
Oct 09 10:58:03 PM UTC 24 |
Oct 09 10:58:21 PM UTC 24 |
959280292 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.3668547923 |
|
|
Oct 09 10:58:08 PM UTC 24 |
Oct 09 10:58:21 PM UTC 24 |
723827779 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.1474352208 |
|
|
Oct 09 10:58:17 PM UTC 24 |
Oct 09 10:58:21 PM UTC 24 |
577521551 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.1036371359 |
|
|
Oct 09 10:58:20 PM UTC 24 |
Oct 09 10:58:22 PM UTC 24 |
43114005 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.4264064726 |
|
|
Oct 09 10:58:21 PM UTC 24 |
Oct 09 10:58:24 PM UTC 24 |
11743600 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.2238334553 |
|
|
Oct 09 10:58:44 PM UTC 24 |
Oct 09 10:58:46 PM UTC 24 |
69559146 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.2996968269 |
|
|
Oct 09 10:58:13 PM UTC 24 |
Oct 09 10:58:25 PM UTC 24 |
57191012 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.1768963477 |
|
|
Oct 09 10:56:32 PM UTC 24 |
Oct 09 10:58:25 PM UTC 24 |
7270377656 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.3849215387 |
|
|
Oct 09 10:58:21 PM UTC 24 |
Oct 09 10:58:25 PM UTC 24 |
39715095 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.2729725280 |
|
|
Oct 09 10:58:00 PM UTC 24 |
Oct 09 10:58:26 PM UTC 24 |
2046712522 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.1745904605 |
|
|
Oct 09 10:57:59 PM UTC 24 |
Oct 09 10:58:26 PM UTC 24 |
328298864 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.3897882796 |
|
|
Oct 09 10:58:16 PM UTC 24 |
Oct 09 10:58:26 PM UTC 24 |
755636630 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.1252841561 |
|
|
Oct 09 10:58:23 PM UTC 24 |
Oct 09 10:58:26 PM UTC 24 |
139808975 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.966403089 |
|
|
Oct 09 10:57:30 PM UTC 24 |
Oct 09 10:58:27 PM UTC 24 |
5541199914 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.75709512 |
|
|
Oct 09 10:58:18 PM UTC 24 |
Oct 09 10:58:27 PM UTC 24 |
927504407 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.1071113962 |
|
|
Oct 09 10:58:18 PM UTC 24 |
Oct 09 10:58:28 PM UTC 24 |
873674073 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.343114979 |
|
|
Oct 09 10:58:10 PM UTC 24 |
Oct 09 10:58:28 PM UTC 24 |
707341171 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.2435877866 |
|
|
Oct 09 10:58:10 PM UTC 24 |
Oct 09 10:58:29 PM UTC 24 |
973133781 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.154840064 |
|
|
Oct 09 10:58:10 PM UTC 24 |
Oct 09 10:58:30 PM UTC 24 |
1820936338 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.1438534589 |
|
|
Oct 09 10:58:23 PM UTC 24 |
Oct 09 10:58:30 PM UTC 24 |
391181282 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.2694779930 |
|
|
Oct 09 10:58:17 PM UTC 24 |
Oct 09 10:58:31 PM UTC 24 |
1893227057 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.2692972713 |
|
|
Oct 09 10:58:16 PM UTC 24 |
Oct 09 10:58:32 PM UTC 24 |
461769364 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.3949284379 |
|
|
Oct 09 10:58:27 PM UTC 24 |
Oct 09 10:58:32 PM UTC 24 |
150168410 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.2265748750 |
|
|
Oct 09 10:57:55 PM UTC 24 |
Oct 09 10:58:32 PM UTC 24 |
8279567689 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.3008041159 |
|
|
Oct 09 10:58:30 PM UTC 24 |
Oct 09 10:58:32 PM UTC 24 |
16623534 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3372224610 |
|
|
Oct 09 10:58:30 PM UTC 24 |
Oct 09 10:58:32 PM UTC 24 |
34539201 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.862708854 |
|
|
Oct 09 10:57:44 PM UTC 24 |
Oct 09 10:58:32 PM UTC 24 |
3528302906 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.435422936 |
|
|
Oct 09 10:58:23 PM UTC 24 |
Oct 09 10:58:33 PM UTC 24 |
877162842 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1663990585 |
|
|
Oct 09 10:57:39 PM UTC 24 |
Oct 09 10:58:33 PM UTC 24 |
3227886953 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.2043088775 |
|
|
Oct 09 10:58:30 PM UTC 24 |
Oct 09 10:58:33 PM UTC 24 |
20227167 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.1295199415 |
|
|
Oct 09 10:58:16 PM UTC 24 |
Oct 09 10:58:33 PM UTC 24 |
3235582816 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.2310340675 |
|
|
Oct 09 10:58:25 PM UTC 24 |
Oct 09 10:58:34 PM UTC 24 |
226120195 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3381777010 |
|
|
Oct 09 10:56:05 PM UTC 24 |
Oct 09 10:58:35 PM UTC 24 |
2781321520 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.421717013 |
|
|
Oct 09 10:58:13 PM UTC 24 |
Oct 09 10:58:35 PM UTC 24 |
308091890 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.413927840 |
|
|
Oct 09 10:58:23 PM UTC 24 |
Oct 09 10:58:35 PM UTC 24 |
101587635 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.4119383112 |
|
|
Oct 09 10:58:32 PM UTC 24 |
Oct 09 10:58:36 PM UTC 24 |
56829465 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.2166832329 |
|
|
Oct 09 10:58:06 PM UTC 24 |
Oct 09 10:58:36 PM UTC 24 |
896397089 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_errors.3490448992 |
|
|
Oct 09 10:58:23 PM UTC 24 |
Oct 09 10:58:36 PM UTC 24 |
942866940 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.3520967386 |
|
|
Oct 09 10:57:25 PM UTC 24 |
Oct 09 10:58:37 PM UTC 24 |
1785259919 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.925672858 |
|
|
Oct 09 10:58:27 PM UTC 24 |
Oct 09 10:58:38 PM UTC 24 |
357651241 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.853283884 |
|
|
Oct 09 10:58:14 PM UTC 24 |
Oct 09 10:58:38 PM UTC 24 |
865684436 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.980922736 |
|
|
Oct 09 10:58:28 PM UTC 24 |
Oct 09 10:58:39 PM UTC 24 |
304894434 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.4045323909 |
|
|
Oct 09 10:58:37 PM UTC 24 |
Oct 09 10:58:39 PM UTC 24 |
229296718 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1417092872 |
|
|
Oct 09 10:58:37 PM UTC 24 |
Oct 09 10:58:39 PM UTC 24 |
19808153 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.2573280866 |
|
|
Oct 09 10:58:37 PM UTC 24 |
Oct 09 10:58:40 PM UTC 24 |
142702084 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.2030873428 |
|
|
Oct 09 10:58:00 PM UTC 24 |
Oct 09 10:58:40 PM UTC 24 |
2812760845 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.4090846665 |
|
|
Oct 09 10:58:34 PM UTC 24 |
Oct 09 10:58:41 PM UTC 24 |
799818559 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.4088492134 |
|
|
Oct 09 10:58:01 PM UTC 24 |
Oct 09 10:58:41 PM UTC 24 |
10667586106 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.3322510111 |
|
|
Oct 09 10:58:21 PM UTC 24 |
Oct 09 10:58:42 PM UTC 24 |
182030035 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.964485821 |
|
|
Oct 09 10:58:37 PM UTC 24 |
Oct 09 10:58:42 PM UTC 24 |
420868689 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.1853092250 |
|
|
Oct 09 10:58:39 PM UTC 24 |
Oct 09 10:58:43 PM UTC 24 |
84105391 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.1811256615 |
|
|
Oct 09 10:58:31 PM UTC 24 |
Oct 09 10:58:43 PM UTC 24 |
618977037 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.3836678417 |
|
|
Oct 09 10:58:34 PM UTC 24 |
Oct 09 10:58:44 PM UTC 24 |
388835512 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.375928964 |
|
|
Oct 09 10:58:27 PM UTC 24 |
Oct 09 10:58:45 PM UTC 24 |
431971726 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.3573886146 |
|
|
Oct 09 10:58:41 PM UTC 24 |
Oct 09 10:58:46 PM UTC 24 |
98978563 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.2945779072 |
|
|
Oct 09 10:57:45 PM UTC 24 |
Oct 09 10:58:47 PM UTC 24 |
9076002984 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.2607234197 |
|
|
Oct 09 10:58:34 PM UTC 24 |
Oct 09 10:58:46 PM UTC 24 |
2341294024 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.1020502947 |
|
|
Oct 09 10:58:34 PM UTC 24 |
Oct 09 10:58:46 PM UTC 24 |
331104946 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.3513348707 |
|
|
Oct 09 10:58:35 PM UTC 24 |
Oct 09 10:58:47 PM UTC 24 |
5239634536 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.3973004182 |
|
|
Oct 09 10:58:35 PM UTC 24 |
Oct 09 10:58:48 PM UTC 24 |
1029746594 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.2012435946 |
|
|
Oct 09 10:58:45 PM UTC 24 |
Oct 09 10:58:48 PM UTC 24 |
233549349 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.3033520647 |
|
|
Oct 09 10:58:40 PM UTC 24 |
Oct 09 10:58:48 PM UTC 24 |
1610967021 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.1919556280 |
|
|
Oct 09 10:58:34 PM UTC 24 |
Oct 09 10:58:48 PM UTC 24 |
403550355 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3552225938 |
|
|
Oct 09 10:58:47 PM UTC 24 |
Oct 09 10:58:49 PM UTC 24 |
32335194 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.2011692088 |
|
|
Oct 09 10:58:33 PM UTC 24 |
Oct 09 10:58:49 PM UTC 24 |
264960124 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.37554056 |
|
|
Oct 09 10:58:34 PM UTC 24 |
Oct 09 10:58:49 PM UTC 24 |
411708242 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.1777973867 |
|
|
Oct 09 10:58:25 PM UTC 24 |
Oct 09 10:58:50 PM UTC 24 |
3440897202 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.2587585538 |
|
|
Oct 09 10:59:18 PM UTC 24 |
Oct 09 10:59:20 PM UTC 24 |
64357861 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.3065072792 |
|
|
Oct 09 10:59:18 PM UTC 24 |
Oct 09 10:59:22 PM UTC 24 |
30511990 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.708268154 |
|
|
Oct 09 10:58:11 PM UTC 24 |
Oct 09 10:58:51 PM UTC 24 |
1131631050 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.4076759335 |
|
|
Oct 09 10:58:47 PM UTC 24 |
Oct 09 10:58:52 PM UTC 24 |
59809604 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.3722150423 |
|
|
Oct 09 10:58:43 PM UTC 24 |
Oct 09 10:58:53 PM UTC 24 |
353631657 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.3535256521 |
|
|
Oct 09 10:59:15 PM UTC 24 |
Oct 09 10:59:21 PM UTC 24 |
1763389002 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.1895216257 |
|
|
Oct 09 10:57:57 PM UTC 24 |
Oct 09 10:58:54 PM UTC 24 |
3110083755 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.3043295220 |
|
|
Oct 09 10:58:16 PM UTC 24 |
Oct 09 10:58:54 PM UTC 24 |
7657089477 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.2898492880 |
|
|
Oct 09 10:58:17 PM UTC 24 |
Oct 09 10:58:55 PM UTC 24 |
7335667701 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.321903426 |
|
|
Oct 09 10:58:48 PM UTC 24 |
Oct 09 10:58:56 PM UTC 24 |
800571997 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.538610155 |
|
|
Oct 09 10:58:53 PM UTC 24 |
Oct 09 10:58:56 PM UTC 24 |
62737628 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.4237161848 |
|
|
Oct 09 10:58:10 PM UTC 24 |
Oct 09 10:58:57 PM UTC 24 |
2594978560 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.1550026048 |
|
|
Oct 09 10:58:16 PM UTC 24 |
Oct 09 10:58:57 PM UTC 24 |
914786370 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.2347298696 |
|
|
Oct 09 10:58:40 PM UTC 24 |
Oct 09 10:58:57 PM UTC 24 |
1102818030 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.3722579548 |
|
|
Oct 09 10:58:48 PM UTC 24 |
Oct 09 10:58:57 PM UTC 24 |
698510504 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.90141683 |
|
|
Oct 09 10:58:55 PM UTC 24 |
Oct 09 10:58:58 PM UTC 24 |
13488912 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.1638671702 |
|
|
Oct 09 10:58:39 PM UTC 24 |
Oct 09 10:58:58 PM UTC 24 |
879784727 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.172147620 |
|
|
Oct 09 10:58:40 PM UTC 24 |
Oct 09 10:58:58 PM UTC 24 |
1497840173 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.2558617515 |
|
|
Oct 09 10:58:55 PM UTC 24 |
Oct 09 10:58:58 PM UTC 24 |
42230048 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.235287311 |
|
|
Oct 09 10:58:48 PM UTC 24 |
Oct 09 10:58:59 PM UTC 24 |
280335887 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.2382454423 |
|
|
Oct 09 10:58:27 PM UTC 24 |
Oct 09 10:59:00 PM UTC 24 |
2103310493 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.2366177691 |
|
|
Oct 09 10:58:47 PM UTC 24 |
Oct 09 10:59:00 PM UTC 24 |
251859287 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.4122815465 |
|
|
Oct 09 10:58:31 PM UTC 24 |
Oct 09 10:59:00 PM UTC 24 |
1701552843 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.2720927620 |
|
|
Oct 09 10:58:50 PM UTC 24 |
Oct 09 10:59:01 PM UTC 24 |
2225319962 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.2205428615 |
|
|
Oct 09 10:59:04 PM UTC 24 |
Oct 09 10:59:22 PM UTC 24 |
355285609 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.1052144171 |
|
|
Oct 09 10:58:50 PM UTC 24 |
Oct 09 10:59:01 PM UTC 24 |
461297570 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.3081335729 |
|
|
Oct 09 10:58:56 PM UTC 24 |
Oct 09 10:59:01 PM UTC 24 |
148768508 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.10698580 |
|
|
Oct 09 10:58:58 PM UTC 24 |
Oct 09 10:59:02 PM UTC 24 |
46640020 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.3059934699 |
|
|
Oct 09 10:58:50 PM UTC 24 |
Oct 09 10:59:02 PM UTC 24 |
883294942 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.543889344 |
|
|
Oct 09 10:58:50 PM UTC 24 |
Oct 09 10:59:02 PM UTC 24 |
471413145 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.4103289153 |
|
|
Oct 09 10:58:59 PM UTC 24 |
Oct 09 10:59:03 PM UTC 24 |
297115342 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.2833820098 |
|
|
Oct 09 10:58:08 PM UTC 24 |
Oct 09 10:59:03 PM UTC 24 |
1587995607 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.4043715968 |
|
|
Oct 09 10:57:55 PM UTC 24 |
Oct 09 10:59:03 PM UTC 24 |
1800331911 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.2476154206 |
|
|
Oct 09 10:58:43 PM UTC 24 |
Oct 09 10:59:04 PM UTC 24 |
3279426741 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3028235236 |
|
|
Oct 09 10:59:02 PM UTC 24 |
Oct 09 10:59:05 PM UTC 24 |
37905683 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.304732602 |
|
|
Oct 09 10:59:02 PM UTC 24 |
Oct 09 10:59:05 PM UTC 24 |
76542832 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.4123712074 |
|
|
Oct 09 10:58:58 PM UTC 24 |
Oct 09 10:59:06 PM UTC 24 |
370965591 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.1880764456 |
|
|
Oct 09 10:58:50 PM UTC 24 |
Oct 09 10:59:07 PM UTC 24 |
2603192324 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.253260253 |
|
|
Oct 09 10:58:37 PM UTC 24 |
Oct 09 10:59:08 PM UTC 24 |
744793561 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.3023888720 |
|
|
Oct 09 10:58:47 PM UTC 24 |
Oct 09 10:59:09 PM UTC 24 |
753978302 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.3617427220 |
|
|
Oct 09 10:59:04 PM UTC 24 |
Oct 09 10:59:09 PM UTC 24 |
71560080 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.3820401842 |
|
|
Oct 09 10:59:02 PM UTC 24 |
Oct 09 10:59:09 PM UTC 24 |
394849453 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.521437640 |
|
|
Oct 09 10:58:51 PM UTC 24 |
Oct 09 10:59:10 PM UTC 24 |
385866711 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.1229607540 |
|
|
Oct 09 10:59:01 PM UTC 24 |
Oct 09 10:59:11 PM UTC 24 |
391253921 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.912381452 |
|
|
Oct 09 10:58:59 PM UTC 24 |
Oct 09 10:59:11 PM UTC 24 |
1171336419 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.3601005304 |
|
|
Oct 09 10:58:58 PM UTC 24 |
Oct 09 10:59:11 PM UTC 24 |
1145154808 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.2494781635 |
|
|
Oct 09 10:58:59 PM UTC 24 |
Oct 09 10:59:12 PM UTC 24 |
944028648 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.3682847882 |
|
|
Oct 09 10:58:43 PM UTC 24 |
Oct 09 10:59:12 PM UTC 24 |
4764543734 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.3799496774 |
|
|
Oct 09 10:59:11 PM UTC 24 |
Oct 09 10:59:14 PM UTC 24 |
160564184 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.415705871 |
|
|
Oct 09 10:59:02 PM UTC 24 |
Oct 09 10:59:14 PM UTC 24 |
60316788 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3543692824 |
|
|
Oct 09 10:58:58 PM UTC 24 |
Oct 09 10:59:14 PM UTC 24 |
1591940646 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2869367140 |
|
|
Oct 09 10:58:19 PM UTC 24 |
Oct 09 10:59:14 PM UTC 24 |
4272800027 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.229058258 |
|
|
Oct 09 10:58:25 PM UTC 24 |
Oct 09 10:59:14 PM UTC 24 |
3964920005 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.450364705 |
|
|
Oct 09 10:59:12 PM UTC 24 |
Oct 09 10:59:15 PM UTC 24 |
23648581 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.3959360458 |
|
|
Oct 09 10:59:05 PM UTC 24 |
Oct 09 10:59:15 PM UTC 24 |
287591793 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.3214016611 |
|
|
Oct 09 10:59:08 PM UTC 24 |
Oct 09 10:59:16 PM UTC 24 |
175615174 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.3803716179 |
|
|
Oct 09 10:59:12 PM UTC 24 |
Oct 09 10:59:16 PM UTC 24 |
55735938 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.484589743 |
|
|
Oct 09 10:57:20 PM UTC 24 |
Oct 09 10:59:16 PM UTC 24 |
17839166025 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.2463202420 |
|
|
Oct 09 10:58:43 PM UTC 24 |
Oct 09 10:59:17 PM UTC 24 |
667262858 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.1404276539 |
|
|
Oct 09 10:59:06 PM UTC 24 |
Oct 09 10:59:17 PM UTC 24 |
347727222 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.681141434 |
|
|
Oct 09 10:59:04 PM UTC 24 |
Oct 09 10:59:17 PM UTC 24 |
4067364208 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.159334252 |
|
|
Oct 09 10:59:06 PM UTC 24 |
Oct 09 10:59:17 PM UTC 24 |
2968604281 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.1299774514 |
|
|
Oct 09 10:59:13 PM UTC 24 |
Oct 09 10:59:18 PM UTC 24 |
46174341 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.2672420933 |
|
|
Oct 09 10:59:09 PM UTC 24 |
Oct 09 10:59:18 PM UTC 24 |
422370772 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.3665989694 |
|
|
Oct 09 10:58:58 PM UTC 24 |
Oct 09 10:59:19 PM UTC 24 |
5489552913 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.2235411066 |
|
|
Oct 09 10:59:09 PM UTC 24 |
Oct 09 10:59:19 PM UTC 24 |
272104282 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.3827923484 |
|
|
Oct 09 10:59:14 PM UTC 24 |
Oct 09 10:59:22 PM UTC 24 |
227531848 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2495226642 |
|
|
Oct 09 10:59:18 PM UTC 24 |
Oct 09 10:59:20 PM UTC 24 |
17945171 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.468077869 |
|
|
Oct 09 10:58:55 PM UTC 24 |
Oct 09 10:59:21 PM UTC 24 |
306340770 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.3108693770 |
|
|
Oct 09 10:59:01 PM UTC 24 |
Oct 09 10:59:23 PM UTC 24 |
1292877554 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.4129566579 |
|
|
Oct 09 10:59:19 PM UTC 24 |
Oct 09 10:59:23 PM UTC 24 |
122749141 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.600086041 |
|
|
Oct 09 10:59:13 PM UTC 24 |
Oct 09 10:59:23 PM UTC 24 |
89748779 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.1668949926 |
|
|
Oct 09 10:58:34 PM UTC 24 |
Oct 09 10:59:24 PM UTC 24 |
3562340503 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.222147249 |
|
|
Oct 09 10:59:08 PM UTC 24 |
Oct 09 10:59:24 PM UTC 24 |
2577988308 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.168931105 |
|
|
Oct 09 10:59:22 PM UTC 24 |
Oct 09 10:59:24 PM UTC 24 |
13964949 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.3972952410 |
|
|
Oct 09 10:59:19 PM UTC 24 |
Oct 09 10:59:25 PM UTC 24 |
135360886 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.865730593 |
|
|
Oct 09 10:59:02 PM UTC 24 |
Oct 09 10:59:25 PM UTC 24 |
2383007581 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.3028078296 |
|
|
Oct 09 10:59:22 PM UTC 24 |
Oct 09 10:59:25 PM UTC 24 |
37095657 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.833900975 |
|
|
Oct 09 10:59:22 PM UTC 24 |
Oct 09 10:59:27 PM UTC 24 |
130336128 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.3768177165 |
|
|
Oct 09 10:59:16 PM UTC 24 |
Oct 09 10:59:27 PM UTC 24 |
2782673132 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.2079274784 |
|
|
Oct 09 10:59:14 PM UTC 24 |
Oct 09 10:59:28 PM UTC 24 |
494251851 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.3159693899 |
|
|
Oct 09 10:59:19 PM UTC 24 |
Oct 09 10:59:28 PM UTC 24 |
1117683497 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.3318238002 |
|
|
Oct 09 10:58:50 PM UTC 24 |
Oct 09 10:59:28 PM UTC 24 |
1467110032 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.2424876612 |
|
|
Oct 09 10:59:25 PM UTC 24 |
Oct 09 10:59:29 PM UTC 24 |
60573679 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.2671787953 |
|
|
Oct 09 10:58:40 PM UTC 24 |
Oct 09 10:59:29 PM UTC 24 |
4505448183 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.1571009264 |
|
|
Oct 09 10:59:16 PM UTC 24 |
Oct 09 10:59:30 PM UTC 24 |
1392932232 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.2729937291 |
|
|
Oct 09 10:59:20 PM UTC 24 |
Oct 09 10:59:32 PM UTC 24 |
1549200165 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.1611877096 |
|
|
Oct 09 10:59:21 PM UTC 24 |
Oct 09 10:59:32 PM UTC 24 |
353485207 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.2385332730 |
|
|
Oct 09 10:59:30 PM UTC 24 |
Oct 09 10:59:32 PM UTC 24 |
21600381 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.2098976561 |
|
|
Oct 09 10:59:21 PM UTC 24 |
Oct 09 10:59:32 PM UTC 24 |
742104783 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.464273937 |
|
|
Oct 09 10:59:30 PM UTC 24 |
Oct 09 10:59:32 PM UTC 24 |
27778626 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.856663456 |
|
|
Oct 09 10:58:48 PM UTC 24 |
Oct 09 10:59:32 PM UTC 24 |
1378939242 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.3069083798 |
|
|
Oct 09 10:59:30 PM UTC 24 |
Oct 09 10:59:33 PM UTC 24 |
18081015 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.2781591412 |
|
|
Oct 09 10:59:16 PM UTC 24 |
Oct 09 10:59:33 PM UTC 24 |
1431215833 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.232795117 |
|
|
Oct 09 10:59:25 PM UTC 24 |
Oct 09 10:59:33 PM UTC 24 |
194808122 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.864940354 |
|
|
Oct 09 10:58:34 PM UTC 24 |
Oct 09 10:59:34 PM UTC 24 |
8430738526 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.4169025744 |
|
|
Oct 09 10:59:19 PM UTC 24 |
Oct 09 10:59:34 PM UTC 24 |
522928525 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.3374563734 |
|
|
Oct 09 10:59:21 PM UTC 24 |
Oct 09 10:59:34 PM UTC 24 |
340413298 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.701653256 |
|
|
Oct 09 10:59:30 PM UTC 24 |
Oct 09 10:59:35 PM UTC 24 |
110096489 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.579996588 |
|
|
Oct 09 10:58:53 PM UTC 24 |
Oct 09 10:59:35 PM UTC 24 |
3893598317 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.1361128799 |
|
|
Oct 09 10:59:34 PM UTC 24 |
Oct 09 10:59:37 PM UTC 24 |
170426666 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.339209648 |
|
|
Oct 09 10:59:34 PM UTC 24 |
Oct 09 10:59:37 PM UTC 24 |
19974151 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.3206774838 |
|
|
Oct 09 10:59:06 PM UTC 24 |
Oct 09 10:59:38 PM UTC 24 |
1545406437 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.2058060541 |
|
|
Oct 09 10:59:30 PM UTC 24 |
Oct 09 10:59:38 PM UTC 24 |
113528745 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.3904682378 |
|
|
Oct 09 10:59:27 PM UTC 24 |
Oct 09 10:59:38 PM UTC 24 |
805103812 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.4222466590 |
|
|
Oct 09 10:59:34 PM UTC 24 |
Oct 09 10:59:39 PM UTC 24 |
56690305 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.2560515035 |
|
|
Oct 09 10:59:32 PM UTC 24 |
Oct 09 10:59:40 PM UTC 24 |
326375594 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.2367938835 |
|
|
Oct 09 10:59:36 PM UTC 24 |
Oct 09 10:59:40 PM UTC 24 |
121133085 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.2947552841 |
|
|
Oct 09 10:59:27 PM UTC 24 |
Oct 09 10:59:40 PM UTC 24 |
2505689121 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.2035865351 |
|
|
Oct 09 10:59:27 PM UTC 24 |
Oct 09 10:59:41 PM UTC 24 |
317830226 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.3355613233 |
|
|
Oct 09 10:59:25 PM UTC 24 |
Oct 09 10:59:41 PM UTC 24 |
6340701851 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.2354667821 |
|
|
Oct 09 10:59:39 PM UTC 24 |
Oct 09 10:59:41 PM UTC 24 |
16783257 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.3830608044 |
|
|
Oct 09 10:59:37 PM UTC 24 |
Oct 09 10:59:42 PM UTC 24 |
321549352 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1421712409 |
|
|
Oct 09 10:59:40 PM UTC 24 |
Oct 09 10:59:43 PM UTC 24 |
35125594 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.3951582249 |
|
|
Oct 09 10:59:12 PM UTC 24 |
Oct 09 10:59:43 PM UTC 24 |
232701760 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.1224224610 |
|
|
Oct 09 10:59:34 PM UTC 24 |
Oct 09 10:59:43 PM UTC 24 |
1380300665 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.4202547413 |
|
|
Oct 09 10:59:32 PM UTC 24 |
Oct 09 10:59:43 PM UTC 24 |
1041358402 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.2579498193 |
|
|
Oct 09 10:58:52 PM UTC 24 |
Oct 09 10:59:44 PM UTC 24 |
18142758867 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.2195042649 |
|
|
Oct 09 10:58:28 PM UTC 24 |
Oct 09 10:59:44 PM UTC 24 |
2506777551 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.3413441350 |
|
|
Oct 09 10:59:34 PM UTC 24 |
Oct 09 10:59:44 PM UTC 24 |
467247084 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.3127145779 |
|
|
Oct 09 10:59:34 PM UTC 24 |
Oct 09 10:59:44 PM UTC 24 |
832430155 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.2449067549 |
|
|
Oct 09 10:59:42 PM UTC 24 |
Oct 09 10:59:45 PM UTC 24 |
28294478 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.1672477347 |
|
|
Oct 09 10:59:36 PM UTC 24 |
Oct 09 10:59:45 PM UTC 24 |
96563448 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.4094302948 |
|
|
Oct 09 10:59:40 PM UTC 24 |
Oct 09 10:59:45 PM UTC 24 |
97721477 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.3523945317 |
|
|
Oct 09 10:59:36 PM UTC 24 |
Oct 09 10:59:47 PM UTC 24 |
3229014437 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.1181661858 |
|
|
Oct 09 10:59:45 PM UTC 24 |
Oct 09 10:59:47 PM UTC 24 |
17495705 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.1543904807 |
|
|
Oct 09 10:59:27 PM UTC 24 |
Oct 09 10:59:48 PM UTC 24 |
3237432524 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.4290345641 |
|
|
Oct 09 10:58:41 PM UTC 24 |
Oct 09 10:59:48 PM UTC 24 |
2479503301 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.3298628448 |
|
|
Oct 09 10:59:39 PM UTC 24 |
Oct 09 10:59:49 PM UTC 24 |
221419888 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.4073752531 |
|
|
Oct 09 10:59:46 PM UTC 24 |
Oct 09 10:59:49 PM UTC 24 |
41321674 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.2153568173 |
|
|
Oct 09 10:59:34 PM UTC 24 |
Oct 09 10:59:49 PM UTC 24 |
4377974035 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.1546363791 |
|
|
Oct 09 10:59:36 PM UTC 24 |
Oct 09 10:59:50 PM UTC 24 |
3863872137 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2406182661 |
|
|
Oct 09 10:58:44 PM UTC 24 |
Oct 09 10:59:51 PM UTC 24 |
5603944718 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.354081478 |
|
|
Oct 09 10:59:46 PM UTC 24 |
Oct 09 10:59:51 PM UTC 24 |
56587334 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.1690914764 |
|
|
Oct 09 10:59:42 PM UTC 24 |
Oct 09 10:59:51 PM UTC 24 |
857037213 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.1346914258 |
|
|
Oct 09 10:59:43 PM UTC 24 |
Oct 09 10:59:52 PM UTC 24 |
279376821 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.3218982538 |
|
|
Oct 09 10:59:27 PM UTC 24 |
Oct 09 10:59:52 PM UTC 24 |
4332342849 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.3959106413 |
|
|
Oct 09 10:59:39 PM UTC 24 |
Oct 09 10:59:52 PM UTC 24 |
1098141767 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.2262810380 |
|
|
Oct 09 10:59:23 PM UTC 24 |
Oct 09 10:59:53 PM UTC 24 |
262485441 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.3066949606 |
|
|
Oct 09 10:59:45 PM UTC 24 |
Oct 09 10:59:54 PM UTC 24 |
277077846 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.3257410668 |
|
|
Oct 09 10:59:52 PM UTC 24 |
Oct 09 10:59:54 PM UTC 24 |
33459754 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1543389064 |
|
|
Oct 09 10:59:52 PM UTC 24 |
Oct 09 10:59:55 PM UTC 24 |
11921653 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.3537383415 |
|
|
Oct 09 10:59:46 PM UTC 24 |
Oct 09 10:59:55 PM UTC 24 |
66548833 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.3520890083 |
|
|
Oct 09 10:59:45 PM UTC 24 |
Oct 09 10:59:56 PM UTC 24 |
149267653 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.4140039710 |
|
|
Oct 09 10:59:36 PM UTC 24 |
Oct 09 10:59:56 PM UTC 24 |
699047709 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.1204892595 |
|
|
Oct 09 10:59:45 PM UTC 24 |
Oct 09 10:59:57 PM UTC 24 |
959438308 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.3188356305 |
|
|
Oct 09 10:59:43 PM UTC 24 |
Oct 09 10:59:57 PM UTC 24 |
605131209 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.8810919 |
|
|
Oct 09 10:59:52 PM UTC 24 |
Oct 09 10:59:58 PM UTC 24 |
53755603 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.3367059913 |
|
|
Oct 09 10:59:18 PM UTC 24 |
Oct 09 10:59:58 PM UTC 24 |
1357201467 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.18948890 |
|
|
Oct 09 10:59:43 PM UTC 24 |
Oct 09 10:59:59 PM UTC 24 |
1889210857 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.175286896 |
|
|
Oct 09 10:59:45 PM UTC 24 |
Oct 09 10:59:59 PM UTC 24 |
1856021673 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.3409479229 |
|
|
Oct 09 10:59:53 PM UTC 24 |
Oct 09 11:00:00 PM UTC 24 |
95021801 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.3269249970 |
|
|
Oct 09 10:59:49 PM UTC 24 |
Oct 09 11:00:00 PM UTC 24 |
408927781 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.296348652 |
|
|
Oct 09 10:59:59 PM UTC 24 |
Oct 09 11:00:01 PM UTC 24 |
52308584 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.497642263 |
|
|
Oct 09 10:59:55 PM UTC 24 |
Oct 09 11:00:01 PM UTC 24 |
745238487 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.1327355867 |
|
|
Oct 09 10:59:40 PM UTC 24 |
Oct 09 11:00:02 PM UTC 24 |
473387098 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.3443052481 |
|
|
Oct 09 10:59:49 PM UTC 24 |
Oct 09 11:00:02 PM UTC 24 |
796416751 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.3840912380 |
|
|
Oct 09 10:59:38 PM UTC 24 |
Oct 09 11:00:02 PM UTC 24 |
5405440646 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1582363421 |
|
|
Oct 09 10:59:02 PM UTC 24 |
Oct 09 11:00:03 PM UTC 24 |
1442191113 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.2094624087 |
|
|
Oct 09 10:59:53 PM UTC 24 |
Oct 09 11:00:03 PM UTC 24 |
132733193 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.4187523768 |
|
|
Oct 09 10:59:50 PM UTC 24 |
Oct 09 11:00:03 PM UTC 24 |
2579718336 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.298908307 |
|
|
Oct 09 10:59:49 PM UTC 24 |
Oct 09 11:00:04 PM UTC 24 |
511266995 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.3167514776 |
|
|
Oct 09 10:58:59 PM UTC 24 |
Oct 09 11:00:04 PM UTC 24 |
20080094572 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.4105434633 |
|
|
Oct 09 10:58:58 PM UTC 24 |
Oct 09 11:00:05 PM UTC 24 |
20536578139 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.2191958937 |
|
|
Oct 09 10:59:09 PM UTC 24 |
Oct 09 11:00:05 PM UTC 24 |
2631643000 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.3852190185 |
|
|
Oct 09 10:59:59 PM UTC 24 |
Oct 09 11:00:05 PM UTC 24 |
160932608 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.2535826081 |
|
|
Oct 09 10:59:55 PM UTC 24 |
Oct 09 11:00:05 PM UTC 24 |
667118353 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.3505622763 |
|
|
Oct 09 10:59:30 PM UTC 24 |
Oct 09 11:00:07 PM UTC 24 |
1148168199 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.2635433305 |
|
|
Oct 09 10:59:56 PM UTC 24 |
Oct 09 11:00:07 PM UTC 24 |
851652696 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_errors.3949072705 |
|
|
Oct 09 10:59:55 PM UTC 24 |
Oct 09 11:00:08 PM UTC 24 |
615022515 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2685391138 |
|
|
Oct 09 10:59:50 PM UTC 24 |
Oct 09 11:00:09 PM UTC 24 |
1451344424 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.1479112515 |
|
|
Oct 09 10:59:57 PM UTC 24 |
Oct 09 11:00:09 PM UTC 24 |
1472787511 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.1400651719 |
|
|
Oct 09 10:59:56 PM UTC 24 |
Oct 09 11:00:09 PM UTC 24 |
450256337 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.2547588037 |
|
|
Oct 09 11:00:21 PM UTC 24 |
Oct 09 11:00:31 PM UTC 24 |
297284196 ps |