| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.33 | 97.97 | 95.95 | 93.40 | 100.00 | 98.53 | 99.00 | 96.47 |
| T1003 | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2482011172 | Oct 09 11:02:48 PM UTC 24 | Oct 09 11:02:50 PM UTC 24 | 57932580 ps | ||
| T1004 | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2100544179 | Oct 09 11:02:47 PM UTC 24 | Oct 09 11:02:50 PM UTC 24 | 21373507 ps | ||
| T1005 | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.691628829 | Oct 09 11:02:47 PM UTC 24 | Oct 09 11:02:50 PM UTC 24 | 75370821 ps | ||
| T1006 | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.487345752 | Oct 09 11:02:47 PM UTC 24 | Oct 09 11:02:50 PM UTC 24 | 23949143 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1566599356 | Oct 09 11:02:47 PM UTC 24 | Oct 09 11:02:50 PM UTC 24 | 64636470 ps | ||
| T1007 | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.959842776 | Oct 09 11:02:47 PM UTC 24 | Oct 09 11:02:50 PM UTC 24 | 27468875 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.325467189 | Oct 09 11:02:47 PM UTC 24 | Oct 09 11:02:51 PM UTC 24 | 253598832 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3259645666 | Oct 09 11:02:47 PM UTC 24 | Oct 09 11:02:52 PM UTC 24 | 405310092 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.770030163 | Oct 09 11:02:34 PM UTC 24 | Oct 09 11:02:55 PM UTC 24 | 839297861 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.4027830587 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1530139887 ps |
| CPU time | 12.76 seconds |
| Started | Oct 09 10:55:30 PM UTC 24 |
| Finished | Oct 09 10:55:45 PM UTC 24 |
| Peak memory | 230356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027830587 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.4027830587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3970779343 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1288559227 ps |
| CPU time | 10.15 seconds |
| Started | Oct 09 10:55:53 PM UTC 24 |
| Finished | Oct 09 10:56:04 PM UTC 24 |
| Peak memory | 236888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970779343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ ctrl_jtag_state_post_trans.3970779343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.795528451 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 1653190348 ps |
| CPU time | 16.96 seconds |
| Started | Oct 09 10:55:30 PM UTC 24 |
| Finished | Oct 09 10:55:49 PM UTC 24 |
| Peak memory | 237936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795528451 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.795528451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.931293192 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 918462632 ps |
| CPU time | 23.18 seconds |
| Started | Oct 09 10:56:38 PM UTC 24 |
| Finished | Oct 09 10:57:03 PM UTC 24 |
| Peak memory | 232376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931293192 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.931293192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1949779231 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2249480652 ps |
| CPU time | 12.98 seconds |
| Started | Oct 09 10:55:38 PM UTC 24 |
| Finished | Oct 09 10:55:52 PM UTC 24 |
| Peak memory | 230720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949779231 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_ mux.1949779231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.240756105 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4160744087 ps |
| CPU time | 28.21 seconds |
| Started | Oct 09 10:55:55 PM UTC 24 |
| Finished | Oct 09 10:56:25 PM UTC 24 |
| Peak memory | 230508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240756105 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.240756105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.2753774450 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1154900511 ps |
| CPU time | 39.79 seconds |
| Started | Oct 09 10:57:31 PM UTC 24 |
| Finished | Oct 09 10:58:12 PM UTC 24 |
| Peak memory | 285752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753774450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.2753774450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2954488845 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 638601322 ps |
| CPU time | 33.31 seconds |
| Started | Oct 09 10:55:41 PM UTC 24 |
| Finished | Oct 09 10:56:16 PM UTC 24 |
| Peak memory | 298452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954488845 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2954488845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2977308170 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 43285309 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 10:55:27 PM UTC 24 |
| Finished | Oct 09 10:55:29 PM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977308170 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. lc_ctrl_volatile_unlock_smoke.2977308170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1780359367 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 237120441 ps |
| CPU time | 2.89 seconds |
| Started | Oct 09 11:02:06 PM UTC 24 |
| Finished | Oct 09 11:02:10 PM UTC 24 |
| Peak memory | 229768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780359367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1780359367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.341638836 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 496269462 ps |
| CPU time | 14.61 seconds |
| Started | Oct 09 10:55:50 PM UTC 24 |
| Finished | Oct 09 10:56:06 PM UTC 24 |
| Peak memory | 238032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341638836 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.341638836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.2086491026 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 4531191797 ps |
| CPU time | 24.47 seconds |
| Started | Oct 09 10:56:43 PM UTC 24 |
| Finished | Oct 09 10:57:10 PM UTC 24 |
| Peak memory | 263124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086491026 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2086491026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1272629470 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 106787181 ps |
| CPU time | 3.66 seconds |
| Started | Oct 09 11:02:06 PM UTC 24 |
| Finished | Oct 09 11:02:11 PM UTC 24 |
| Peak memory | 235796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272629470 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_ intg_err.1272629470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.3953558684 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 43674862679 ps |
| CPU time | 289.07 seconds |
| Started | Oct 09 11:00:49 PM UTC 24 |
| Finished | Oct 09 11:05:42 PM UTC 24 |
| Peak memory | 283620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3953558684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 36.lc_ctrl_stress_all.3953558684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.681141434 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4067364208 ps |
| CPU time | 12.12 seconds |
| Started | Oct 09 10:59:04 PM UTC 24 |
| Finished | Oct 09 10:59:17 PM UTC 24 |
| Peak memory | 238492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681141434 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.681141434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2327779817 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1873892865 ps |
| CPU time | 39 seconds |
| Started | Oct 09 10:55:40 PM UTC 24 |
| Finished | Oct 09 10:56:21 PM UTC 24 |
| Peak memory | 238076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327779817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.2327779817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.1494635235 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7175881338 ps |
| CPU time | 26.69 seconds |
| Started | Oct 09 10:55:32 PM UTC 24 |
| Finished | Oct 09 10:56:00 PM UTC 24 |
| Peak memory | 263060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494635235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ ctrl_jtag_state_post_trans.1494635235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3219315720 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 16823085 ps |
| CPU time | 1.6 seconds |
| Started | Oct 09 11:02:08 PM UTC 24 |
| Finished | Oct 09 11:02:10 PM UTC 24 |
| Peak memory | 228312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219315720 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3219315720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.939448093 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 35322218 ps |
| CPU time | 1.7 seconds |
| Started | Oct 09 10:55:45 PM UTC 24 |
| Finished | Oct 09 10:55:48 PM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939448093 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.939448093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.2601874354 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 276327124 ps |
| CPU time | 10.95 seconds |
| Started | Oct 09 10:56:00 PM UTC 24 |
| Finished | Oct 09 10:56:12 PM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601874354 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2601874354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3352849019 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 785082954 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 11:02:39 PM UTC 24 |
| Finished | Oct 09 11:02:43 PM UTC 24 |
| Peak memory | 235784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352849019 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl _intg_err.3352849019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2226941381 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1566663147 ps |
| CPU time | 29.5 seconds |
| Started | Oct 09 10:56:27 PM UTC 24 |
| Finished | Oct 09 10:56:58 PM UTC 24 |
| Peak memory | 261028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226941381 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2226941381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.1061781656 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1033137158 ps |
| CPU time | 33.95 seconds |
| Started | Oct 09 10:55:28 PM UTC 24 |
| Finished | Oct 09 10:56:04 PM UTC 24 |
| Peak memory | 263076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061781656 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1061781656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2062726451 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4337467093 ps |
| CPU time | 17.97 seconds |
| Started | Oct 09 10:55:35 PM UTC 24 |
| Finished | Oct 09 10:55:55 PM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062726451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ ctrl_jtag_regwen_during_op.2062726451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3731382287 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 78358766 ps |
| CPU time | 2.8 seconds |
| Started | Oct 09 11:02:37 PM UTC 24 |
| Finished | Oct 09 11:02:41 PM UTC 24 |
| Peak memory | 236196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731382287 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_ intg_err.3731382287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3573875542 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 56092358 ps |
| CPU time | 1.87 seconds |
| Started | Oct 09 11:02:14 PM UTC 24 |
| Finished | Oct 09 11:02:17 PM UTC 24 |
| Peak memory | 218576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357387 5542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc _ctrl_same_csr_outstanding.3573875542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1656790869 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 422929886 ps |
| CPU time | 2.04 seconds |
| Started | Oct 09 11:02:20 PM UTC 24 |
| Finished | Oct 09 11:02:23 PM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656790869 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1656790869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.3829353753 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2864724294 ps |
| CPU time | 75.75 seconds |
| Started | Oct 09 10:56:05 PM UTC 24 |
| Finished | Oct 09 10:57:22 PM UTC 24 |
| Peak memory | 263060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3829353753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 1.lc_ctrl_stress_all.3829353753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1877264546 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 18446267 ps |
| CPU time | 1.66 seconds |
| Started | Oct 09 10:55:45 PM UTC 24 |
| Finished | Oct 09 10:55:48 PM UTC 24 |
| Peak memory | 222824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877264546 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1. lc_ctrl_volatile_unlock_smoke.1877264546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.818779414 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 127861431 ps |
| CPU time | 3.29 seconds |
| Started | Oct 09 11:02:12 PM UTC 24 |
| Finished | Oct 09 11:02:17 PM UTC 24 |
| Peak memory | 235776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818779414 -asse rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_i ntg_err.818779414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3696143536 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 353526551 ps |
| CPU time | 2.98 seconds |
| Started | Oct 09 11:02:34 PM UTC 24 |
| Finished | Oct 09 11:02:38 PM UTC 24 |
| Peak memory | 233748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696143536 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_ intg_err.3696143536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3381777010 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 2781321520 ps |
| CPU time | 147.2 seconds |
| Started | Oct 09 10:56:05 PM UTC 24 |
| Finished | Oct 09 10:58:35 PM UTC 24 |
| Peak memory | 263356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381777010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.3381777010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.259762339 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 185309257 ps |
| CPU time | 23.32 seconds |
| Started | Oct 09 10:57:52 PM UTC 24 |
| Finished | Oct 09 10:58:16 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259762339 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.259762339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.3735651876 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 212276621 ps |
| CPU time | 10.6 seconds |
| Started | Oct 09 10:55:49 PM UTC 24 |
| Finished | Oct 09 10:56:00 PM UTC 24 |
| Peak memory | 263144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735651876 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3735651876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1730141495 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 26814794 ps |
| CPU time | 2.72 seconds |
| Started | Oct 09 11:02:06 PM UTC 24 |
| Finished | Oct 09 11:02:10 PM UTC 24 |
| Peak memory | 231680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730141495 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1730141495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2857915229 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 178963322 ps |
| CPU time | 4.87 seconds |
| Started | Oct 09 10:55:33 PM UTC 24 |
| Finished | Oct 09 10:55:39 PM UTC 24 |
| Peak memory | 234300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857915229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl _jtag_prog_failure.2857915229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.1153026761 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 164155516 ps |
| CPU time | 8.74 seconds |
| Started | Oct 09 10:58:00 PM UTC 24 |
| Finished | Oct 09 10:58:10 PM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153026761 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1153026761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.2376183460 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 23497795 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 10:56:32 PM UTC 24 |
| Finished | Oct 09 10:56:34 PM UTC 24 |
| Peak memory | 217936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376183460 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2376183460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.2372076436 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 19222495 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 10:56:49 PM UTC 24 |
| Finished | Oct 09 10:56:51 PM UTC 24 |
| Peak memory | 218548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372076436 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2372076436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.608418983 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 79493976 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:57:24 PM UTC 24 |
| Finished | Oct 09 10:57:26 PM UTC 24 |
| Peak memory | 218968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608418983 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.608418983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.1038191415 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 11437812 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 10:57:35 PM UTC 24 |
| Finished | Oct 09 10:57:38 PM UTC 24 |
| Peak memory | 217876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038191415 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1038191415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.4164596817 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 10997105 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 10:57:43 PM UTC 24 |
| Finished | Oct 09 10:57:45 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164596817 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.4164596817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1113312311 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 263324883 ps |
| CPU time | 2.4 seconds |
| Started | Oct 09 11:02:03 PM UTC 24 |
| Finished | Oct 09 11:02:06 PM UTC 24 |
| Peak memory | 221372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1113312311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1113312311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3989727639 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 69382038 ps |
| CPU time | 3.21 seconds |
| Started | Oct 09 11:02:39 PM UTC 24 |
| Finished | Oct 09 11:02:43 PM UTC 24 |
| Peak memory | 229728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989727639 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl _intg_err.3989727639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4076306653 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 153763537 ps |
| CPU time | 1.81 seconds |
| Started | Oct 09 11:02:41 PM UTC 24 |
| Finished | Oct 09 11:02:44 PM UTC 24 |
| Peak memory | 234544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076306653 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl _intg_err.4076306653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.649722967 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 396943494 ps |
| CPU time | 3.99 seconds |
| Started | Oct 09 11:02:41 PM UTC 24 |
| Finished | Oct 09 11:02:46 PM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649722967 -asse rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_ intg_err.649722967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2951319189 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 136137398 ps |
| CPU time | 3.71 seconds |
| Started | Oct 09 11:02:43 PM UTC 24 |
| Finished | Oct 09 11:02:48 PM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951319189 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl _intg_err.2951319189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.306061917 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 65229505 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 11:02:45 PM UTC 24 |
| Finished | Oct 09 11:02:48 PM UTC 24 |
| Peak memory | 233760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306061917 -asse rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_ intg_err.306061917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3259645666 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 405310092 ps |
| CPU time | 3.23 seconds |
| Started | Oct 09 11:02:47 PM UTC 24 |
| Finished | Oct 09 11:02:52 PM UTC 24 |
| Peak memory | 235720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259645666 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl _intg_err.3259645666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3234661177 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 123011323 ps |
| CPU time | 2.79 seconds |
| Started | Oct 09 11:02:29 PM UTC 24 |
| Finished | Oct 09 11:02:33 PM UTC 24 |
| Peak memory | 229636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234661177 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_ intg_err.3234661177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.3809824707 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2212754586 ps |
| CPU time | 65.44 seconds |
| Started | Oct 09 10:56:56 PM UTC 24 |
| Finished | Oct 09 10:58:04 PM UTC 24 |
| Peak memory | 271392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3809824707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 4.lc_ctrl_stress_all.3809824707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.2823032095 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2973918269 ps |
| CPU time | 71.46 seconds |
| Started | Oct 09 10:55:32 PM UTC 24 |
| Finished | Oct 09 10:56:45 PM UTC 24 |
| Peak memory | 283420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823032095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr l_jtag_state_failure.2823032095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3539733612 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 120546780 ps |
| CPU time | 1.48 seconds |
| Started | Oct 09 11:02:08 PM UTC 24 |
| Finished | Oct 09 11:02:10 PM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539733612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_al iasing.3539733612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3037018273 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 188945681 ps |
| CPU time | 2.65 seconds |
| Started | Oct 09 11:02:08 PM UTC 24 |
| Finished | Oct 09 11:02:12 PM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037018273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bi t_bash.3037018273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4000622350 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 56470173 ps |
| CPU time | 1.76 seconds |
| Started | Oct 09 11:02:08 PM UTC 24 |
| Finished | Oct 09 11:02:11 PM UTC 24 |
| Peak memory | 230444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000622350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw _reset.4000622350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.32378415 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 62698939 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 11:02:09 PM UTC 24 |
| Finished | Oct 09 11:02:12 PM UTC 24 |
| Peak memory | 228048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=32378415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.32378415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3111544263 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 36720806 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 11:02:06 PM UTC 24 |
| Finished | Oct 09 11:02:09 PM UTC 24 |
| Peak memory | 218820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3111544263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3111544263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3589382189 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 447214020 ps |
| CPU time | 7.99 seconds |
| Started | Oct 09 11:02:04 PM UTC 24 |
| Finished | Oct 09 11:02:13 PM UTC 24 |
| Peak memory | 219372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3589382189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3589382189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.849319179 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2887715057 ps |
| CPU time | 19.22 seconds |
| Started | Oct 09 11:02:04 PM UTC 24 |
| Finished | Oct 09 11:02:24 PM UTC 24 |
| Peak memory | 219080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=849319179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.849319179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1854060228 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 56289726 ps |
| CPU time | 2.22 seconds |
| Started | Oct 09 11:02:03 PM UTC 24 |
| Finished | Oct 09 11:02:06 PM UTC 24 |
| Peak memory | 218720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1854060228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 0.lc_ctrl_jtag_csr_rw.1854060228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.545052483 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 18097639 ps |
| CPU time | 1.76 seconds |
| Started | Oct 09 11:02:05 PM UTC 24 |
| Finished | Oct 09 11:02:08 PM UTC 24 |
| Peak memory | 218576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=545052483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.545052483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1900757736 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 35121598 ps |
| CPU time | 1.94 seconds |
| Started | Oct 09 11:02:09 PM UTC 24 |
| Finished | Oct 09 11:02:12 PM UTC 24 |
| Peak memory | 218328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190075 7736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc _ctrl_same_csr_outstanding.1900757736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3397233770 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 109466925 ps |
| CPU time | 1.74 seconds |
| Started | Oct 09 11:02:14 PM UTC 24 |
| Finished | Oct 09 11:02:17 PM UTC 24 |
| Peak memory | 218576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397233770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_al iasing.3397233770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1890052730 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 54401428 ps |
| CPU time | 2.39 seconds |
| Started | Oct 09 11:02:14 PM UTC 24 |
| Finished | Oct 09 11:02:17 PM UTC 24 |
| Peak memory | 219352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890052730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bi t_bash.1890052730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.315914499 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 56336223 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 11:02:12 PM UTC 24 |
| Finished | Oct 09 11:02:15 PM UTC 24 |
| Peak memory | 220204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315914499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_ reset.315914499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2482983223 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 29485073 ps |
| CPU time | 2.03 seconds |
| Started | Oct 09 11:02:14 PM UTC 24 |
| Finished | Oct 09 11:02:17 PM UTC 24 |
| Peak memory | 231756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2482983223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2482983223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2810198371 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 12598950 ps |
| CPU time | 0.96 seconds |
| Started | Oct 09 11:02:12 PM UTC 24 |
| Finished | Oct 09 11:02:14 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810198371 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2810198371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3426238738 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 33066768 ps |
| CPU time | 1.75 seconds |
| Started | Oct 09 11:02:12 PM UTC 24 |
| Finished | Oct 09 11:02:15 PM UTC 24 |
| Peak memory | 218544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3426238738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3426238738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3975030486 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 984369379 ps |
| CPU time | 6.33 seconds |
| Started | Oct 09 11:02:12 PM UTC 24 |
| Finished | Oct 09 11:02:19 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3975030486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3975030486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2861936893 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 1801977749 ps |
| CPU time | 21.24 seconds |
| Started | Oct 09 11:02:11 PM UTC 24 |
| Finished | Oct 09 11:02:33 PM UTC 24 |
| Peak memory | 219276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2861936893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2861936893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.998362491 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 478882301 ps |
| CPU time | 1.84 seconds |
| Started | Oct 09 11:02:09 PM UTC 24 |
| Finished | Oct 09 11:02:12 PM UTC 24 |
| Peak memory | 220612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=998362491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.998362491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3334468027 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 75310309 ps |
| CPU time | 3.13 seconds |
| Started | Oct 09 11:02:12 PM UTC 24 |
| Finished | Oct 09 11:02:16 PM UTC 24 |
| Peak memory | 234120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334468027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3334468027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2838045436 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 186770442 ps |
| CPU time | 1.9 seconds |
| Started | Oct 09 11:02:10 PM UTC 24 |
| Finished | Oct 09 11:02:13 PM UTC 24 |
| Peak memory | 218936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2838045436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 1.lc_ctrl_jtag_csr_rw.2838045436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.515303731 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 38400241 ps |
| CPU time | 2.04 seconds |
| Started | Oct 09 11:02:12 PM UTC 24 |
| Finished | Oct 09 11:02:15 PM UTC 24 |
| Peak memory | 219392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=515303731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.515303731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3724229998 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 68494546 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 11:02:12 PM UTC 24 |
| Finished | Oct 09 11:02:17 PM UTC 24 |
| Peak memory | 232016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724229998 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3724229998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2908563877 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 72878144 ps |
| CPU time | 1.76 seconds |
| Started | Oct 09 11:02:39 PM UTC 24 |
| Finished | Oct 09 11:02:42 PM UTC 24 |
| Peak memory | 228404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2908563877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2908563877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3339820191 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 17221433 ps |
| CPU time | 1.5 seconds |
| Started | Oct 09 11:02:39 PM UTC 24 |
| Finished | Oct 09 11:02:41 PM UTC 24 |
| Peak memory | 228396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339820191 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3339820191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3942678421 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 156353944 ps |
| CPU time | 1.78 seconds |
| Started | Oct 09 11:02:39 PM UTC 24 |
| Finished | Oct 09 11:02:42 PM UTC 24 |
| Peak memory | 228892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394267 8421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.l c_ctrl_same_csr_outstanding.3942678421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.885937806 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 139840340 ps |
| CPU time | 4.59 seconds |
| Started | Oct 09 11:02:37 PM UTC 24 |
| Finished | Oct 09 11:02:43 PM UTC 24 |
| Peak memory | 229972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885937806 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.885937806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2003480764 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 23966712 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 11:02:41 PM UTC 24 |
| Finished | Oct 09 11:02:43 PM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2003480764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2003480764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2192593942 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 14962114 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 11:02:39 PM UTC 24 |
| Finished | Oct 09 11:02:41 PM UTC 24 |
| Peak memory | 218096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192593942 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2192593942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3872423716 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 36653194 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 11:02:39 PM UTC 24 |
| Finished | Oct 09 11:02:42 PM UTC 24 |
| Peak memory | 218512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387242 3716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.l c_ctrl_same_csr_outstanding.3872423716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.503061583 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 140362758 ps |
| CPU time | 1.96 seconds |
| Started | Oct 09 11:02:39 PM UTC 24 |
| Finished | Oct 09 11:02:42 PM UTC 24 |
| Peak memory | 228396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503061583 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.503061583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4250149796 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 44088592 ps |
| CPU time | 1.59 seconds |
| Started | Oct 09 11:02:41 PM UTC 24 |
| Finished | Oct 09 11:02:44 PM UTC 24 |
| Peak memory | 228404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4250149796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.4250149796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1517667744 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 15887741 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 11:02:41 PM UTC 24 |
| Finished | Oct 09 11:02:43 PM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517667744 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1517667744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2832653042 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 30127855 ps |
| CPU time | 1.75 seconds |
| Started | Oct 09 11:02:41 PM UTC 24 |
| Finished | Oct 09 11:02:44 PM UTC 24 |
| Peak memory | 218580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283265 3042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.l c_ctrl_same_csr_outstanding.2832653042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2383582959 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 36776255 ps |
| CPU time | 2.2 seconds |
| Started | Oct 09 11:02:41 PM UTC 24 |
| Finished | Oct 09 11:02:44 PM UTC 24 |
| Peak memory | 229636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383582959 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2383582959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1692285796 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 21424522 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 11:02:43 PM UTC 24 |
| Finished | Oct 09 11:02:45 PM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1692285796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1692285796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2599480980 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 14482518 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 11:02:43 PM UTC 24 |
| Finished | Oct 09 11:02:45 PM UTC 24 |
| Peak memory | 218096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599480980 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2599480980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2223943464 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 129013395 ps |
| CPU time | 1.65 seconds |
| Started | Oct 09 11:02:43 PM UTC 24 |
| Finished | Oct 09 11:02:45 PM UTC 24 |
| Peak memory | 220628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222394 3464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.l c_ctrl_same_csr_outstanding.2223943464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2982908751 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 43303344 ps |
| CPU time | 3.36 seconds |
| Started | Oct 09 11:02:41 PM UTC 24 |
| Finished | Oct 09 11:02:46 PM UTC 24 |
| Peak memory | 231632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982908751 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2982908751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.389210459 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 63087093 ps |
| CPU time | 2.01 seconds |
| Started | Oct 09 11:02:43 PM UTC 24 |
| Finished | Oct 09 11:02:46 PM UTC 24 |
| Peak memory | 232072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=389210459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.389210459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3747225286 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 41821220 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 11:02:43 PM UTC 24 |
| Finished | Oct 09 11:02:45 PM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747225286 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3747225286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3009772822 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 94526004 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 11:02:43 PM UTC 24 |
| Finished | Oct 09 11:02:45 PM UTC 24 |
| Peak memory | 218652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300977 2822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.l c_ctrl_same_csr_outstanding.3009772822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2912862115 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 57763188 ps |
| CPU time | 2.53 seconds |
| Started | Oct 09 11:02:43 PM UTC 24 |
| Finished | Oct 09 11:02:46 PM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912862115 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2912862115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3294230275 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 140135214 ps |
| CPU time | 2.07 seconds |
| Started | Oct 09 11:02:43 PM UTC 24 |
| Finished | Oct 09 11:02:46 PM UTC 24 |
| Peak memory | 236176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294230275 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl _intg_err.3294230275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2528548014 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 23429705 ps |
| CPU time | 1.79 seconds |
| Started | Oct 09 11:02:45 PM UTC 24 |
| Finished | Oct 09 11:02:48 PM UTC 24 |
| Peak memory | 228404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2528548014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2528548014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.655794595 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 25781480 ps |
| CPU time | 0.84 seconds |
| Started | Oct 09 11:02:43 PM UTC 24 |
| Finished | Oct 09 11:02:45 PM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655794595 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.655794595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2849603658 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 78285510 ps |
| CPU time | 1.5 seconds |
| Started | Oct 09 11:02:43 PM UTC 24 |
| Finished | Oct 09 11:02:46 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284960 3658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.l c_ctrl_same_csr_outstanding.2849603658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4241763992 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 69680921 ps |
| CPU time | 2.88 seconds |
| Started | Oct 09 11:02:43 PM UTC 24 |
| Finished | Oct 09 11:02:47 PM UTC 24 |
| Peak memory | 229652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241763992 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.4241763992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4265580071 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 26169341 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 11:02:45 PM UTC 24 |
| Finished | Oct 09 11:02:47 PM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=4265580071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.4265580071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1115045900 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 19787436 ps |
| CPU time | 1 seconds |
| Started | Oct 09 11:02:45 PM UTC 24 |
| Finished | Oct 09 11:02:47 PM UTC 24 |
| Peak memory | 218096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115045900 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1115045900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3985860192 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 24700406 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 11:02:45 PM UTC 24 |
| Finished | Oct 09 11:02:47 PM UTC 24 |
| Peak memory | 218224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398586 0192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.l c_ctrl_same_csr_outstanding.3985860192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3873604127 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 31952068 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 11:02:45 PM UTC 24 |
| Finished | Oct 09 11:02:48 PM UTC 24 |
| Peak memory | 229636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873604127 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3873604127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1005506680 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 412286113 ps |
| CPU time | 1.77 seconds |
| Started | Oct 09 11:02:45 PM UTC 24 |
| Finished | Oct 09 11:02:48 PM UTC 24 |
| Peak memory | 228460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005506680 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl _intg_err.1005506680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1313140256 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 141015459 ps |
| CPU time | 1.63 seconds |
| Started | Oct 09 11:02:45 PM UTC 24 |
| Finished | Oct 09 11:02:48 PM UTC 24 |
| Peak memory | 234548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1313140256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1313140256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2321935979 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 17605758 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 11:02:45 PM UTC 24 |
| Finished | Oct 09 11:02:48 PM UTC 24 |
| Peak memory | 218096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321935979 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2321935979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.19212831 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 123192795 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 11:02:45 PM UTC 24 |
| Finished | Oct 09 11:02:48 PM UTC 24 |
| Peak memory | 218636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192128 31 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ ctrl_same_csr_outstanding.19212831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4080782332 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 55621350 ps |
| CPU time | 2.52 seconds |
| Started | Oct 09 11:02:45 PM UTC 24 |
| Finished | Oct 09 11:02:49 PM UTC 24 |
| Peak memory | 231680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080782332 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.4080782332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3180998594 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 60824590 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 11:02:47 PM UTC 24 |
| Finished | Oct 09 11:02:50 PM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3180998594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3180998594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3906820937 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 29454535 ps |
| CPU time | 1.03 seconds |
| Started | Oct 09 11:02:47 PM UTC 24 |
| Finished | Oct 09 11:02:49 PM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906820937 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3906820937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.487345752 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 23949143 ps |
| CPU time | 1.84 seconds |
| Started | Oct 09 11:02:47 PM UTC 24 |
| Finished | Oct 09 11:02:50 PM UTC 24 |
| Peak memory | 220688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487345 752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc _ctrl_same_csr_outstanding.487345752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.325467189 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 253598832 ps |
| CPU time | 2.97 seconds |
| Started | Oct 09 11:02:47 PM UTC 24 |
| Finished | Oct 09 11:02:51 PM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325467189 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.325467189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1566599356 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 64636470 ps |
| CPU time | 1.98 seconds |
| Started | Oct 09 11:02:47 PM UTC 24 |
| Finished | Oct 09 11:02:50 PM UTC 24 |
| Peak memory | 228400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566599356 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl _intg_err.1566599356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2482011172 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 57932580 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 11:02:48 PM UTC 24 |
| Finished | Oct 09 11:02:50 PM UTC 24 |
| Peak memory | 228404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2482011172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2482011172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2100544179 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 21373507 ps |
| CPU time | 1.36 seconds |
| Started | Oct 09 11:02:47 PM UTC 24 |
| Finished | Oct 09 11:02:50 PM UTC 24 |
| Peak memory | 218604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100544179 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2100544179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.691628829 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 75370821 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 11:02:47 PM UTC 24 |
| Finished | Oct 09 11:02:50 PM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691628 829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc _ctrl_same_csr_outstanding.691628829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.959842776 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 27468875 ps |
| CPU time | 1.92 seconds |
| Started | Oct 09 11:02:47 PM UTC 24 |
| Finished | Oct 09 11:02:50 PM UTC 24 |
| Peak memory | 228460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959842776 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.959842776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.443487838 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 135731331 ps |
| CPU time | 1.48 seconds |
| Started | Oct 09 11:02:18 PM UTC 24 |
| Finished | Oct 09 11:02:21 PM UTC 24 |
| Peak memory | 218696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443487838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_ali asing.443487838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1266271589 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 65315551 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 11:02:17 PM UTC 24 |
| Finished | Oct 09 11:02:19 PM UTC 24 |
| Peak memory | 218868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266271589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bi t_bash.1266271589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2386513404 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 34855266 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 11:02:16 PM UTC 24 |
| Finished | Oct 09 11:02:18 PM UTC 24 |
| Peak memory | 220204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386513404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw _reset.2386513404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2169361016 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 43185573 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 11:02:18 PM UTC 24 |
| Finished | Oct 09 11:02:21 PM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2169361016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2169361016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3193979483 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 52155221 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 11:02:17 PM UTC 24 |
| Finished | Oct 09 11:02:19 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193979483 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3193979483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.391265952 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 124586881 ps |
| CPU time | 1.54 seconds |
| Started | Oct 09 11:02:15 PM UTC 24 |
| Finished | Oct 09 11:02:18 PM UTC 24 |
| Peak memory | 218668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=391265952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.lc_ctrl_jtag_alert_test.391265952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3220185495 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 4924658511 ps |
| CPU time | 27.77 seconds |
| Started | Oct 09 11:02:14 PM UTC 24 |
| Finished | Oct 09 11:02:43 PM UTC 24 |
| Peak memory | 219388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3220185495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3220185495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.354209254 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 2681803233 ps |
| CPU time | 9.9 seconds |
| Started | Oct 09 11:02:14 PM UTC 24 |
| Finished | Oct 09 11:02:25 PM UTC 24 |
| Peak memory | 219668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=354209254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.354209254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.64012778 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 150873025 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 11:02:14 PM UTC 24 |
| Finished | Oct 09 11:02:18 PM UTC 24 |
| Peak memory | 221376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=64012778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.64012778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2810733033 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 51702693 ps |
| CPU time | 1.6 seconds |
| Started | Oct 09 11:02:14 PM UTC 24 |
| Finished | Oct 09 11:02:17 PM UTC 24 |
| Peak memory | 230448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810733033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2810733033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1364797003 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 301514511 ps |
| CPU time | 2.6 seconds |
| Started | Oct 09 11:02:14 PM UTC 24 |
| Finished | Oct 09 11:02:18 PM UTC 24 |
| Peak memory | 219320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1364797003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 2.lc_ctrl_jtag_csr_rw.1364797003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.673454031 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 16886998 ps |
| CPU time | 1.66 seconds |
| Started | Oct 09 11:02:14 PM UTC 24 |
| Finished | Oct 09 11:02:17 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=673454031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.673454031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3542380308 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 203456803 ps |
| CPU time | 2.06 seconds |
| Started | Oct 09 11:02:18 PM UTC 24 |
| Finished | Oct 09 11:02:21 PM UTC 24 |
| Peak memory | 229960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354238 0308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc _ctrl_same_csr_outstanding.3542380308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2330234906 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 256850280 ps |
| CPU time | 2.21 seconds |
| Started | Oct 09 11:02:15 PM UTC 24 |
| Finished | Oct 09 11:02:19 PM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330234906 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2330234906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2113731916 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 127364559 ps |
| CPU time | 3.37 seconds |
| Started | Oct 09 11:02:16 PM UTC 24 |
| Finished | Oct 09 11:02:20 PM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113731916 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_ intg_err.2113731916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.254189088 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 41635185 ps |
| CPU time | 2 seconds |
| Started | Oct 09 11:02:20 PM UTC 24 |
| Finished | Oct 09 11:02:23 PM UTC 24 |
| Peak memory | 218468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254189088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_ali asing.254189088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2531088016 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 38013880 ps |
| CPU time | 1.78 seconds |
| Started | Oct 09 11:02:20 PM UTC 24 |
| Finished | Oct 09 11:02:23 PM UTC 24 |
| Peak memory | 218656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531088016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bi t_bash.2531088016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1162749155 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 160152427 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 11:02:20 PM UTC 24 |
| Finished | Oct 09 11:02:22 PM UTC 24 |
| Peak memory | 230444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162749155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw _reset.1162749155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1929034218 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 70798928 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 11:02:21 PM UTC 24 |
| Finished | Oct 09 11:02:24 PM UTC 24 |
| Peak memory | 228404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1929034218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1929034218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.795073589 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 32660564 ps |
| CPU time | 1.11 seconds |
| Started | Oct 09 11:02:20 PM UTC 24 |
| Finished | Oct 09 11:02:22 PM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795073589 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.795073589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.811643094 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 43246354 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 11:02:20 PM UTC 24 |
| Finished | Oct 09 11:02:22 PM UTC 24 |
| Peak memory | 218804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=811643094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.lc_ctrl_jtag_alert_test.811643094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4149658599 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 263270611 ps |
| CPU time | 6.95 seconds |
| Started | Oct 09 11:02:18 PM UTC 24 |
| Finished | Oct 09 11:02:26 PM UTC 24 |
| Peak memory | 218644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4149658599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.4149658599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3828224555 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 913852919 ps |
| CPU time | 5.46 seconds |
| Started | Oct 09 11:02:18 PM UTC 24 |
| Finished | Oct 09 11:02:25 PM UTC 24 |
| Peak memory | 219280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3828224555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3828224555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.34527681 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 79784785 ps |
| CPU time | 1.84 seconds |
| Started | Oct 09 11:02:18 PM UTC 24 |
| Finished | Oct 09 11:02:21 PM UTC 24 |
| Peak memory | 220564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=34527681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.34527681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3360883447 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 95469459 ps |
| CPU time | 4.1 seconds |
| Started | Oct 09 11:02:18 PM UTC 24 |
| Finished | Oct 09 11:02:24 PM UTC 24 |
| Peak memory | 229704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360883447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3360883447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2468612855 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 35656390 ps |
| CPU time | 2.4 seconds |
| Started | Oct 09 11:02:18 PM UTC 24 |
| Finished | Oct 09 11:02:22 PM UTC 24 |
| Peak memory | 219656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2468612855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 3.lc_ctrl_jtag_csr_rw.2468612855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3139230542 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 21131140 ps |
| CPU time | 1.93 seconds |
| Started | Oct 09 11:02:18 PM UTC 24 |
| Finished | Oct 09 11:02:21 PM UTC 24 |
| Peak memory | 220684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3139230542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3139230542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.985824404 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 73001117 ps |
| CPU time | 1.63 seconds |
| Started | Oct 09 11:02:21 PM UTC 24 |
| Finished | Oct 09 11:02:24 PM UTC 24 |
| Peak memory | 228884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985824 404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ ctrl_same_csr_outstanding.985824404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2149881422 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 78672469 ps |
| CPU time | 2.81 seconds |
| Started | Oct 09 11:02:20 PM UTC 24 |
| Finished | Oct 09 11:02:24 PM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149881422 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_ intg_err.2149881422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2700128842 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 25444864 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 11:02:24 PM UTC 24 |
| Finished | Oct 09 11:02:26 PM UTC 24 |
| Peak memory | 218532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700128842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_al iasing.2700128842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1908720190 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 78132998 ps |
| CPU time | 1.76 seconds |
| Started | Oct 09 11:02:24 PM UTC 24 |
| Finished | Oct 09 11:02:27 PM UTC 24 |
| Peak memory | 218708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908720190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bi t_bash.1908720190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4268852673 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 32988551 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 11:02:24 PM UTC 24 |
| Finished | Oct 09 11:02:26 PM UTC 24 |
| Peak memory | 220204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268852673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw _reset.4268852673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2830032817 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 72676019 ps |
| CPU time | 1.84 seconds |
| Started | Oct 09 11:02:25 PM UTC 24 |
| Finished | Oct 09 11:02:28 PM UTC 24 |
| Peak memory | 232500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2830032817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2830032817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.602283346 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 26408269 ps |
| CPU time | 0.93 seconds |
| Started | Oct 09 11:02:24 PM UTC 24 |
| Finished | Oct 09 11:02:26 PM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602283346 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.602283346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1102228798 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 272040890 ps |
| CPU time | 2.32 seconds |
| Started | Oct 09 11:02:22 PM UTC 24 |
| Finished | Oct 09 11:02:26 PM UTC 24 |
| Peak memory | 218956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1102228798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1102228798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3830092921 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 2024166858 ps |
| CPU time | 3.69 seconds |
| Started | Oct 09 11:02:22 PM UTC 24 |
| Finished | Oct 09 11:02:27 PM UTC 24 |
| Peak memory | 219200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3830092921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3830092921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1429711529 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 495114452 ps |
| CPU time | 11.93 seconds |
| Started | Oct 09 11:02:22 PM UTC 24 |
| Finished | Oct 09 11:02:36 PM UTC 24 |
| Peak memory | 219300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1429711529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1429711529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1696392712 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 198679176 ps |
| CPU time | 2.05 seconds |
| Started | Oct 09 11:02:21 PM UTC 24 |
| Finished | Oct 09 11:02:24 PM UTC 24 |
| Peak memory | 221444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1696392712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1696392712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4227343483 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 81160160 ps |
| CPU time | 1.96 seconds |
| Started | Oct 09 11:02:22 PM UTC 24 |
| Finished | Oct 09 11:02:25 PM UTC 24 |
| Peak memory | 230448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227343483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4227343483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.508140084 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 243554306 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 11:02:21 PM UTC 24 |
| Finished | Oct 09 11:02:24 PM UTC 24 |
| Peak memory | 218868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=508140084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.lc_ctrl_jtag_csr_rw.508140084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1919616739 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 72496299 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 11:02:22 PM UTC 24 |
| Finished | Oct 09 11:02:25 PM UTC 24 |
| Peak memory | 218632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1919616739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1919616739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1156781882 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 28040806 ps |
| CPU time | 1.81 seconds |
| Started | Oct 09 11:02:25 PM UTC 24 |
| Finished | Oct 09 11:02:28 PM UTC 24 |
| Peak memory | 218636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115678 1882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc _ctrl_same_csr_outstanding.1156781882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2837936361 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 122687402 ps |
| CPU time | 5.34 seconds |
| Started | Oct 09 11:02:23 PM UTC 24 |
| Finished | Oct 09 11:02:29 PM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837936361 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2837936361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.22338825 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 58178881 ps |
| CPU time | 2.45 seconds |
| Started | Oct 09 11:02:24 PM UTC 24 |
| Finished | Oct 09 11:02:27 PM UTC 24 |
| Peak memory | 229728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22338825 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_in tg_err.22338825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3314146436 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 61047818 ps |
| CPU time | 1.95 seconds |
| Started | Oct 09 11:02:27 PM UTC 24 |
| Finished | Oct 09 11:02:30 PM UTC 24 |
| Peak memory | 234548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3314146436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3314146436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2308695402 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 41209176 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 11:02:27 PM UTC 24 |
| Finished | Oct 09 11:02:29 PM UTC 24 |
| Peak memory | 218364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308695402 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2308695402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.56329778 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 428664353 ps |
| CPU time | 1.96 seconds |
| Started | Oct 09 11:02:26 PM UTC 24 |
| Finished | Oct 09 11:02:29 PM UTC 24 |
| Peak memory | 218808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=56329778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.lc_ctrl_jtag_alert_test.56329778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2554018279 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2751236300 ps |
| CPU time | 9.42 seconds |
| Started | Oct 09 11:02:25 PM UTC 24 |
| Finished | Oct 09 11:02:36 PM UTC 24 |
| Peak memory | 219456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2554018279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2554018279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2520593918 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 2550919265 ps |
| CPU time | 16.61 seconds |
| Started | Oct 09 11:02:25 PM UTC 24 |
| Finished | Oct 09 11:02:43 PM UTC 24 |
| Peak memory | 219388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2520593918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2520593918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3473170532 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 151819890 ps |
| CPU time | 4.11 seconds |
| Started | Oct 09 11:02:25 PM UTC 24 |
| Finished | Oct 09 11:02:31 PM UTC 24 |
| Peak memory | 221372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3473170532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3473170532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1339904699 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 539213920 ps |
| CPU time | 6.93 seconds |
| Started | Oct 09 11:02:25 PM UTC 24 |
| Finished | Oct 09 11:02:34 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339904699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1339904699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.913696595 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 1267707717 ps |
| CPU time | 2.41 seconds |
| Started | Oct 09 11:02:25 PM UTC 24 |
| Finished | Oct 09 11:02:29 PM UTC 24 |
| Peak memory | 219404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=913696595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.lc_ctrl_jtag_csr_rw.913696595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2599695672 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 39417808 ps |
| CPU time | 1.4 seconds |
| Started | Oct 09 11:02:25 PM UTC 24 |
| Finished | Oct 09 11:02:28 PM UTC 24 |
| Peak memory | 218540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2599695672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2599695672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2907779830 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 25081476 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 11:02:27 PM UTC 24 |
| Finished | Oct 09 11:02:30 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290777 9830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc _ctrl_same_csr_outstanding.2907779830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4085524124 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 984444442 ps |
| CPU time | 4.45 seconds |
| Started | Oct 09 11:02:27 PM UTC 24 |
| Finished | Oct 09 11:02:33 PM UTC 24 |
| Peak memory | 231952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085524124 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.4085524124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.77551716 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 82074749 ps |
| CPU time | 2.56 seconds |
| Started | Oct 09 11:02:27 PM UTC 24 |
| Finished | Oct 09 11:02:31 PM UTC 24 |
| Peak memory | 233736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77551716 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_in tg_err.77551716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3214712348 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 27515646 ps |
| CPU time | 1.65 seconds |
| Started | Oct 09 11:02:30 PM UTC 24 |
| Finished | Oct 09 11:02:33 PM UTC 24 |
| Peak memory | 228400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3214712348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3214712348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1748312947 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 123357895 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 11:02:29 PM UTC 24 |
| Finished | Oct 09 11:02:31 PM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748312947 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1748312947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1635361422 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 74605374 ps |
| CPU time | 2.33 seconds |
| Started | Oct 09 11:02:29 PM UTC 24 |
| Finished | Oct 09 11:02:32 PM UTC 24 |
| Peak memory | 219392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1635361422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1635361422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1788134475 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 2902609289 ps |
| CPU time | 11.68 seconds |
| Started | Oct 09 11:02:29 PM UTC 24 |
| Finished | Oct 09 11:02:41 PM UTC 24 |
| Peak memory | 219404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1788134475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1788134475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3635789201 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 765420978 ps |
| CPU time | 16.66 seconds |
| Started | Oct 09 11:02:27 PM UTC 24 |
| Finished | Oct 09 11:02:45 PM UTC 24 |
| Peak memory | 219428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3635789201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3635789201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1104851491 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 108823838 ps |
| CPU time | 3.01 seconds |
| Started | Oct 09 11:02:27 PM UTC 24 |
| Finished | Oct 09 11:02:31 PM UTC 24 |
| Peak memory | 221700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1104851491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1104851491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1827493097 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 104007128 ps |
| CPU time | 3.43 seconds |
| Started | Oct 09 11:02:29 PM UTC 24 |
| Finished | Oct 09 11:02:33 PM UTC 24 |
| Peak memory | 230024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827493097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1827493097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1753746637 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 343675527 ps |
| CPU time | 2.71 seconds |
| Started | Oct 09 11:02:27 PM UTC 24 |
| Finished | Oct 09 11:02:31 PM UTC 24 |
| Peak memory | 219308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1753746637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 6.lc_ctrl_jtag_csr_rw.1753746637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3993732634 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 65343069 ps |
| CPU time | 1.78 seconds |
| Started | Oct 09 11:02:29 PM UTC 24 |
| Finished | Oct 09 11:02:31 PM UTC 24 |
| Peak memory | 218644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3993732634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3993732634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1894735468 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 29299609 ps |
| CPU time | 1.55 seconds |
| Started | Oct 09 11:02:29 PM UTC 24 |
| Finished | Oct 09 11:02:32 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189473 5468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc _ctrl_same_csr_outstanding.1894735468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.958365120 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 417050729 ps |
| CPU time | 4.66 seconds |
| Started | Oct 09 11:02:29 PM UTC 24 |
| Finished | Oct 09 11:02:35 PM UTC 24 |
| Peak memory | 229960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958365120 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.958365120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2300784472 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 81303016 ps |
| CPU time | 2.67 seconds |
| Started | Oct 09 11:02:34 PM UTC 24 |
| Finished | Oct 09 11:02:38 PM UTC 24 |
| Peak memory | 229724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=2300784472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2300784472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1908063098 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 103594096 ps |
| CPU time | 1.51 seconds |
| Started | Oct 09 11:02:32 PM UTC 24 |
| Finished | Oct 09 11:02:35 PM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908063098 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1908063098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3327346671 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 829690600 ps |
| CPU time | 2.09 seconds |
| Started | Oct 09 11:02:32 PM UTC 24 |
| Finished | Oct 09 11:02:35 PM UTC 24 |
| Peak memory | 219396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3327346671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3327346671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.870378736 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 1102737260 ps |
| CPU time | 3.53 seconds |
| Started | Oct 09 11:02:32 PM UTC 24 |
| Finished | Oct 09 11:02:36 PM UTC 24 |
| Peak memory | 219536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=870378736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.870378736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1347915115 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 423178500 ps |
| CPU time | 6.32 seconds |
| Started | Oct 09 11:02:30 PM UTC 24 |
| Finished | Oct 09 11:02:38 PM UTC 24 |
| Peak memory | 219248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1347915115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1347915115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.4055906741 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 245970876 ps |
| CPU time | 3.55 seconds |
| Started | Oct 09 11:02:30 PM UTC 24 |
| Finished | Oct 09 11:02:35 PM UTC 24 |
| Peak memory | 221704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4055906741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.4055906741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3496036090 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 48226086 ps |
| CPU time | 1.98 seconds |
| Started | Oct 09 11:02:32 PM UTC 24 |
| Finished | Oct 09 11:02:35 PM UTC 24 |
| Peak memory | 230448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496036090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3496036090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2840755580 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 130307665 ps |
| CPU time | 1.71 seconds |
| Started | Oct 09 11:02:30 PM UTC 24 |
| Finished | Oct 09 11:02:33 PM UTC 24 |
| Peak memory | 218136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2840755580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 7.lc_ctrl_jtag_csr_rw.2840755580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2216495139 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 300428884 ps |
| CPU time | 1.97 seconds |
| Started | Oct 09 11:02:32 PM UTC 24 |
| Finished | Oct 09 11:02:35 PM UTC 24 |
| Peak memory | 218632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2216495139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2216495139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4031325378 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 38884890 ps |
| CPU time | 1.86 seconds |
| Started | Oct 09 11:02:32 PM UTC 24 |
| Finished | Oct 09 11:02:35 PM UTC 24 |
| Peak memory | 220624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403132 5378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc _ctrl_same_csr_outstanding.4031325378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.956680910 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 48870254 ps |
| CPU time | 1.99 seconds |
| Started | Oct 09 11:02:32 PM UTC 24 |
| Finished | Oct 09 11:02:35 PM UTC 24 |
| Peak memory | 228460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956680910 -assert nopostpro c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.956680910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3874279415 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 170523649 ps |
| CPU time | 2.39 seconds |
| Started | Oct 09 11:02:32 PM UTC 24 |
| Finished | Oct 09 11:02:36 PM UTC 24 |
| Peak memory | 229980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874279415 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_ intg_err.3874279415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3457777017 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 56791397 ps |
| CPU time | 1.61 seconds |
| Started | Oct 09 11:02:36 PM UTC 24 |
| Finished | Oct 09 11:02:38 PM UTC 24 |
| Peak memory | 228404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=3457777017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3457777017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3064042640 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 20266586 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 11:02:35 PM UTC 24 |
| Finished | Oct 09 11:02:38 PM UTC 24 |
| Peak memory | 218096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064042640 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3064042640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.80285212 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 47511199 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 11:02:34 PM UTC 24 |
| Finished | Oct 09 11:02:37 PM UTC 24 |
| Peak memory | 218808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=80285212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.lc_ctrl_jtag_alert_test.80285212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2508519673 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 263175473 ps |
| CPU time | 4.46 seconds |
| Started | Oct 09 11:02:34 PM UTC 24 |
| Finished | Oct 09 11:02:40 PM UTC 24 |
| Peak memory | 219224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2508519673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2508519673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.770030163 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 839297861 ps |
| CPU time | 19.62 seconds |
| Started | Oct 09 11:02:34 PM UTC 24 |
| Finished | Oct 09 11:02:55 PM UTC 24 |
| Peak memory | 219276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=770030163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.770030163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.402756716 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 238370750 ps |
| CPU time | 1.94 seconds |
| Started | Oct 09 11:02:34 PM UTC 24 |
| Finished | Oct 09 11:02:37 PM UTC 24 |
| Peak memory | 220560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=402756716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.402756716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3946016476 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 431156436 ps |
| CPU time | 2.35 seconds |
| Started | Oct 09 11:02:34 PM UTC 24 |
| Finished | Oct 09 11:02:38 PM UTC 24 |
| Peak memory | 233792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946016476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_en abled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3946016476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1657071144 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 85422498 ps |
| CPU time | 1.4 seconds |
| Started | Oct 09 11:02:34 PM UTC 24 |
| Finished | Oct 09 11:02:36 PM UTC 24 |
| Peak memory | 218804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1657071144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 8.lc_ctrl_jtag_csr_rw.1657071144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1110916713 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 79839384 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 11:02:34 PM UTC 24 |
| Finished | Oct 09 11:02:37 PM UTC 24 |
| Peak memory | 220692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1110916713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1110916713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2384139154 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 16016827 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 11:02:35 PM UTC 24 |
| Finished | Oct 09 11:02:38 PM UTC 24 |
| Peak memory | 218576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238413 9154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc _ctrl_same_csr_outstanding.2384139154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3804678393 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 29139236 ps |
| CPU time | 2.34 seconds |
| Started | Oct 09 11:02:34 PM UTC 24 |
| Finished | Oct 09 11:02:38 PM UTC 24 |
| Peak memory | 231684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804678393 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3804678393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1263068242 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 86647836 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 11:02:37 PM UTC 24 |
| Finished | Oct 09 11:02:41 PM UTC 24 |
| Peak memory | 229700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/to ols/sim.tcl +ntb_random_seed=1263068242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1263068242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1162157143 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 16770727 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 11:02:37 PM UTC 24 |
| Finished | Oct 09 11:02:40 PM UTC 24 |
| Peak memory | 218156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162157143 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1162157143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.877499476 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 123843267 ps |
| CPU time | 2.57 seconds |
| Started | Oct 09 11:02:37 PM UTC 24 |
| Finished | Oct 09 11:02:41 PM UTC 24 |
| Peak memory | 219064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +cr eate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=877499476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.lc_ctrl_jtag_alert_test.877499476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.931602614 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 514589491 ps |
| CPU time | 5.88 seconds |
| Started | Oct 09 11:02:36 PM UTC 24 |
| Finished | Oct 09 11:02:43 PM UTC 24 |
| Peak memory | 219432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=931602614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.931602614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2126480423 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 2456284204 ps |
| CPU time | 12.32 seconds |
| Started | Oct 09 11:02:36 PM UTC 24 |
| Finished | Oct 09 11:02:49 PM UTC 24 |
| Peak memory | 219516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2126480423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2126480423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2679341418 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 1172217203 ps |
| CPU time | 2.76 seconds |
| Started | Oct 09 11:02:36 PM UTC 24 |
| Finished | Oct 09 11:02:39 PM UTC 24 |
| Peak memory | 221444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_ri scv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2679341418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2679341418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.741299429 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 148374716 ps |
| CPU time | 2.36 seconds |
| Started | Oct 09 11:02:37 PM UTC 24 |
| Finished | Oct 09 11:02:41 PM UTC 24 |
| Peak memory | 231684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_tim eout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741299429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_ena bled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.741299429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1375304618 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 254670263 ps |
| CPU time | 2.38 seconds |
| Started | Oct 09 11:02:36 PM UTC 24 |
| Finished | Oct 09 11:02:39 PM UTC 24 |
| Peak memory | 219656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_ma p=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1375304618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 9.lc_ctrl_jtag_csr_rw.1375304618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1629047624 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 24541790 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 11:02:36 PM UTC 24 |
| Finished | Oct 09 11:02:38 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +cr eate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1629047624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1629047624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3193866921 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 23242419 ps |
| CPU time | 1.56 seconds |
| Started | Oct 09 11:02:37 PM UTC 24 |
| Finished | Oct 09 11:02:40 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319386 6921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc _ctrl_same_csr_outstanding.3193866921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3743041429 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 32152522 ps |
| CPU time | 2.45 seconds |
| Started | Oct 09 11:02:37 PM UTC 24 |
| Finished | Oct 09 11:02:41 PM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743041429 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3743041429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.82369393 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 34810785 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:55:30 PM UTC 24 |
| Finished | Oct 09 10:55:33 PM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82369393 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.82369393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.69076291 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 147638290 ps |
| CPU time | 1.82 seconds |
| Started | Oct 09 10:55:34 PM UTC 24 |
| Finished | Oct 09 10:55:37 PM UTC 24 |
| Peak memory | 228104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69076291 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.69076291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.89777823 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2238711364 ps |
| CPU time | 62.22 seconds |
| Started | Oct 09 10:55:34 PM UTC 24 |
| Finished | Oct 09 10:56:38 PM UTC 24 |
| Peak memory | 238164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89777823 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag _errors.89777823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3995150999 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 737867721 ps |
| CPU time | 8.31 seconds |
| Started | Oct 09 10:55:34 PM UTC 24 |
| Finished | Oct 09 10:55:44 PM UTC 24 |
| Peak memory | 230040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995150999 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_prior ity.3995150999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.3896042704 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3368507727 ps |
| CPU time | 7.07 seconds |
| Started | Oct 09 10:55:32 PM UTC 24 |
| Finished | Oct 09 10:55:40 PM UTC 24 |
| Peak memory | 226008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896042704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_s moke.3896042704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3149470528 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 127872956 ps |
| CPU time | 2.82 seconds |
| Started | Oct 09 10:55:29 PM UTC 24 |
| Finished | Oct 09 10:55:33 PM UTC 24 |
| Peak memory | 234704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149470528 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3149470528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.430929718 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1240734994 ps |
| CPU time | 15.14 seconds |
| Started | Oct 09 10:55:30 PM UTC 24 |
| Finished | Oct 09 10:55:47 PM UTC 24 |
| Peak memory | 226032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430929718 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.430929718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2943478949 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 329871259 ps |
| CPU time | 13.14 seconds |
| Started | Oct 09 10:55:36 PM UTC 24 |
| Finished | Oct 09 10:55:50 PM UTC 24 |
| Peak memory | 238168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943478949 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2943478949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.490312072 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 4897653566 ps |
| CPU time | 13.61 seconds |
| Started | Oct 09 10:55:38 PM UTC 24 |
| Finished | Oct 09 10:55:53 PM UTC 24 |
| Peak memory | 230460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490312072 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_toke n_digest.490312072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.2697551316 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 38721559 ps |
| CPU time | 1.76 seconds |
| Started | Oct 09 10:55:27 PM UTC 24 |
| Finished | Oct 09 10:55:30 PM UTC 24 |
| Peak memory | 222396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697551316 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2697551316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.3380499455 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 141887410 ps |
| CPU time | 14.59 seconds |
| Started | Oct 09 10:55:28 PM UTC 24 |
| Finished | Oct 09 10:55:44 PM UTC 24 |
| Peak memory | 260860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380499455 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3380499455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.44605437 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 12059017344 ps |
| CPU time | 337.31 seconds |
| Started | Oct 09 10:55:40 PM UTC 24 |
| Finished | Oct 09 11:01:22 PM UTC 24 |
| Peak memory | 273440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=44605437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.lc_ctrl_stress_all.44605437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.3774887304 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 17909457 ps |
| CPU time | 1.35 seconds |
| Started | Oct 09 10:56:07 PM UTC 24 |
| Finished | Oct 09 10:56:10 PM UTC 24 |
| Peak memory | 218660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774887304 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3774887304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.2784875536 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 27334307 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 10:55:51 PM UTC 24 |
| Finished | Oct 09 10:55:54 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784875536 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2784875536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.1468508484 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1310856553 ps |
| CPU time | 15.07 seconds |
| Started | Oct 09 10:55:50 PM UTC 24 |
| Finished | Oct 09 10:56:06 PM UTC 24 |
| Peak memory | 238028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468508484 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1468508484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.2469830428 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 11593412467 ps |
| CPU time | 55.11 seconds |
| Started | Oct 09 10:55:55 PM UTC 24 |
| Finished | Oct 09 10:56:52 PM UTC 24 |
| Peak memory | 238084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469830428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jt ag_errors.2469830428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.1974761555 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2844840530 ps |
| CPU time | 39.46 seconds |
| Started | Oct 09 10:55:56 PM UTC 24 |
| Finished | Oct 09 10:56:37 PM UTC 24 |
| Peak memory | 230244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974761555 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_prior ity.1974761555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.3743039168 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 638413246 ps |
| CPU time | 23.77 seconds |
| Started | Oct 09 10:55:54 PM UTC 24 |
| Finished | Oct 09 10:56:19 PM UTC 24 |
| Peak memory | 236680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743039168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl _jtag_prog_failure.3743039168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2073905757 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 807558731 ps |
| CPU time | 14.96 seconds |
| Started | Oct 09 10:55:59 PM UTC 24 |
| Finished | Oct 09 10:56:15 PM UTC 24 |
| Peak memory | 224192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073905757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ ctrl_jtag_regwen_during_op.2073905757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3508388368 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 824190085 ps |
| CPU time | 5.58 seconds |
| Started | Oct 09 10:55:51 PM UTC 24 |
| Finished | Oct 09 10:55:58 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508388368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_s moke.3508388368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.1638233302 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2429751502 ps |
| CPU time | 54.46 seconds |
| Started | Oct 09 10:55:53 PM UTC 24 |
| Finished | Oct 09 10:56:49 PM UTC 24 |
| Peak memory | 263272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638233302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr l_jtag_state_failure.1638233302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.2797892865 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 277897897 ps |
| CPU time | 3.45 seconds |
| Started | Oct 09 10:55:50 PM UTC 24 |
| Finished | Oct 09 10:55:55 PM UTC 24 |
| Peak memory | 234512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797892865 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2797892865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.374459949 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 525033455 ps |
| CPU time | 12.85 seconds |
| Started | Oct 09 10:55:50 PM UTC 24 |
| Finished | Oct 09 10:56:04 PM UTC 24 |
| Peak memory | 230120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374459949 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.374459949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.2207245432 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 775008693 ps |
| CPU time | 38.11 seconds |
| Started | Oct 09 10:56:05 PM UTC 24 |
| Finished | Oct 09 10:56:45 PM UTC 24 |
| Peak memory | 290116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207245432 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2207245432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.197237411 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 994688967 ps |
| CPU time | 8.51 seconds |
| Started | Oct 09 10:56:05 PM UTC 24 |
| Finished | Oct 09 10:56:14 PM UTC 24 |
| Peak memory | 230664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197237411 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_toke n_digest.197237411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.2161279346 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1415643786 ps |
| CPU time | 12.68 seconds |
| Started | Oct 09 10:56:01 PM UTC 24 |
| Finished | Oct 09 10:56:15 PM UTC 24 |
| Peak memory | 237956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161279346 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_ mux.2161279346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.929630869 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 126636397 ps |
| CPU time | 4.42 seconds |
| Started | Oct 09 10:55:45 PM UTC 24 |
| Finished | Oct 09 10:55:51 PM UTC 24 |
| Peak memory | 226028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929630869 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.929630869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.95978059 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 189741835 ps |
| CPU time | 20.84 seconds |
| Started | Oct 09 10:55:48 PM UTC 24 |
| Finished | Oct 09 10:56:10 PM UTC 24 |
| Peak memory | 258972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95978059 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.95978059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.141907898 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 14825446 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:57:57 PM UTC 24 |
| Finished | Oct 09 10:57:59 PM UTC 24 |
| Peak memory | 218960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141907898 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.141907898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.1138024786 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1185355536 ps |
| CPU time | 9.51 seconds |
| Started | Oct 09 10:57:53 PM UTC 24 |
| Finished | Oct 09 10:58:04 PM UTC 24 |
| Peak memory | 238108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138024786 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1138024786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.1492099258 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 1028688695 ps |
| CPU time | 6.28 seconds |
| Started | Oct 09 10:57:57 PM UTC 24 |
| Finished | Oct 09 10:58:04 PM UTC 24 |
| Peak memory | 229096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492099258 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1492099258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.2265748750 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 8279567689 ps |
| CPU time | 35.47 seconds |
| Started | Oct 09 10:57:55 PM UTC 24 |
| Finished | Oct 09 10:58:32 PM UTC 24 |
| Peak memory | 238152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265748750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_j tag_errors.2265748750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.1004414273 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 293997613 ps |
| CPU time | 7.71 seconds |
| Started | Oct 09 10:57:55 PM UTC 24 |
| Finished | Oct 09 10:58:04 PM UTC 24 |
| Peak memory | 230276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004414273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctr l_jtag_prog_failure.1004414273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.1650793923 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 416690508 ps |
| CPU time | 9.11 seconds |
| Started | Oct 09 10:57:54 PM UTC 24 |
| Finished | Oct 09 10:58:05 PM UTC 24 |
| Peak memory | 230056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650793923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_ smoke.1650793923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.4043715968 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1800331911 ps |
| CPU time | 66.77 seconds |
| Started | Oct 09 10:57:55 PM UTC 24 |
| Finished | Oct 09 10:59:03 PM UTC 24 |
| Peak memory | 283744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043715968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct rl_jtag_state_failure.4043715968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.2608835410 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 4994211596 ps |
| CPU time | 9.27 seconds |
| Started | Oct 09 10:57:55 PM UTC 24 |
| Finished | Oct 09 10:58:05 PM UTC 24 |
| Peak memory | 236940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608835410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc _ctrl_jtag_state_post_trans.2608835410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.4132763096 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 113693003 ps |
| CPU time | 2.66 seconds |
| Started | Oct 09 10:57:53 PM UTC 24 |
| Finished | Oct 09 10:57:57 PM UTC 24 |
| Peak memory | 234504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132763096 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.4132763096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.431365038 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 208988449 ps |
| CPU time | 9.2 seconds |
| Started | Oct 09 10:57:57 PM UTC 24 |
| Finished | Oct 09 10:58:07 PM UTC 24 |
| Peak memory | 230344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431365038 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.431365038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.1900496440 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 713831298 ps |
| CPU time | 10.83 seconds |
| Started | Oct 09 10:57:57 PM UTC 24 |
| Finished | Oct 09 10:58:09 PM UTC 24 |
| Peak memory | 230268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900496440 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_to ken_digest.1900496440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.3069290073 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 828713328 ps |
| CPU time | 9.82 seconds |
| Started | Oct 09 10:57:57 PM UTC 24 |
| Finished | Oct 09 10:58:08 PM UTC 24 |
| Peak memory | 238024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069290073 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token _mux.3069290073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.2435589981 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 251424176 ps |
| CPU time | 7.09 seconds |
| Started | Oct 09 10:57:54 PM UTC 24 |
| Finished | Oct 09 10:58:03 PM UTC 24 |
| Peak memory | 230484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435589981 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2435589981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.600226082 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 79030542 ps |
| CPU time | 2.88 seconds |
| Started | Oct 09 10:57:52 PM UTC 24 |
| Finished | Oct 09 10:57:55 PM UTC 24 |
| Peak memory | 226108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600226082 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.600226082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.2096121296 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 81993827 ps |
| CPU time | 6.9 seconds |
| Started | Oct 09 10:57:53 PM UTC 24 |
| Finished | Oct 09 10:58:01 PM UTC 24 |
| Peak memory | 262948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096121296 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2096121296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.1895216257 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 3110083755 ps |
| CPU time | 55.22 seconds |
| Started | Oct 09 10:57:57 PM UTC 24 |
| Finished | Oct 09 10:58:54 PM UTC 24 |
| Peak memory | 263204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1895216257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 10.lc_ctrl_stress_all.1895216257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3737593241 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 13181190 ps |
| CPU time | 1.34 seconds |
| Started | Oct 09 10:57:52 PM UTC 24 |
| Finished | Oct 09 10:57:55 PM UTC 24 |
| Peak memory | 218844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737593241 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10 .lc_ctrl_volatile_unlock_smoke.3737593241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/10.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.2749516095 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 50838836 ps |
| CPU time | 1.34 seconds |
| Started | Oct 09 10:58:05 PM UTC 24 |
| Finished | Oct 09 10:58:08 PM UTC 24 |
| Peak memory | 218960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749516095 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2749516095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.3590018732 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 989984071 ps |
| CPU time | 20.2 seconds |
| Started | Oct 09 10:57:59 PM UTC 24 |
| Finished | Oct 09 10:58:20 PM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590018732 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3590018732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.2760331571 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4217181341 ps |
| CPU time | 13.61 seconds |
| Started | Oct 09 10:58:01 PM UTC 24 |
| Finished | Oct 09 10:58:16 PM UTC 24 |
| Peak memory | 230108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760331571 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2760331571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.4088492134 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 10667586106 ps |
| CPU time | 38.62 seconds |
| Started | Oct 09 10:58:01 PM UTC 24 |
| Finished | Oct 09 10:58:41 PM UTC 24 |
| Peak memory | 232720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088492134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_j tag_errors.4088492134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.256672607 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1959440230 ps |
| CPU time | 13.93 seconds |
| Started | Oct 09 10:58:01 PM UTC 24 |
| Finished | Oct 09 10:58:17 PM UTC 24 |
| Peak memory | 236680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256672607 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl _jtag_prog_failure.256672607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.1467459168 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 204870645 ps |
| CPU time | 5.98 seconds |
| Started | Oct 09 10:58:00 PM UTC 24 |
| Finished | Oct 09 10:58:07 PM UTC 24 |
| Peak memory | 230128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467459168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_ smoke.1467459168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.2030873428 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2812760845 ps |
| CPU time | 38.9 seconds |
| Started | Oct 09 10:58:00 PM UTC 24 |
| Finished | Oct 09 10:58:40 PM UTC 24 |
| Peak memory | 281820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030873428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct rl_jtag_state_failure.2030873428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.2729725280 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2046712522 ps |
| CPU time | 24.35 seconds |
| Started | Oct 09 10:58:00 PM UTC 24 |
| Finished | Oct 09 10:58:26 PM UTC 24 |
| Peak memory | 263200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729725280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc _ctrl_jtag_state_post_trans.2729725280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.122035424 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 91321643 ps |
| CPU time | 2.26 seconds |
| Started | Oct 09 10:57:59 PM UTC 24 |
| Finished | Oct 09 10:58:02 PM UTC 24 |
| Peak memory | 234480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122035424 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.122035424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.80599166 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 687818339 ps |
| CPU time | 10.33 seconds |
| Started | Oct 09 10:58:02 PM UTC 24 |
| Finished | Oct 09 10:58:13 PM UTC 24 |
| Peak memory | 230264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80599166 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.80599166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.2692141577 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 959280292 ps |
| CPU time | 16.93 seconds |
| Started | Oct 09 10:58:03 PM UTC 24 |
| Finished | Oct 09 10:58:21 PM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692141577 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_to ken_digest.2692141577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.1700227572 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2956174061 ps |
| CPU time | 10.43 seconds |
| Started | Oct 09 10:58:03 PM UTC 24 |
| Finished | Oct 09 10:58:14 PM UTC 24 |
| Peak memory | 230728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700227572 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token _mux.1700227572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.3936070630 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 110007558 ps |
| CPU time | 2.61 seconds |
| Started | Oct 09 10:57:57 PM UTC 24 |
| Finished | Oct 09 10:58:01 PM UTC 24 |
| Peak memory | 225952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936070630 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3936070630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.1745904605 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 328298864 ps |
| CPU time | 25.97 seconds |
| Started | Oct 09 10:57:59 PM UTC 24 |
| Finished | Oct 09 10:58:26 PM UTC 24 |
| Peak memory | 263068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745904605 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1745904605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.1644027903 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 296069592 ps |
| CPU time | 9.06 seconds |
| Started | Oct 09 10:57:59 PM UTC 24 |
| Finished | Oct 09 10:58:09 PM UTC 24 |
| Peak memory | 258816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644027903 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1644027903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.1841276770 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 41442966545 ps |
| CPU time | 309.8 seconds |
| Started | Oct 09 10:58:04 PM UTC 24 |
| Finished | Oct 09 11:03:18 PM UTC 24 |
| Peak memory | 289752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1841276770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 11.lc_ctrl_stress_all.1841276770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.108430054 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 45306971 ps |
| CPU time | 1.12 seconds |
| Started | Oct 09 10:57:58 PM UTC 24 |
| Finished | Oct 09 10:58:01 PM UTC 24 |
| Peak memory | 220776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108430054 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11. lc_ctrl_volatile_unlock_smoke.108430054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.2800960937 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 145148810 ps |
| CPU time | 1.51 seconds |
| Started | Oct 09 10:58:11 PM UTC 24 |
| Finished | Oct 09 10:58:14 PM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800960937 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2800960937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.3150992639 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 736502217 ps |
| CPU time | 7.34 seconds |
| Started | Oct 09 10:58:07 PM UTC 24 |
| Finished | Oct 09 10:58:15 PM UTC 24 |
| Peak memory | 238180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150992639 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3150992639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.1424640799 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1148216058 ps |
| CPU time | 9.19 seconds |
| Started | Oct 09 10:58:10 PM UTC 24 |
| Finished | Oct 09 10:58:20 PM UTC 24 |
| Peak memory | 229596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424640799 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1424640799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.4237161848 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2594978560 ps |
| CPU time | 45.41 seconds |
| Started | Oct 09 10:58:10 PM UTC 24 |
| Finished | Oct 09 10:58:57 PM UTC 24 |
| Peak memory | 238076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237161848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_j tag_errors.4237161848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.2435877866 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 973133781 ps |
| CPU time | 17.64 seconds |
| Started | Oct 09 10:58:10 PM UTC 24 |
| Finished | Oct 09 10:58:29 PM UTC 24 |
| Peak memory | 230344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435877866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctr l_jtag_prog_failure.2435877866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.3684947929 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 365357171 ps |
| CPU time | 7.61 seconds |
| Started | Oct 09 10:58:08 PM UTC 24 |
| Finished | Oct 09 10:58:17 PM UTC 24 |
| Peak memory | 229908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684947929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_ smoke.3684947929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.2833820098 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1587995607 ps |
| CPU time | 53.43 seconds |
| Started | Oct 09 10:58:08 PM UTC 24 |
| Finished | Oct 09 10:59:03 PM UTC 24 |
| Peak memory | 263204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833820098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct rl_jtag_state_failure.2833820098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.154840064 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1820936338 ps |
| CPU time | 18.91 seconds |
| Started | Oct 09 10:58:10 PM UTC 24 |
| Finished | Oct 09 10:58:30 PM UTC 24 |
| Peak memory | 263188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154840064 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ ctrl_jtag_state_post_trans.154840064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.1860927924 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 50327292 ps |
| CPU time | 3.41 seconds |
| Started | Oct 09 10:58:06 PM UTC 24 |
| Finished | Oct 09 10:58:10 PM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860927924 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1860927924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.343114979 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 707341171 ps |
| CPU time | 17.13 seconds |
| Started | Oct 09 10:58:10 PM UTC 24 |
| Finished | Oct 09 10:58:28 PM UTC 24 |
| Peak memory | 238108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343114979 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.343114979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.2887286949 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 758548587 ps |
| CPU time | 7.57 seconds |
| Started | Oct 09 10:58:11 PM UTC 24 |
| Finished | Oct 09 10:58:20 PM UTC 24 |
| Peak memory | 237236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887286949 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_to ken_digest.2887286949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.1464354863 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 270378288 ps |
| CPU time | 7.57 seconds |
| Started | Oct 09 10:58:10 PM UTC 24 |
| Finished | Oct 09 10:58:19 PM UTC 24 |
| Peak memory | 238016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464354863 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token _mux.1464354863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.3668547923 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 723827779 ps |
| CPU time | 11.77 seconds |
| Started | Oct 09 10:58:08 PM UTC 24 |
| Finished | Oct 09 10:58:21 PM UTC 24 |
| Peak memory | 238104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668547923 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3668547923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.923466477 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 84357409 ps |
| CPU time | 2.76 seconds |
| Started | Oct 09 10:58:06 PM UTC 24 |
| Finished | Oct 09 10:58:09 PM UTC 24 |
| Peak memory | 224060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923466477 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.923466477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.2166832329 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 896397089 ps |
| CPU time | 29.04 seconds |
| Started | Oct 09 10:58:06 PM UTC 24 |
| Finished | Oct 09 10:58:36 PM UTC 24 |
| Peak memory | 263372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166832329 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2166832329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.246315688 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 82594491 ps |
| CPU time | 8.56 seconds |
| Started | Oct 09 10:58:06 PM UTC 24 |
| Finished | Oct 09 10:58:16 PM UTC 24 |
| Peak memory | 263272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246315688 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.246315688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.2524664433 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 9924014676 ps |
| CPU time | 185.02 seconds |
| Started | Oct 09 10:58:11 PM UTC 24 |
| Finished | Oct 09 11:01:19 PM UTC 24 |
| Peak memory | 300000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2524664433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 12.lc_ctrl_stress_all.2524664433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.708268154 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1131631050 ps |
| CPU time | 38.51 seconds |
| Started | Oct 09 10:58:11 PM UTC 24 |
| Finished | Oct 09 10:58:51 PM UTC 24 |
| Peak memory | 263484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708268154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.708268154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1961256252 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 24351678 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 10:58:06 PM UTC 24 |
| Finished | Oct 09 10:58:08 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961256252 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12 .lc_ctrl_volatile_unlock_smoke.1961256252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.1036371359 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 43114005 ps |
| CPU time | 1.37 seconds |
| Started | Oct 09 10:58:20 PM UTC 24 |
| Finished | Oct 09 10:58:22 PM UTC 24 |
| Peak memory | 218664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036371359 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1036371359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.853283884 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 865684436 ps |
| CPU time | 22.7 seconds |
| Started | Oct 09 10:58:14 PM UTC 24 |
| Finished | Oct 09 10:58:38 PM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853283884 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.853283884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.1474352208 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 577521551 ps |
| CPU time | 2.83 seconds |
| Started | Oct 09 10:58:17 PM UTC 24 |
| Finished | Oct 09 10:58:21 PM UTC 24 |
| Peak memory | 229276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474352208 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1474352208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.2898492880 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 7335667701 ps |
| CPU time | 36.02 seconds |
| Started | Oct 09 10:58:17 PM UTC 24 |
| Finished | Oct 09 10:58:55 PM UTC 24 |
| Peak memory | 238196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898492880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_j tag_errors.2898492880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.2692972713 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 461769364 ps |
| CPU time | 14.43 seconds |
| Started | Oct 09 10:58:16 PM UTC 24 |
| Finished | Oct 09 10:58:32 PM UTC 24 |
| Peak memory | 236680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692972713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctr l_jtag_prog_failure.2692972713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.3897882796 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 755636630 ps |
| CPU time | 9.17 seconds |
| Started | Oct 09 10:58:16 PM UTC 24 |
| Finished | Oct 09 10:58:26 PM UTC 24 |
| Peak memory | 223920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897882796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_ smoke.3897882796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.1550026048 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 914786370 ps |
| CPU time | 39.22 seconds |
| Started | Oct 09 10:58:16 PM UTC 24 |
| Finished | Oct 09 10:58:57 PM UTC 24 |
| Peak memory | 263016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550026048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct rl_jtag_state_failure.1550026048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.3043295220 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 7657089477 ps |
| CPU time | 36.94 seconds |
| Started | Oct 09 10:58:16 PM UTC 24 |
| Finished | Oct 09 10:58:54 PM UTC 24 |
| Peak memory | 263060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043295220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc _ctrl_jtag_state_post_trans.3043295220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.2504194012 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 69833073 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 10:58:13 PM UTC 24 |
| Finished | Oct 09 10:58:18 PM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504194012 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2504194012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.2694779930 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1893227057 ps |
| CPU time | 12.5 seconds |
| Started | Oct 09 10:58:17 PM UTC 24 |
| Finished | Oct 09 10:58:31 PM UTC 24 |
| Peak memory | 232316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694779930 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2694779930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.75709512 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 927504407 ps |
| CPU time | 8.04 seconds |
| Started | Oct 09 10:58:18 PM UTC 24 |
| Finished | Oct 09 10:58:27 PM UTC 24 |
| Peak memory | 230336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75709512 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_toke n_digest.75709512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.1071113962 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 873674073 ps |
| CPU time | 9.19 seconds |
| Started | Oct 09 10:58:18 PM UTC 24 |
| Finished | Oct 09 10:58:28 PM UTC 24 |
| Peak memory | 230672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071113962 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token _mux.1071113962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.1295199415 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 3235582816 ps |
| CPU time | 16.09 seconds |
| Started | Oct 09 10:58:16 PM UTC 24 |
| Finished | Oct 09 10:58:33 PM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295199415 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.1295199415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.557982937 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 298279222 ps |
| CPU time | 2.93 seconds |
| Started | Oct 09 10:58:11 PM UTC 24 |
| Finished | Oct 09 10:58:16 PM UTC 24 |
| Peak memory | 226112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557982937 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.557982937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.421717013 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 308091890 ps |
| CPU time | 20.79 seconds |
| Started | Oct 09 10:58:13 PM UTC 24 |
| Finished | Oct 09 10:58:35 PM UTC 24 |
| Peak memory | 263208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421717013 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.421717013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.2996968269 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 57191012 ps |
| CPU time | 10.16 seconds |
| Started | Oct 09 10:58:13 PM UTC 24 |
| Finished | Oct 09 10:58:25 PM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996968269 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2996968269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.1634063088 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 32909456043 ps |
| CPU time | 205.03 seconds |
| Started | Oct 09 10:58:18 PM UTC 24 |
| Finished | Oct 09 11:01:46 PM UTC 24 |
| Peak memory | 265180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1634063088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 13.lc_ctrl_stress_all.1634063088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2869367140 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 4272800027 ps |
| CPU time | 53.92 seconds |
| Started | Oct 09 10:58:19 PM UTC 24 |
| Finished | Oct 09 10:59:14 PM UTC 24 |
| Peak memory | 283900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869367140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2869367140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3537199750 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 76878977 ps |
| CPU time | 1.39 seconds |
| Started | Oct 09 10:58:12 PM UTC 24 |
| Finished | Oct 09 10:58:14 PM UTC 24 |
| Peak memory | 222820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537199750 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13 .lc_ctrl_volatile_unlock_smoke.3537199750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/13.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.3008041159 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 16623534 ps |
| CPU time | 1.4 seconds |
| Started | Oct 09 10:58:30 PM UTC 24 |
| Finished | Oct 09 10:58:32 PM UTC 24 |
| Peak memory | 218304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008041159 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3008041159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_errors.3490448992 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 942866940 ps |
| CPU time | 12.31 seconds |
| Started | Oct 09 10:58:23 PM UTC 24 |
| Finished | Oct 09 10:58:36 PM UTC 24 |
| Peak memory | 237832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490448992 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3490448992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.3949284379 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 150168410 ps |
| CPU time | 4.06 seconds |
| Started | Oct 09 10:58:27 PM UTC 24 |
| Finished | Oct 09 10:58:32 PM UTC 24 |
| Peak memory | 229356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949284379 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3949284379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.2382454423 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2103310493 ps |
| CPU time | 32 seconds |
| Started | Oct 09 10:58:27 PM UTC 24 |
| Finished | Oct 09 10:59:00 PM UTC 24 |
| Peak memory | 230396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382454423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_j tag_errors.2382454423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.2310340675 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 226120195 ps |
| CPU time | 7.32 seconds |
| Started | Oct 09 10:58:25 PM UTC 24 |
| Finished | Oct 09 10:58:34 PM UTC 24 |
| Peak memory | 234364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310340675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctr l_jtag_prog_failure.2310340675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.1438534589 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 391181282 ps |
| CPU time | 5.63 seconds |
| Started | Oct 09 10:58:23 PM UTC 24 |
| Finished | Oct 09 10:58:30 PM UTC 24 |
| Peak memory | 230296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438534589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_ smoke.1438534589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.229058258 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3964920005 ps |
| CPU time | 47.58 seconds |
| Started | Oct 09 10:58:25 PM UTC 24 |
| Finished | Oct 09 10:59:14 PM UTC 24 |
| Peak memory | 287652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229058258 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctr l_jtag_state_failure.229058258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.1777973867 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3440897202 ps |
| CPU time | 23.38 seconds |
| Started | Oct 09 10:58:25 PM UTC 24 |
| Finished | Oct 09 10:58:50 PM UTC 24 |
| Peak memory | 263328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777973867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc _ctrl_jtag_state_post_trans.1777973867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.1252841561 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 139808975 ps |
| CPU time | 2.51 seconds |
| Started | Oct 09 10:58:23 PM UTC 24 |
| Finished | Oct 09 10:58:26 PM UTC 24 |
| Peak memory | 234696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252841561 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1252841561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.375928964 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 431971726 ps |
| CPU time | 16.82 seconds |
| Started | Oct 09 10:58:27 PM UTC 24 |
| Finished | Oct 09 10:58:45 PM UTC 24 |
| Peak memory | 238068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375928964 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.375928964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.980922736 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 304894434 ps |
| CPU time | 9.55 seconds |
| Started | Oct 09 10:58:28 PM UTC 24 |
| Finished | Oct 09 10:58:39 PM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980922736 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_tok en_digest.980922736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.925672858 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 357651241 ps |
| CPU time | 9.83 seconds |
| Started | Oct 09 10:58:27 PM UTC 24 |
| Finished | Oct 09 10:58:38 PM UTC 24 |
| Peak memory | 238312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925672858 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_ mux.925672858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.435422936 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 877162842 ps |
| CPU time | 8.29 seconds |
| Started | Oct 09 10:58:23 PM UTC 24 |
| Finished | Oct 09 10:58:33 PM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435422936 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.435422936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.3849215387 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 39715095 ps |
| CPU time | 2.97 seconds |
| Started | Oct 09 10:58:21 PM UTC 24 |
| Finished | Oct 09 10:58:25 PM UTC 24 |
| Peak memory | 226132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849215387 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3849215387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.3322510111 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 182030035 ps |
| CPU time | 19.24 seconds |
| Started | Oct 09 10:58:21 PM UTC 24 |
| Finished | Oct 09 10:58:42 PM UTC 24 |
| Peak memory | 258908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322510111 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3322510111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.413927840 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 101587635 ps |
| CPU time | 11.61 seconds |
| Started | Oct 09 10:58:23 PM UTC 24 |
| Finished | Oct 09 10:58:35 PM UTC 24 |
| Peak memory | 263016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413927840 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.413927840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.3333259832 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 31542106659 ps |
| CPU time | 150.39 seconds |
| Started | Oct 09 10:58:28 PM UTC 24 |
| Finished | Oct 09 11:01:01 PM UTC 24 |
| Peak memory | 295900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3333259832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 14.lc_ctrl_stress_all.3333259832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.2195042649 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2506777551 ps |
| CPU time | 73.52 seconds |
| Started | Oct 09 10:58:28 PM UTC 24 |
| Finished | Oct 09 10:59:44 PM UTC 24 |
| Peak memory | 238284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195042649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.2195042649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.4264064726 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 11743600 ps |
| CPU time | 1.58 seconds |
| Started | Oct 09 10:58:21 PM UTC 24 |
| Finished | Oct 09 10:58:24 PM UTC 24 |
| Peak memory | 220772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264064726 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14 .lc_ctrl_volatile_unlock_smoke.4264064726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/14.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.4045323909 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 229296718 ps |
| CPU time | 1.39 seconds |
| Started | Oct 09 10:58:37 PM UTC 24 |
| Finished | Oct 09 10:58:39 PM UTC 24 |
| Peak memory | 218840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045323909 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.4045323909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.2011692088 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 264960124 ps |
| CPU time | 14.1 seconds |
| Started | Oct 09 10:58:33 PM UTC 24 |
| Finished | Oct 09 10:58:49 PM UTC 24 |
| Peak memory | 238032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011692088 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2011692088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.1919556280 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 403550355 ps |
| CPU time | 12.93 seconds |
| Started | Oct 09 10:58:34 PM UTC 24 |
| Finished | Oct 09 10:58:48 PM UTC 24 |
| Peak memory | 229652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919556280 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1919556280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.864940354 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 8430738526 ps |
| CPU time | 57.96 seconds |
| Started | Oct 09 10:58:34 PM UTC 24 |
| Finished | Oct 09 10:59:34 PM UTC 24 |
| Peak memory | 232444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864940354 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt ag_errors.864940354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.1020502947 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 331104946 ps |
| CPU time | 10.88 seconds |
| Started | Oct 09 10:58:34 PM UTC 24 |
| Finished | Oct 09 10:58:46 PM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020502947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctr l_jtag_prog_failure.1020502947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.4090846665 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 799818559 ps |
| CPU time | 6.56 seconds |
| Started | Oct 09 10:58:34 PM UTC 24 |
| Finished | Oct 09 10:58:41 PM UTC 24 |
| Peak memory | 230124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090846665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_ smoke.4090846665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.1668949926 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 3562340503 ps |
| CPU time | 48.21 seconds |
| Started | Oct 09 10:58:34 PM UTC 24 |
| Finished | Oct 09 10:59:24 PM UTC 24 |
| Peak memory | 263056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668949926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct rl_jtag_state_failure.1668949926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.37554056 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 411708242 ps |
| CPU time | 14.2 seconds |
| Started | Oct 09 10:58:34 PM UTC 24 |
| Finished | Oct 09 10:58:49 PM UTC 24 |
| Peak memory | 237952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37554056 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c trl_jtag_state_post_trans.37554056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.4119383112 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 56829465 ps |
| CPU time | 2.46 seconds |
| Started | Oct 09 10:58:32 PM UTC 24 |
| Finished | Oct 09 10:58:36 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119383112 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.4119383112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.2607234197 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2341294024 ps |
| CPU time | 10.57 seconds |
| Started | Oct 09 10:58:34 PM UTC 24 |
| Finished | Oct 09 10:58:46 PM UTC 24 |
| Peak memory | 230460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607234197 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2607234197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.3973004182 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1029746594 ps |
| CPU time | 10.95 seconds |
| Started | Oct 09 10:58:35 PM UTC 24 |
| Finished | Oct 09 10:58:48 PM UTC 24 |
| Peak memory | 230336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973004182 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_to ken_digest.3973004182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.3513348707 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 5239634536 ps |
| CPU time | 10.92 seconds |
| Started | Oct 09 10:58:35 PM UTC 24 |
| Finished | Oct 09 10:58:47 PM UTC 24 |
| Peak memory | 238144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513348707 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token _mux.3513348707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.3836678417 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 388835512 ps |
| CPU time | 9.56 seconds |
| Started | Oct 09 10:58:34 PM UTC 24 |
| Finished | Oct 09 10:58:44 PM UTC 24 |
| Peak memory | 238104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836678417 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3836678417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.2043088775 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 20227167 ps |
| CPU time | 1.97 seconds |
| Started | Oct 09 10:58:30 PM UTC 24 |
| Finished | Oct 09 10:58:33 PM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043088775 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2043088775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.4122815465 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 1701552843 ps |
| CPU time | 28.04 seconds |
| Started | Oct 09 10:58:31 PM UTC 24 |
| Finished | Oct 09 10:59:00 PM UTC 24 |
| Peak memory | 263268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122815465 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.4122815465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.1811256615 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 618977037 ps |
| CPU time | 11.19 seconds |
| Started | Oct 09 10:58:31 PM UTC 24 |
| Finished | Oct 09 10:58:43 PM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811256615 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1811256615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.3693606706 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 36712285639 ps |
| CPU time | 154.83 seconds |
| Started | Oct 09 10:58:36 PM UTC 24 |
| Finished | Oct 09 11:01:13 PM UTC 24 |
| Peak memory | 289896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3693606706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 15.lc_ctrl_stress_all.3693606706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3372224610 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 34539201 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 10:58:30 PM UTC 24 |
| Finished | Oct 09 10:58:32 PM UTC 24 |
| Peak memory | 220772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372224610 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15 .lc_ctrl_volatile_unlock_smoke.3372224610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.2238334553 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 69559146 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 10:58:44 PM UTC 24 |
| Finished | Oct 09 10:58:46 PM UTC 24 |
| Peak memory | 218960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238334553 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2238334553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.1638671702 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 879784727 ps |
| CPU time | 18.24 seconds |
| Started | Oct 09 10:58:39 PM UTC 24 |
| Finished | Oct 09 10:58:58 PM UTC 24 |
| Peak memory | 238300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638671702 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1638671702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.3682847882 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 4764543734 ps |
| CPU time | 27.94 seconds |
| Started | Oct 09 10:58:43 PM UTC 24 |
| Finished | Oct 09 10:59:12 PM UTC 24 |
| Peak memory | 230204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682847882 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3682847882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.4290345641 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2479503301 ps |
| CPU time | 65.21 seconds |
| Started | Oct 09 10:58:41 PM UTC 24 |
| Finished | Oct 09 10:59:48 PM UTC 24 |
| Peak memory | 232512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290345641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_j tag_errors.4290345641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.3573886146 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 98978563 ps |
| CPU time | 3.35 seconds |
| Started | Oct 09 10:58:41 PM UTC 24 |
| Finished | Oct 09 10:58:46 PM UTC 24 |
| Peak memory | 234444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573886146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctr l_jtag_prog_failure.3573886146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.3033520647 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1610967021 ps |
| CPU time | 6.87 seconds |
| Started | Oct 09 10:58:40 PM UTC 24 |
| Finished | Oct 09 10:58:48 PM UTC 24 |
| Peak memory | 223980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033520647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_ smoke.3033520647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.2671787953 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 4505448183 ps |
| CPU time | 47.45 seconds |
| Started | Oct 09 10:58:40 PM UTC 24 |
| Finished | Oct 09 10:59:29 PM UTC 24 |
| Peak memory | 287636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671787953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct rl_jtag_state_failure.2671787953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.2347298696 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1102818030 ps |
| CPU time | 15.25 seconds |
| Started | Oct 09 10:58:40 PM UTC 24 |
| Finished | Oct 09 10:58:57 PM UTC 24 |
| Peak memory | 262960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347298696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc _ctrl_jtag_state_post_trans.2347298696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.1853092250 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 84105391 ps |
| CPU time | 3.24 seconds |
| Started | Oct 09 10:58:39 PM UTC 24 |
| Finished | Oct 09 10:58:43 PM UTC 24 |
| Peak memory | 234696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853092250 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1853092250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.2476154206 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3279426741 ps |
| CPU time | 19.94 seconds |
| Started | Oct 09 10:58:43 PM UTC 24 |
| Finished | Oct 09 10:59:04 PM UTC 24 |
| Peak memory | 232652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476154206 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2476154206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.2463202420 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 667262858 ps |
| CPU time | 32.61 seconds |
| Started | Oct 09 10:58:43 PM UTC 24 |
| Finished | Oct 09 10:59:17 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463202420 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_to ken_digest.2463202420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.3722150423 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 353631657 ps |
| CPU time | 8.88 seconds |
| Started | Oct 09 10:58:43 PM UTC 24 |
| Finished | Oct 09 10:58:53 PM UTC 24 |
| Peak memory | 237332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722150423 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token _mux.3722150423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.172147620 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1497840173 ps |
| CPU time | 16.99 seconds |
| Started | Oct 09 10:58:40 PM UTC 24 |
| Finished | Oct 09 10:58:58 PM UTC 24 |
| Peak memory | 237272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172147620 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.172147620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.2573280866 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 142702084 ps |
| CPU time | 2.1 seconds |
| Started | Oct 09 10:58:37 PM UTC 24 |
| Finished | Oct 09 10:58:40 PM UTC 24 |
| Peak memory | 226364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573280866 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2573280866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.253260253 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 744793561 ps |
| CPU time | 29.88 seconds |
| Started | Oct 09 10:58:37 PM UTC 24 |
| Finished | Oct 09 10:59:08 PM UTC 24 |
| Peak memory | 263016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253260253 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.253260253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.964485821 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 420868689 ps |
| CPU time | 3.31 seconds |
| Started | Oct 09 10:58:37 PM UTC 24 |
| Finished | Oct 09 10:58:42 PM UTC 24 |
| Peak memory | 234908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964485821 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.964485821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.2280025922 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 11061049575 ps |
| CPU time | 110.71 seconds |
| Started | Oct 09 10:58:43 PM UTC 24 |
| Finished | Oct 09 11:00:36 PM UTC 24 |
| Peak memory | 232888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2280025922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 16.lc_ctrl_stress_all.2280025922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2406182661 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 5603944718 ps |
| CPU time | 65.11 seconds |
| Started | Oct 09 10:58:44 PM UTC 24 |
| Finished | Oct 09 10:59:51 PM UTC 24 |
| Peak memory | 265576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406182661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.2406182661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1417092872 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 19808153 ps |
| CPU time | 1.37 seconds |
| Started | Oct 09 10:58:37 PM UTC 24 |
| Finished | Oct 09 10:58:39 PM UTC 24 |
| Peak memory | 220768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417092872 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16 .lc_ctrl_volatile_unlock_smoke.1417092872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/16.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.538610155 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 62737628 ps |
| CPU time | 1.81 seconds |
| Started | Oct 09 10:58:53 PM UTC 24 |
| Finished | Oct 09 10:58:56 PM UTC 24 |
| Peak memory | 218660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538610155 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.538610155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.235287311 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 280335887 ps |
| CPU time | 10.12 seconds |
| Started | Oct 09 10:58:48 PM UTC 24 |
| Finished | Oct 09 10:58:59 PM UTC 24 |
| Peak memory | 237824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235287311 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.235287311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.1052144171 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 461297570 ps |
| CPU time | 9.96 seconds |
| Started | Oct 09 10:58:50 PM UTC 24 |
| Finished | Oct 09 10:59:01 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052144171 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1052144171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.3318238002 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1467110032 ps |
| CPU time | 37.38 seconds |
| Started | Oct 09 10:58:50 PM UTC 24 |
| Finished | Oct 09 10:59:28 PM UTC 24 |
| Peak memory | 237952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318238002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_j tag_errors.3318238002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.2720927620 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2225319962 ps |
| CPU time | 9.83 seconds |
| Started | Oct 09 10:58:50 PM UTC 24 |
| Finished | Oct 09 10:59:01 PM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720927620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctr l_jtag_prog_failure.2720927620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.321903426 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 800571997 ps |
| CPU time | 6.68 seconds |
| Started | Oct 09 10:58:48 PM UTC 24 |
| Finished | Oct 09 10:58:56 PM UTC 24 |
| Peak memory | 224180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321903426 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_s moke.321903426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.856663456 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1378939242 ps |
| CPU time | 42.53 seconds |
| Started | Oct 09 10:58:48 PM UTC 24 |
| Finished | Oct 09 10:59:32 PM UTC 24 |
| Peak memory | 281360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856663456 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctr l_jtag_state_failure.856663456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.1880764456 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2603192324 ps |
| CPU time | 16.41 seconds |
| Started | Oct 09 10:58:50 PM UTC 24 |
| Finished | Oct 09 10:59:07 PM UTC 24 |
| Peak memory | 238340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880764456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc _ctrl_jtag_state_post_trans.1880764456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.4076759335 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 59809604 ps |
| CPU time | 4.53 seconds |
| Started | Oct 09 10:58:47 PM UTC 24 |
| Finished | Oct 09 10:58:52 PM UTC 24 |
| Peak memory | 234504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076759335 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.4076759335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.3059934699 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 883294942 ps |
| CPU time | 10.84 seconds |
| Started | Oct 09 10:58:50 PM UTC 24 |
| Finished | Oct 09 10:59:02 PM UTC 24 |
| Peak memory | 238284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059934699 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3059934699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.521437640 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 385866711 ps |
| CPU time | 17.41 seconds |
| Started | Oct 09 10:58:51 PM UTC 24 |
| Finished | Oct 09 10:59:10 PM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521437640 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_tok en_digest.521437640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.543889344 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 471413145 ps |
| CPU time | 11.18 seconds |
| Started | Oct 09 10:58:50 PM UTC 24 |
| Finished | Oct 09 10:59:02 PM UTC 24 |
| Peak memory | 238120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543889344 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_ mux.543889344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.3722579548 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 698510504 ps |
| CPU time | 7.83 seconds |
| Started | Oct 09 10:58:48 PM UTC 24 |
| Finished | Oct 09 10:58:57 PM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722579548 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3722579548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.2012435946 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 233549349 ps |
| CPU time | 1.79 seconds |
| Started | Oct 09 10:58:45 PM UTC 24 |
| Finished | Oct 09 10:58:48 PM UTC 24 |
| Peak memory | 229140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012435946 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2012435946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.3023888720 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 753978302 ps |
| CPU time | 20.67 seconds |
| Started | Oct 09 10:58:47 PM UTC 24 |
| Finished | Oct 09 10:59:09 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023888720 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3023888720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.2366177691 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 251859287 ps |
| CPU time | 12.41 seconds |
| Started | Oct 09 10:58:47 PM UTC 24 |
| Finished | Oct 09 10:59:00 PM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366177691 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2366177691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.2579498193 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 18142758867 ps |
| CPU time | 50.02 seconds |
| Started | Oct 09 10:58:52 PM UTC 24 |
| Finished | Oct 09 10:59:44 PM UTC 24 |
| Peak memory | 230464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2579498193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 17.lc_ctrl_stress_all.2579498193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.579996588 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3893598317 ps |
| CPU time | 40.58 seconds |
| Started | Oct 09 10:58:53 PM UTC 24 |
| Finished | Oct 09 10:59:35 PM UTC 24 |
| Peak memory | 279660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579996588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.579996588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3552225938 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 32335194 ps |
| CPU time | 1.13 seconds |
| Started | Oct 09 10:58:47 PM UTC 24 |
| Finished | Oct 09 10:58:49 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552225938 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17 .lc_ctrl_volatile_unlock_smoke.3552225938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.304732602 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 76542832 ps |
| CPU time | 1.69 seconds |
| Started | Oct 09 10:59:02 PM UTC 24 |
| Finished | Oct 09 10:59:05 PM UTC 24 |
| Peak memory | 218788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304732602 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.304732602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.3601005304 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1145154808 ps |
| CPU time | 11.91 seconds |
| Started | Oct 09 10:58:58 PM UTC 24 |
| Finished | Oct 09 10:59:11 PM UTC 24 |
| Peak memory | 238236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601005304 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3601005304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.912381452 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1171336419 ps |
| CPU time | 10.34 seconds |
| Started | Oct 09 10:58:59 PM UTC 24 |
| Finished | Oct 09 10:59:11 PM UTC 24 |
| Peak memory | 229472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912381452 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.912381452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.3167514776 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 20080094572 ps |
| CPU time | 62.61 seconds |
| Started | Oct 09 10:58:59 PM UTC 24 |
| Finished | Oct 09 11:00:04 PM UTC 24 |
| Peak memory | 238076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167514776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_j tag_errors.3167514776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.4103289153 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 297115342 ps |
| CPU time | 2.65 seconds |
| Started | Oct 09 10:58:59 PM UTC 24 |
| Finished | Oct 09 10:59:03 PM UTC 24 |
| Peak memory | 234360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103289153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctr l_jtag_prog_failure.4103289153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.4123712074 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 370965591 ps |
| CPU time | 7.37 seconds |
| Started | Oct 09 10:58:58 PM UTC 24 |
| Finished | Oct 09 10:59:06 PM UTC 24 |
| Peak memory | 230060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123712074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_ smoke.4123712074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.4105434633 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 20536578139 ps |
| CPU time | 64.93 seconds |
| Started | Oct 09 10:58:58 PM UTC 24 |
| Finished | Oct 09 11:00:05 PM UTC 24 |
| Peak memory | 283536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105434633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct rl_jtag_state_failure.4105434633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.3665989694 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 5489552913 ps |
| CPU time | 19.31 seconds |
| Started | Oct 09 10:58:58 PM UTC 24 |
| Finished | Oct 09 10:59:19 PM UTC 24 |
| Peak memory | 236876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665989694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc _ctrl_jtag_state_post_trans.3665989694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.10698580 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 46640020 ps |
| CPU time | 2.78 seconds |
| Started | Oct 09 10:58:58 PM UTC 24 |
| Finished | Oct 09 10:59:02 PM UTC 24 |
| Peak memory | 234764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10698580 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.10698580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.2494781635 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 944028648 ps |
| CPU time | 11.33 seconds |
| Started | Oct 09 10:58:59 PM UTC 24 |
| Finished | Oct 09 10:59:12 PM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494781635 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2494781635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.3108693770 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1292877554 ps |
| CPU time | 20.78 seconds |
| Started | Oct 09 10:59:01 PM UTC 24 |
| Finished | Oct 09 10:59:23 PM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108693770 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_to ken_digest.3108693770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.1229607540 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 391253921 ps |
| CPU time | 8.96 seconds |
| Started | Oct 09 10:59:01 PM UTC 24 |
| Finished | Oct 09 10:59:11 PM UTC 24 |
| Peak memory | 237992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229607540 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token _mux.1229607540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3543692824 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1591940646 ps |
| CPU time | 14.6 seconds |
| Started | Oct 09 10:58:58 PM UTC 24 |
| Finished | Oct 09 10:59:14 PM UTC 24 |
| Peak memory | 230352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543692824 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3543692824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.2558617515 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 42230048 ps |
| CPU time | 2.17 seconds |
| Started | Oct 09 10:58:55 PM UTC 24 |
| Finished | Oct 09 10:58:58 PM UTC 24 |
| Peak memory | 230264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558617515 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2558617515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.468077869 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 306340770 ps |
| CPU time | 24.33 seconds |
| Started | Oct 09 10:58:55 PM UTC 24 |
| Finished | Oct 09 10:59:21 PM UTC 24 |
| Peak memory | 258916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468077869 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.468077869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.3081335729 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 148768508 ps |
| CPU time | 4.11 seconds |
| Started | Oct 09 10:58:56 PM UTC 24 |
| Finished | Oct 09 10:59:01 PM UTC 24 |
| Peak memory | 234828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081335729 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3081335729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.1533074066 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 8543558988 ps |
| CPU time | 167.28 seconds |
| Started | Oct 09 10:59:02 PM UTC 24 |
| Finished | Oct 09 11:01:52 PM UTC 24 |
| Peak memory | 263208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1533074066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 18.lc_ctrl_stress_all.1533074066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1582363421 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1442191113 ps |
| CPU time | 58.84 seconds |
| Started | Oct 09 10:59:02 PM UTC 24 |
| Finished | Oct 09 11:00:03 PM UTC 24 |
| Peak memory | 263404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582363421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.1582363421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.90141683 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 13488912 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 10:58:55 PM UTC 24 |
| Finished | Oct 09 10:58:58 PM UTC 24 |
| Peak memory | 217936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90141683 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.l c_ctrl_volatile_unlock_smoke.90141683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.3799496774 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 160564184 ps |
| CPU time | 1.46 seconds |
| Started | Oct 09 10:59:11 PM UTC 24 |
| Finished | Oct 09 10:59:14 PM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799496774 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3799496774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.2205428615 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 355285609 ps |
| CPU time | 16.5 seconds |
| Started | Oct 09 10:59:04 PM UTC 24 |
| Finished | Oct 09 10:59:22 PM UTC 24 |
| Peak memory | 238304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205428615 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2205428615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.3214016611 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 175615174 ps |
| CPU time | 6.88 seconds |
| Started | Oct 09 10:59:08 PM UTC 24 |
| Finished | Oct 09 10:59:16 PM UTC 24 |
| Peak memory | 229440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214016611 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3214016611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.3206774838 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1545406437 ps |
| CPU time | 30.3 seconds |
| Started | Oct 09 10:59:06 PM UTC 24 |
| Finished | Oct 09 10:59:38 PM UTC 24 |
| Peak memory | 237976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206774838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_j tag_errors.3206774838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.1404276539 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 347727222 ps |
| CPU time | 9.93 seconds |
| Started | Oct 09 10:59:06 PM UTC 24 |
| Finished | Oct 09 10:59:17 PM UTC 24 |
| Peak memory | 236344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404276539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctr l_jtag_prog_failure.1404276539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.3959360458 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 287591793 ps |
| CPU time | 7.85 seconds |
| Started | Oct 09 10:59:05 PM UTC 24 |
| Finished | Oct 09 10:59:15 PM UTC 24 |
| Peak memory | 230060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959360458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_ smoke.3959360458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.3512620771 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 2955585999 ps |
| CPU time | 85.63 seconds |
| Started | Oct 09 10:59:05 PM UTC 24 |
| Finished | Oct 09 11:00:34 PM UTC 24 |
| Peak memory | 283880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512620771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct rl_jtag_state_failure.3512620771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.159334252 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 2968604281 ps |
| CPU time | 10.29 seconds |
| Started | Oct 09 10:59:06 PM UTC 24 |
| Finished | Oct 09 10:59:17 PM UTC 24 |
| Peak memory | 238484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159334252 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ ctrl_jtag_state_post_trans.159334252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.3617427220 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 71560080 ps |
| CPU time | 3.72 seconds |
| Started | Oct 09 10:59:04 PM UTC 24 |
| Finished | Oct 09 10:59:09 PM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617427220 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3617427220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.222147249 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2577988308 ps |
| CPU time | 14.9 seconds |
| Started | Oct 09 10:59:08 PM UTC 24 |
| Finished | Oct 09 10:59:24 PM UTC 24 |
| Peak memory | 232520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222147249 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.222147249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.2235411066 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 272104282 ps |
| CPU time | 8.73 seconds |
| Started | Oct 09 10:59:09 PM UTC 24 |
| Finished | Oct 09 10:59:19 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235411066 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_to ken_digest.2235411066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.2672420933 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 422370772 ps |
| CPU time | 7.69 seconds |
| Started | Oct 09 10:59:09 PM UTC 24 |
| Finished | Oct 09 10:59:18 PM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672420933 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token _mux.2672420933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.3820401842 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 394849453 ps |
| CPU time | 5.53 seconds |
| Started | Oct 09 10:59:02 PM UTC 24 |
| Finished | Oct 09 10:59:09 PM UTC 24 |
| Peak memory | 230060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820401842 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3820401842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.865730593 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2383007581 ps |
| CPU time | 21.07 seconds |
| Started | Oct 09 10:59:02 PM UTC 24 |
| Finished | Oct 09 10:59:25 PM UTC 24 |
| Peak memory | 263400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865730593 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.865730593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.415705871 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 60316788 ps |
| CPU time | 10 seconds |
| Started | Oct 09 10:59:02 PM UTC 24 |
| Finished | Oct 09 10:59:14 PM UTC 24 |
| Peak memory | 260952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415705871 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.415705871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.2191958937 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2631643000 ps |
| CPU time | 53.54 seconds |
| Started | Oct 09 10:59:09 PM UTC 24 |
| Finished | Oct 09 11:00:05 PM UTC 24 |
| Peak memory | 259052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2191958937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 19.lc_ctrl_stress_all.2191958937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3970938270 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4311881660 ps |
| CPU time | 58.66 seconds |
| Started | Oct 09 10:59:11 PM UTC 24 |
| Finished | Oct 09 11:00:11 PM UTC 24 |
| Peak memory | 281768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970938270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.3970938270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3028235236 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 37905683 ps |
| CPU time | 1.07 seconds |
| Started | Oct 09 10:59:02 PM UTC 24 |
| Finished | Oct 09 10:59:05 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028235236 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19 .lc_ctrl_volatile_unlock_smoke.3028235236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.3534950734 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 23465024 ps |
| CPU time | 1.64 seconds |
| Started | Oct 09 10:56:26 PM UTC 24 |
| Finished | Oct 09 10:56:29 PM UTC 24 |
| Peak memory | 218900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534950734 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3534950734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.4102961314 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 55007019 ps |
| CPU time | 1.01 seconds |
| Started | Oct 09 10:56:13 PM UTC 24 |
| Finished | Oct 09 10:56:15 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102961314 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.4102961314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1472592513 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 689188421 ps |
| CPU time | 12.05 seconds |
| Started | Oct 09 10:56:11 PM UTC 24 |
| Finished | Oct 09 10:56:24 PM UTC 24 |
| Peak memory | 238108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472592513 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1472592513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2128203990 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1221043077 ps |
| CPU time | 10.46 seconds |
| Started | Oct 09 10:56:19 PM UTC 24 |
| Finished | Oct 09 10:56:31 PM UTC 24 |
| Peak memory | 229472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128203990 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2128203990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.349127706 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 7966394891 ps |
| CPU time | 57.96 seconds |
| Started | Oct 09 10:56:17 PM UTC 24 |
| Finished | Oct 09 10:57:17 PM UTC 24 |
| Peak memory | 238084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349127706 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta g_errors.349127706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.2850867557 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 4147848795 ps |
| CPU time | 18.64 seconds |
| Started | Oct 09 10:56:19 PM UTC 24 |
| Finished | Oct 09 10:56:39 PM UTC 24 |
| Peak memory | 230372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850867557 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_prior ity.2850867557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.2177051374 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 130615336 ps |
| CPU time | 4.15 seconds |
| Started | Oct 09 10:56:17 PM UTC 24 |
| Finished | Oct 09 10:56:22 PM UTC 24 |
| Peak memory | 234432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177051374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl _jtag_prog_failure.2177051374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3410121027 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1572575488 ps |
| CPU time | 12.15 seconds |
| Started | Oct 09 10:56:20 PM UTC 24 |
| Finished | Oct 09 10:56:34 PM UTC 24 |
| Peak memory | 223920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410121027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ ctrl_jtag_regwen_during_op.3410121027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.2145324850 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 335656400 ps |
| CPU time | 8.81 seconds |
| Started | Oct 09 10:56:15 PM UTC 24 |
| Finished | Oct 09 10:56:25 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145324850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_s moke.2145324850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.3822083994 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 2146403025 ps |
| CPU time | 59.86 seconds |
| Started | Oct 09 10:56:17 PM UTC 24 |
| Finished | Oct 09 10:57:18 PM UTC 24 |
| Peak memory | 293980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822083994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr l_jtag_state_failure.3822083994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1025153160 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 873749865 ps |
| CPU time | 13.59 seconds |
| Started | Oct 09 10:56:17 PM UTC 24 |
| Finished | Oct 09 10:56:32 PM UTC 24 |
| Peak memory | 238508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025153160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ ctrl_jtag_state_post_trans.1025153160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.2458747585 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 452728389 ps |
| CPU time | 6.53 seconds |
| Started | Oct 09 10:56:11 PM UTC 24 |
| Finished | Oct 09 10:56:19 PM UTC 24 |
| Peak memory | 234436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458747585 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2458747585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.643719603 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 215662423 ps |
| CPU time | 10.67 seconds |
| Started | Oct 09 10:56:13 PM UTC 24 |
| Finished | Oct 09 10:56:25 PM UTC 24 |
| Peak memory | 230192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643719603 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.643719603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.2855885321 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 840035090 ps |
| CPU time | 30.9 seconds |
| Started | Oct 09 10:56:26 PM UTC 24 |
| Finished | Oct 09 10:56:58 PM UTC 24 |
| Peak memory | 290232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855885321 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2855885321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.2231323910 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 431088153 ps |
| CPU time | 8.29 seconds |
| Started | Oct 09 10:56:21 PM UTC 24 |
| Finished | Oct 09 10:56:31 PM UTC 24 |
| Peak memory | 238028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231323910 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2231323910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.3235535947 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1277337086 ps |
| CPU time | 12.77 seconds |
| Started | Oct 09 10:56:25 PM UTC 24 |
| Finished | Oct 09 10:56:39 PM UTC 24 |
| Peak memory | 238172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235535947 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_tok en_digest.3235535947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.2397222277 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 708543207 ps |
| CPU time | 9.7 seconds |
| Started | Oct 09 10:56:22 PM UTC 24 |
| Finished | Oct 09 10:56:33 PM UTC 24 |
| Peak memory | 236940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397222277 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_ mux.2397222277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.2289272486 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 384904693 ps |
| CPU time | 17.78 seconds |
| Started | Oct 09 10:56:12 PM UTC 24 |
| Finished | Oct 09 10:56:31 PM UTC 24 |
| Peak memory | 238028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289272486 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2289272486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.2942439832 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 83307148 ps |
| CPU time | 3.98 seconds |
| Started | Oct 09 10:56:07 PM UTC 24 |
| Finished | Oct 09 10:56:12 PM UTC 24 |
| Peak memory | 226024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942439832 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2942439832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.3041407083 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 875808888 ps |
| CPU time | 24.74 seconds |
| Started | Oct 09 10:56:10 PM UTC 24 |
| Finished | Oct 09 10:56:36 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041407083 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3041407083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.3379618791 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 104724629 ps |
| CPU time | 7.54 seconds |
| Started | Oct 09 10:56:10 PM UTC 24 |
| Finished | Oct 09 10:56:18 PM UTC 24 |
| Peak memory | 263088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379618791 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3379618791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.602108 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 4803721248 ps |
| CPU time | 89.31 seconds |
| Started | Oct 09 10:56:25 PM UTC 24 |
| Finished | Oct 09 10:57:56 PM UTC 24 |
| Peak memory | 263420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=602108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.lc_ctrl_stress_all.602108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3938467612 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 5476618327 ps |
| CPU time | 86.75 seconds |
| Started | Oct 09 10:56:26 PM UTC 24 |
| Finished | Oct 09 10:57:55 PM UTC 24 |
| Peak memory | 279736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938467612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.3938467612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2936654289 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 31102008 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 10:56:08 PM UTC 24 |
| Finished | Oct 09 10:56:11 PM UTC 24 |
| Peak memory | 217876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936654289 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2. lc_ctrl_volatile_unlock_smoke.2936654289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.2587585538 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 64357861 ps |
| CPU time | 1.38 seconds |
| Started | Oct 09 10:59:18 PM UTC 24 |
| Finished | Oct 09 10:59:20 PM UTC 24 |
| Peak memory | 218204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587585538 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2587585538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.2079274784 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 494251851 ps |
| CPU time | 12.06 seconds |
| Started | Oct 09 10:59:14 PM UTC 24 |
| Finished | Oct 09 10:59:28 PM UTC 24 |
| Peak memory | 237964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079274784 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2079274784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.3535256521 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1763389002 ps |
| CPU time | 5.43 seconds |
| Started | Oct 09 10:59:15 PM UTC 24 |
| Finished | Oct 09 10:59:21 PM UTC 24 |
| Peak memory | 229664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535256521 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3535256521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.1299774514 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 46174341 ps |
| CPU time | 3.11 seconds |
| Started | Oct 09 10:59:13 PM UTC 24 |
| Finished | Oct 09 10:59:18 PM UTC 24 |
| Peak memory | 234696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299774514 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1299774514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.3768177165 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2782673132 ps |
| CPU time | 10.12 seconds |
| Started | Oct 09 10:59:16 PM UTC 24 |
| Finished | Oct 09 10:59:27 PM UTC 24 |
| Peak memory | 237240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768177165 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3768177165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.2781591412 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 1431215833 ps |
| CPU time | 15.27 seconds |
| Started | Oct 09 10:59:16 PM UTC 24 |
| Finished | Oct 09 10:59:33 PM UTC 24 |
| Peak memory | 237952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781591412 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_to ken_digest.2781591412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.1571009264 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 1392932232 ps |
| CPU time | 12.59 seconds |
| Started | Oct 09 10:59:16 PM UTC 24 |
| Finished | Oct 09 10:59:30 PM UTC 24 |
| Peak memory | 237348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571009264 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token _mux.1571009264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.3827923484 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 227531848 ps |
| CPU time | 6.13 seconds |
| Started | Oct 09 10:59:14 PM UTC 24 |
| Finished | Oct 09 10:59:22 PM UTC 24 |
| Peak memory | 236480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827923484 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3827923484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.3803716179 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 55735938 ps |
| CPU time | 2.56 seconds |
| Started | Oct 09 10:59:12 PM UTC 24 |
| Finished | Oct 09 10:59:16 PM UTC 24 |
| Peak memory | 226100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803716179 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3803716179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.3951582249 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 232701760 ps |
| CPU time | 29.13 seconds |
| Started | Oct 09 10:59:12 PM UTC 24 |
| Finished | Oct 09 10:59:43 PM UTC 24 |
| Peak memory | 258984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951582249 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3951582249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.600086041 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 89748779 ps |
| CPU time | 8.87 seconds |
| Started | Oct 09 10:59:13 PM UTC 24 |
| Finished | Oct 09 10:59:23 PM UTC 24 |
| Peak memory | 263076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600086041 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.600086041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.672733618 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 11841360916 ps |
| CPU time | 76.7 seconds |
| Started | Oct 09 10:59:16 PM UTC 24 |
| Finished | Oct 09 11:00:35 PM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=672733618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 20.lc_ctrl_stress_all.672733618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.450364705 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 23648581 ps |
| CPU time | 1.02 seconds |
| Started | Oct 09 10:59:12 PM UTC 24 |
| Finished | Oct 09 10:59:15 PM UTC 24 |
| Peak memory | 217876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450364705 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20. lc_ctrl_volatile_unlock_smoke.450364705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.3028078296 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 37095657 ps |
| CPU time | 1.63 seconds |
| Started | Oct 09 10:59:22 PM UTC 24 |
| Finished | Oct 09 10:59:25 PM UTC 24 |
| Peak memory | 219020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028078296 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3028078296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.4169025744 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 522928525 ps |
| CPU time | 13.03 seconds |
| Started | Oct 09 10:59:19 PM UTC 24 |
| Finished | Oct 09 10:59:34 PM UTC 24 |
| Peak memory | 238296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169025744 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.4169025744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.2729937291 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 1549200165 ps |
| CPU time | 10.87 seconds |
| Started | Oct 09 10:59:20 PM UTC 24 |
| Finished | Oct 09 10:59:32 PM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729937291 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2729937291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.4129566579 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 122749141 ps |
| CPU time | 2.43 seconds |
| Started | Oct 09 10:59:19 PM UTC 24 |
| Finished | Oct 09 10:59:23 PM UTC 24 |
| Peak memory | 234760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129566579 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.4129566579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.3374563734 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 340413298 ps |
| CPU time | 11.98 seconds |
| Started | Oct 09 10:59:21 PM UTC 24 |
| Finished | Oct 09 10:59:34 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374563734 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3374563734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.2098976561 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 742104783 ps |
| CPU time | 10.1 seconds |
| Started | Oct 09 10:59:21 PM UTC 24 |
| Finished | Oct 09 10:59:32 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098976561 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_to ken_digest.2098976561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.1611877096 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 353485207 ps |
| CPU time | 9.99 seconds |
| Started | Oct 09 10:59:21 PM UTC 24 |
| Finished | Oct 09 10:59:32 PM UTC 24 |
| Peak memory | 238016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611877096 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token _mux.1611877096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.3159693899 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1117683497 ps |
| CPU time | 7.55 seconds |
| Started | Oct 09 10:59:19 PM UTC 24 |
| Finished | Oct 09 10:59:28 PM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159693899 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3159693899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.3065072792 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 30511990 ps |
| CPU time | 3.08 seconds |
| Started | Oct 09 10:59:18 PM UTC 24 |
| Finished | Oct 09 10:59:22 PM UTC 24 |
| Peak memory | 226100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065072792 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3065072792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.3367059913 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1357201467 ps |
| CPU time | 38.87 seconds |
| Started | Oct 09 10:59:18 PM UTC 24 |
| Finished | Oct 09 10:59:58 PM UTC 24 |
| Peak memory | 260920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367059913 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3367059913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.3972952410 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 135360886 ps |
| CPU time | 4.29 seconds |
| Started | Oct 09 10:59:19 PM UTC 24 |
| Finished | Oct 09 10:59:25 PM UTC 24 |
| Peak memory | 238420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972952410 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3972952410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.3129398355 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 37577313116 ps |
| CPU time | 224.03 seconds |
| Started | Oct 09 10:59:21 PM UTC 24 |
| Finished | Oct 09 11:03:09 PM UTC 24 |
| Peak memory | 238556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3129398355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 21.lc_ctrl_stress_all.3129398355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2495226642 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 17945171 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 10:59:18 PM UTC 24 |
| Finished | Oct 09 10:59:20 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495226642 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21 .lc_ctrl_volatile_unlock_smoke.2495226642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.2385332730 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 21600381 ps |
| CPU time | 1.42 seconds |
| Started | Oct 09 10:59:30 PM UTC 24 |
| Finished | Oct 09 10:59:32 PM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385332730 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2385332730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.3355613233 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 6340701851 ps |
| CPU time | 14.82 seconds |
| Started | Oct 09 10:59:25 PM UTC 24 |
| Finished | Oct 09 10:59:41 PM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355613233 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3355613233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.3218982538 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 4332342849 ps |
| CPU time | 23.52 seconds |
| Started | Oct 09 10:59:27 PM UTC 24 |
| Finished | Oct 09 10:59:52 PM UTC 24 |
| Peak memory | 230204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218982538 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3218982538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.2424876612 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 60573679 ps |
| CPU time | 2.58 seconds |
| Started | Oct 09 10:59:25 PM UTC 24 |
| Finished | Oct 09 10:59:29 PM UTC 24 |
| Peak memory | 234364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424876612 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2424876612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.2947552841 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2505689121 ps |
| CPU time | 11.92 seconds |
| Started | Oct 09 10:59:27 PM UTC 24 |
| Finished | Oct 09 10:59:40 PM UTC 24 |
| Peak memory | 238148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947552841 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2947552841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.1543904807 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3237432524 ps |
| CPU time | 19.42 seconds |
| Started | Oct 09 10:59:27 PM UTC 24 |
| Finished | Oct 09 10:59:48 PM UTC 24 |
| Peak memory | 230728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543904807 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_to ken_digest.1543904807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.2035865351 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 317830226 ps |
| CPU time | 12.39 seconds |
| Started | Oct 09 10:59:27 PM UTC 24 |
| Finished | Oct 09 10:59:41 PM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035865351 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token _mux.2035865351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.3904682378 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 805103812 ps |
| CPU time | 10.2 seconds |
| Started | Oct 09 10:59:27 PM UTC 24 |
| Finished | Oct 09 10:59:38 PM UTC 24 |
| Peak memory | 236624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904682378 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3904682378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.833900975 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 130336128 ps |
| CPU time | 3.69 seconds |
| Started | Oct 09 10:59:22 PM UTC 24 |
| Finished | Oct 09 10:59:27 PM UTC 24 |
| Peak memory | 226032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833900975 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.833900975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.2262810380 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 262485441 ps |
| CPU time | 29.08 seconds |
| Started | Oct 09 10:59:23 PM UTC 24 |
| Finished | Oct 09 10:59:53 PM UTC 24 |
| Peak memory | 263336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262810380 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2262810380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.232795117 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 194808122 ps |
| CPU time | 7 seconds |
| Started | Oct 09 10:59:25 PM UTC 24 |
| Finished | Oct 09 10:59:33 PM UTC 24 |
| Peak memory | 260948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232795117 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.232795117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.611199200 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 82371369299 ps |
| CPU time | 406.41 seconds |
| Started | Oct 09 10:59:27 PM UTC 24 |
| Finished | Oct 09 11:06:19 PM UTC 24 |
| Peak memory | 508952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=611199200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 22.lc_ctrl_stress_all.611199200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.4008018547 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3988291499 ps |
| CPU time | 101.06 seconds |
| Started | Oct 09 10:59:27 PM UTC 24 |
| Finished | Oct 09 11:01:11 PM UTC 24 |
| Peak memory | 279912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008018547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.4008018547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.168931105 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 13964949 ps |
| CPU time | 0.97 seconds |
| Started | Oct 09 10:59:22 PM UTC 24 |
| Finished | Oct 09 10:59:24 PM UTC 24 |
| Peak memory | 217876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168931105 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22. lc_ctrl_volatile_unlock_smoke.168931105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/22.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.1361128799 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 170426666 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:59:34 PM UTC 24 |
| Finished | Oct 09 10:59:37 PM UTC 24 |
| Peak memory | 218384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361128799 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1361128799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.4202547413 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1041358402 ps |
| CPU time | 9.67 seconds |
| Started | Oct 09 10:59:32 PM UTC 24 |
| Finished | Oct 09 10:59:43 PM UTC 24 |
| Peak memory | 238132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202547413 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.4202547413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.1224224610 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 1380300665 ps |
| CPU time | 7.88 seconds |
| Started | Oct 09 10:59:34 PM UTC 24 |
| Finished | Oct 09 10:59:43 PM UTC 24 |
| Peak memory | 229432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224224610 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1224224610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.701653256 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 110096489 ps |
| CPU time | 3.18 seconds |
| Started | Oct 09 10:59:30 PM UTC 24 |
| Finished | Oct 09 10:59:35 PM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701653256 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.701653256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.2153568173 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 4377974035 ps |
| CPU time | 13.48 seconds |
| Started | Oct 09 10:59:34 PM UTC 24 |
| Finished | Oct 09 10:59:49 PM UTC 24 |
| Peak memory | 232836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153568173 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2153568173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.3127145779 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 832430155 ps |
| CPU time | 8.49 seconds |
| Started | Oct 09 10:59:34 PM UTC 24 |
| Finished | Oct 09 10:59:44 PM UTC 24 |
| Peak memory | 238016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127145779 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_to ken_digest.3127145779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.3413441350 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 467247084 ps |
| CPU time | 8.51 seconds |
| Started | Oct 09 10:59:34 PM UTC 24 |
| Finished | Oct 09 10:59:44 PM UTC 24 |
| Peak memory | 236872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413441350 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token _mux.3413441350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.2560515035 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 326375594 ps |
| CPU time | 6.01 seconds |
| Started | Oct 09 10:59:32 PM UTC 24 |
| Finished | Oct 09 10:59:40 PM UTC 24 |
| Peak memory | 236660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560515035 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2560515035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.3069083798 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 18081015 ps |
| CPU time | 1.46 seconds |
| Started | Oct 09 10:59:30 PM UTC 24 |
| Finished | Oct 09 10:59:33 PM UTC 24 |
| Peak memory | 222404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069083798 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3069083798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.3505622763 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1148168199 ps |
| CPU time | 35.53 seconds |
| Started | Oct 09 10:59:30 PM UTC 24 |
| Finished | Oct 09 11:00:07 PM UTC 24 |
| Peak memory | 262996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505622763 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3505622763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.2058060541 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 113528745 ps |
| CPU time | 6.7 seconds |
| Started | Oct 09 10:59:30 PM UTC 24 |
| Finished | Oct 09 10:59:38 PM UTC 24 |
| Peak memory | 260944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058060541 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2058060541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.403820313 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 55028714701 ps |
| CPU time | 300.6 seconds |
| Started | Oct 09 10:59:34 PM UTC 24 |
| Finished | Oct 09 11:04:40 PM UTC 24 |
| Peak memory | 295960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=403820313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 23.lc_ctrl_stress_all.403820313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.464273937 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 27778626 ps |
| CPU time | 1.51 seconds |
| Started | Oct 09 10:59:30 PM UTC 24 |
| Finished | Oct 09 10:59:32 PM UTC 24 |
| Peak memory | 228948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464273937 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23. lc_ctrl_volatile_unlock_smoke.464273937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/23.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.2354667821 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 16783257 ps |
| CPU time | 1.23 seconds |
| Started | Oct 09 10:59:39 PM UTC 24 |
| Finished | Oct 09 10:59:41 PM UTC 24 |
| Peak memory | 218532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354667821 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2354667821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.1546363791 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 3863872137 ps |
| CPU time | 12.6 seconds |
| Started | Oct 09 10:59:36 PM UTC 24 |
| Finished | Oct 09 10:59:50 PM UTC 24 |
| Peak memory | 238164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546363791 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1546363791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.3830608044 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 321549352 ps |
| CPU time | 2.98 seconds |
| Started | Oct 09 10:59:37 PM UTC 24 |
| Finished | Oct 09 10:59:42 PM UTC 24 |
| Peak memory | 229280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830608044 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3830608044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.2367938835 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 121133085 ps |
| CPU time | 2.66 seconds |
| Started | Oct 09 10:59:36 PM UTC 24 |
| Finished | Oct 09 10:59:40 PM UTC 24 |
| Peak memory | 234760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367938835 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2367938835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.3840912380 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 5405440646 ps |
| CPU time | 23.62 seconds |
| Started | Oct 09 10:59:38 PM UTC 24 |
| Finished | Oct 09 11:00:02 PM UTC 24 |
| Peak memory | 238424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840912380 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3840912380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.3959106413 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1098141767 ps |
| CPU time | 11.62 seconds |
| Started | Oct 09 10:59:39 PM UTC 24 |
| Finished | Oct 09 10:59:52 PM UTC 24 |
| Peak memory | 230404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959106413 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_to ken_digest.3959106413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.3298628448 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 221419888 ps |
| CPU time | 8.46 seconds |
| Started | Oct 09 10:59:39 PM UTC 24 |
| Finished | Oct 09 10:59:49 PM UTC 24 |
| Peak memory | 237476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298628448 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token _mux.3298628448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.3523945317 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3229014437 ps |
| CPU time | 10.23 seconds |
| Started | Oct 09 10:59:36 PM UTC 24 |
| Finished | Oct 09 10:59:47 PM UTC 24 |
| Peak memory | 238424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523945317 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3523945317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.4222466590 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 56690305 ps |
| CPU time | 3.2 seconds |
| Started | Oct 09 10:59:34 PM UTC 24 |
| Finished | Oct 09 10:59:39 PM UTC 24 |
| Peak memory | 225988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222466590 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.4222466590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.4140039710 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 699047709 ps |
| CPU time | 19.23 seconds |
| Started | Oct 09 10:59:36 PM UTC 24 |
| Finished | Oct 09 10:59:56 PM UTC 24 |
| Peak memory | 263076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140039710 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4140039710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.1672477347 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 96563448 ps |
| CPU time | 8.32 seconds |
| Started | Oct 09 10:59:36 PM UTC 24 |
| Finished | Oct 09 10:59:45 PM UTC 24 |
| Peak memory | 263288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672477347 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1672477347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.3395325119 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 511495523 ps |
| CPU time | 31 seconds |
| Started | Oct 09 10:59:39 PM UTC 24 |
| Finished | Oct 09 11:00:11 PM UTC 24 |
| Peak memory | 263028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3395325119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 24.lc_ctrl_stress_all.3395325119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.339209648 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 19974151 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 10:59:34 PM UTC 24 |
| Finished | Oct 09 10:59:37 PM UTC 24 |
| Peak memory | 218788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339209648 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24. lc_ctrl_volatile_unlock_smoke.339209648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/24.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.1181661858 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 17495705 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 10:59:45 PM UTC 24 |
| Finished | Oct 09 10:59:47 PM UTC 24 |
| Peak memory | 218840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181661858 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1181661858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.3188356305 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 605131209 ps |
| CPU time | 12.98 seconds |
| Started | Oct 09 10:59:43 PM UTC 24 |
| Finished | Oct 09 10:59:57 PM UTC 24 |
| Peak memory | 230676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188356305 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3188356305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.1346914258 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 279376821 ps |
| CPU time | 7.21 seconds |
| Started | Oct 09 10:59:43 PM UTC 24 |
| Finished | Oct 09 10:59:52 PM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346914258 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1346914258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.2449067549 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 28294478 ps |
| CPU time | 2.23 seconds |
| Started | Oct 09 10:59:42 PM UTC 24 |
| Finished | Oct 09 10:59:45 PM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449067549 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2449067549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.1204892595 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 959438308 ps |
| CPU time | 11.24 seconds |
| Started | Oct 09 10:59:45 PM UTC 24 |
| Finished | Oct 09 10:59:57 PM UTC 24 |
| Peak memory | 230596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204892595 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1204892595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.3066949606 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 277077846 ps |
| CPU time | 7.73 seconds |
| Started | Oct 09 10:59:45 PM UTC 24 |
| Finished | Oct 09 10:59:54 PM UTC 24 |
| Peak memory | 230264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066949606 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_to ken_digest.3066949606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.175286896 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 1856021673 ps |
| CPU time | 13.43 seconds |
| Started | Oct 09 10:59:45 PM UTC 24 |
| Finished | Oct 09 10:59:59 PM UTC 24 |
| Peak memory | 238012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175286896 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_ mux.175286896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.18948890 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1889210857 ps |
| CPU time | 14.61 seconds |
| Started | Oct 09 10:59:43 PM UTC 24 |
| Finished | Oct 09 10:59:59 PM UTC 24 |
| Peak memory | 236608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18948890 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.18948890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.4094302948 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 97721477 ps |
| CPU time | 3.94 seconds |
| Started | Oct 09 10:59:40 PM UTC 24 |
| Finished | Oct 09 10:59:45 PM UTC 24 |
| Peak memory | 226028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094302948 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.4094302948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.1327355867 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 473387098 ps |
| CPU time | 20.26 seconds |
| Started | Oct 09 10:59:40 PM UTC 24 |
| Finished | Oct 09 11:00:02 PM UTC 24 |
| Peak memory | 260948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327355867 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1327355867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.1690914764 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 857037213 ps |
| CPU time | 8.64 seconds |
| Started | Oct 09 10:59:42 PM UTC 24 |
| Finished | Oct 09 10:59:51 PM UTC 24 |
| Peak memory | 263268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690914764 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1690914764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.1793628991 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1462359093 ps |
| CPU time | 39.32 seconds |
| Started | Oct 09 10:59:45 PM UTC 24 |
| Finished | Oct 09 11:00:25 PM UTC 24 |
| Peak memory | 283560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1793628991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 25.lc_ctrl_stress_all.1793628991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.73616403 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1545248022 ps |
| CPU time | 46.53 seconds |
| Started | Oct 09 10:59:45 PM UTC 24 |
| Finished | Oct 09 11:00:33 PM UTC 24 |
| Peak memory | 279972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73616403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SE Q=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unl ock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.73616403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1421712409 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 35125594 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 10:59:40 PM UTC 24 |
| Finished | Oct 09 10:59:43 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421712409 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25 .lc_ctrl_volatile_unlock_smoke.1421712409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/25.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.3257410668 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 33459754 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:59:52 PM UTC 24 |
| Finished | Oct 09 10:59:54 PM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257410668 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3257410668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.298908307 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 511266995 ps |
| CPU time | 13.75 seconds |
| Started | Oct 09 10:59:49 PM UTC 24 |
| Finished | Oct 09 11:00:04 PM UTC 24 |
| Peak memory | 238292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298908307 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.298908307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.3443052481 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 796416751 ps |
| CPU time | 11.92 seconds |
| Started | Oct 09 10:59:49 PM UTC 24 |
| Finished | Oct 09 11:00:02 PM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443052481 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3443052481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.354081478 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 56587334 ps |
| CPU time | 3.48 seconds |
| Started | Oct 09 10:59:46 PM UTC 24 |
| Finished | Oct 09 10:59:51 PM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354081478 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.354081478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2685391138 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1451344424 ps |
| CPU time | 17.21 seconds |
| Started | Oct 09 10:59:50 PM UTC 24 |
| Finished | Oct 09 11:00:09 PM UTC 24 |
| Peak memory | 238020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685391138 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2685391138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.2517595772 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1006946789 ps |
| CPU time | 22.92 seconds |
| Started | Oct 09 10:59:50 PM UTC 24 |
| Finished | Oct 09 11:00:15 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517595772 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_to ken_digest.2517595772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.4187523768 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 2579718336 ps |
| CPU time | 11.81 seconds |
| Started | Oct 09 10:59:50 PM UTC 24 |
| Finished | Oct 09 11:00:03 PM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187523768 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token _mux.4187523768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.3269249970 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 408927781 ps |
| CPU time | 9.63 seconds |
| Started | Oct 09 10:59:49 PM UTC 24 |
| Finished | Oct 09 11:00:00 PM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269249970 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3269249970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.3520890083 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 149267653 ps |
| CPU time | 9.87 seconds |
| Started | Oct 09 10:59:45 PM UTC 24 |
| Finished | Oct 09 10:59:56 PM UTC 24 |
| Peak memory | 230060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520890083 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3520890083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.3974137041 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 524151035 ps |
| CPU time | 28.52 seconds |
| Started | Oct 09 10:59:46 PM UTC 24 |
| Finished | Oct 09 11:00:16 PM UTC 24 |
| Peak memory | 258900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974137041 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3974137041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.3537383415 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 66548833 ps |
| CPU time | 7.39 seconds |
| Started | Oct 09 10:59:46 PM UTC 24 |
| Finished | Oct 09 10:59:55 PM UTC 24 |
| Peak memory | 262996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537383415 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3537383415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.4091780863 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1270977827 ps |
| CPU time | 36.21 seconds |
| Started | Oct 09 10:59:50 PM UTC 24 |
| Finished | Oct 09 11:00:28 PM UTC 24 |
| Peak memory | 263148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4091780863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 26.lc_ctrl_stress_all.4091780863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2881885356 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 7139126086 ps |
| CPU time | 55.85 seconds |
| Started | Oct 09 10:59:52 PM UTC 24 |
| Finished | Oct 09 11:00:49 PM UTC 24 |
| Peak memory | 263524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881885356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.2881885356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.4073752531 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 41321674 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 10:59:46 PM UTC 24 |
| Finished | Oct 09 10:59:49 PM UTC 24 |
| Peak memory | 220772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073752531 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26 .lc_ctrl_volatile_unlock_smoke.4073752531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/26.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.296348652 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 52308584 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:59:59 PM UTC 24 |
| Finished | Oct 09 11:00:01 PM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296348652 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.296348652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_errors.3949072705 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 615022515 ps |
| CPU time | 11.49 seconds |
| Started | Oct 09 10:59:55 PM UTC 24 |
| Finished | Oct 09 11:00:08 PM UTC 24 |
| Peak memory | 238112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949072705 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3949072705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.497642263 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 745238487 ps |
| CPU time | 4.98 seconds |
| Started | Oct 09 10:59:55 PM UTC 24 |
| Finished | Oct 09 11:00:01 PM UTC 24 |
| Peak memory | 229356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497642263 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.497642263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.3409479229 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 95021801 ps |
| CPU time | 4.97 seconds |
| Started | Oct 09 10:59:53 PM UTC 24 |
| Finished | Oct 09 11:00:00 PM UTC 24 |
| Peak memory | 234428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409479229 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3409479229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.1400651719 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 450256337 ps |
| CPU time | 12.29 seconds |
| Started | Oct 09 10:59:56 PM UTC 24 |
| Finished | Oct 09 11:00:09 PM UTC 24 |
| Peak memory | 237924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400651719 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1400651719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.1479112515 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1472787511 ps |
| CPU time | 10.54 seconds |
| Started | Oct 09 10:59:57 PM UTC 24 |
| Finished | Oct 09 11:00:09 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479112515 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_to ken_digest.1479112515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.2635433305 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 851652696 ps |
| CPU time | 9.92 seconds |
| Started | Oct 09 10:59:56 PM UTC 24 |
| Finished | Oct 09 11:00:07 PM UTC 24 |
| Peak memory | 238084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635433305 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token _mux.2635433305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.2535826081 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 667118353 ps |
| CPU time | 9.07 seconds |
| Started | Oct 09 10:59:55 PM UTC 24 |
| Finished | Oct 09 11:00:05 PM UTC 24 |
| Peak memory | 237388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535826081 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2535826081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.8810919 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 53755603 ps |
| CPU time | 4.67 seconds |
| Started | Oct 09 10:59:52 PM UTC 24 |
| Finished | Oct 09 10:59:58 PM UTC 24 |
| Peak memory | 230124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8810919 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.8810919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.1279260307 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 714756993 ps |
| CPU time | 26.12 seconds |
| Started | Oct 09 10:59:52 PM UTC 24 |
| Finished | Oct 09 11:00:20 PM UTC 24 |
| Peak memory | 263352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279260307 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1279260307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.2094624087 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 132733193 ps |
| CPU time | 8.47 seconds |
| Started | Oct 09 10:59:53 PM UTC 24 |
| Finished | Oct 09 11:00:03 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094624087 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2094624087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.1976590494 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 2064413161 ps |
| CPU time | 15.75 seconds |
| Started | Oct 09 10:59:57 PM UTC 24 |
| Finished | Oct 09 11:00:14 PM UTC 24 |
| Peak memory | 263076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1976590494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 27.lc_ctrl_stress_all.1976590494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.56037066 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 2571603908 ps |
| CPU time | 68.46 seconds |
| Started | Oct 09 10:59:59 PM UTC 24 |
| Finished | Oct 09 11:01:09 PM UTC 24 |
| Peak memory | 273596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56037066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SE Q=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unl ock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.56037066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1543389064 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 11921653 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 10:59:52 PM UTC 24 |
| Finished | Oct 09 10:59:55 PM UTC 24 |
| Peak memory | 220772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543389064 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27 .lc_ctrl_volatile_unlock_smoke.1543389064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.1022038229 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 15884481 ps |
| CPU time | 1.2 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:14 PM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022038229 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1022038229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.2753912692 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 795596583 ps |
| CPU time | 7.7 seconds |
| Started | Oct 09 11:00:01 PM UTC 24 |
| Finished | Oct 09 11:00:18 PM UTC 24 |
| Peak memory | 230612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753912692 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2753912692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.2557281472 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1086322545 ps |
| CPU time | 4.86 seconds |
| Started | Oct 09 11:00:02 PM UTC 24 |
| Finished | Oct 09 11:00:16 PM UTC 24 |
| Peak memory | 229232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557281472 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2557281472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.80323262 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 242257975 ps |
| CPU time | 3.23 seconds |
| Started | Oct 09 11:00:00 PM UTC 24 |
| Finished | Oct 09 11:00:13 PM UTC 24 |
| Peak memory | 234700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80323262 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.80323262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.277135500 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1030658921 ps |
| CPU time | 9.87 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:23 PM UTC 24 |
| Peak memory | 230612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277135500 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.277135500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.1690375770 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 334338406 ps |
| CPU time | 9.98 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:23 PM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690375770 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_to ken_digest.1690375770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.3795987313 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2318893525 ps |
| CPU time | 21.06 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:34 PM UTC 24 |
| Peak memory | 230700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795987313 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token _mux.3795987313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.3774364684 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2063683560 ps |
| CPU time | 8.2 seconds |
| Started | Oct 09 11:00:02 PM UTC 24 |
| Finished | Oct 09 11:00:19 PM UTC 24 |
| Peak memory | 230436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774364684 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3774364684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.3852190185 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 160932608 ps |
| CPU time | 4.99 seconds |
| Started | Oct 09 10:59:59 PM UTC 24 |
| Finished | Oct 09 11:00:05 PM UTC 24 |
| Peak memory | 226032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852190185 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3852190185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.309197018 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 368768480 ps |
| CPU time | 38 seconds |
| Started | Oct 09 11:00:00 PM UTC 24 |
| Finished | Oct 09 11:00:48 PM UTC 24 |
| Peak memory | 262928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309197018 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.309197018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.1894426229 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 379074090 ps |
| CPU time | 3.25 seconds |
| Started | Oct 09 11:00:00 PM UTC 24 |
| Finished | Oct 09 11:00:14 PM UTC 24 |
| Peak memory | 235100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894426229 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1894426229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.628885109 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 7168660032 ps |
| CPU time | 288.48 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:05:05 PM UTC 24 |
| Peak memory | 449720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=628885109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 28.lc_ctrl_stress_all.628885109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.3642608087 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1647643329 ps |
| CPU time | 24.48 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:38 PM UTC 24 |
| Peak memory | 240668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642608087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.3642608087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2412599452 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 11316517 ps |
| CPU time | 0.92 seconds |
| Started | Oct 09 11:00:00 PM UTC 24 |
| Finished | Oct 09 11:00:11 PM UTC 24 |
| Peak memory | 217996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412599452 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28 .lc_ctrl_volatile_unlock_smoke.2412599452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.4181974872 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 55739573 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 11:00:13 PM UTC 24 |
| Finished | Oct 09 11:00:15 PM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181974872 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.4181974872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.497420642 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 239697186 ps |
| CPU time | 10.62 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:24 PM UTC 24 |
| Peak memory | 238020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497420642 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.497420642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.3385404643 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1406612100 ps |
| CPU time | 5.89 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:19 PM UTC 24 |
| Peak memory | 229868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385404643 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3385404643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.1513808605 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 18806088 ps |
| CPU time | 2.26 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:16 PM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513808605 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1513808605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.1339120966 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2771968462 ps |
| CPU time | 18.26 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:32 PM UTC 24 |
| Peak memory | 232508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339120966 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1339120966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.615792252 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 852805020 ps |
| CPU time | 17.03 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:31 PM UTC 24 |
| Peak memory | 230336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615792252 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_tok en_digest.615792252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.2616236517 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 193546589 ps |
| CPU time | 6.91 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:21 PM UTC 24 |
| Peak memory | 236832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616236517 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token _mux.2616236517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.1005096095 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 887961411 ps |
| CPU time | 10.56 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:24 PM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005096095 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1005096095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.991860322 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 293825665 ps |
| CPU time | 5.64 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:19 PM UTC 24 |
| Peak memory | 232188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991860322 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.991860322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.4042443900 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 257181718 ps |
| CPU time | 23.5 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:37 PM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042443900 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.4042443900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.2183916101 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 290030080 ps |
| CPU time | 10.63 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:24 PM UTC 24 |
| Peak memory | 263268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183916101 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2183916101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1161938805 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 63692275 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 11:00:12 PM UTC 24 |
| Finished | Oct 09 11:00:14 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161938805 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29 .lc_ctrl_volatile_unlock_smoke.1161938805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/29.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.2737248883 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 104474326 ps |
| CPU time | 1.28 seconds |
| Started | Oct 09 10:56:40 PM UTC 24 |
| Finished | Oct 09 10:56:42 PM UTC 24 |
| Peak memory | 218784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737248883 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2737248883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.4110302461 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 310108575 ps |
| CPU time | 14.22 seconds |
| Started | Oct 09 10:56:32 PM UTC 24 |
| Finished | Oct 09 10:56:47 PM UTC 24 |
| Peak memory | 238028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110302461 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.4110302461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.2581968607 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1345922707 ps |
| CPU time | 14.05 seconds |
| Started | Oct 09 10:56:36 PM UTC 24 |
| Finished | Oct 09 10:56:51 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581968607 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2581968607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.1725042273 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 6848305980 ps |
| CPU time | 37.69 seconds |
| Started | Oct 09 10:56:35 PM UTC 24 |
| Finished | Oct 09 10:57:14 PM UTC 24 |
| Peak memory | 232764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725042273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jt ag_errors.1725042273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.1454364377 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 137362268 ps |
| CPU time | 1.94 seconds |
| Started | Oct 09 10:56:37 PM UTC 24 |
| Finished | Oct 09 10:56:40 PM UTC 24 |
| Peak memory | 228100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454364377 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_prior ity.1454364377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.603257743 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 614758369 ps |
| CPU time | 17.08 seconds |
| Started | Oct 09 10:56:35 PM UTC 24 |
| Finished | Oct 09 10:56:53 PM UTC 24 |
| Peak memory | 236688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603257743 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_prog_failure.603257743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1266485158 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 693377862 ps |
| CPU time | 18.08 seconds |
| Started | Oct 09 10:56:37 PM UTC 24 |
| Finished | Oct 09 10:56:56 PM UTC 24 |
| Peak memory | 224128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266485158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ ctrl_jtag_regwen_during_op.1266485158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.1621216784 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 307930885 ps |
| CPU time | 4.1 seconds |
| Started | Oct 09 10:56:32 PM UTC 24 |
| Finished | Oct 09 10:56:37 PM UTC 24 |
| Peak memory | 223984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621216784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_s moke.1621216784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.1768963477 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 7270377656 ps |
| CPU time | 110.2 seconds |
| Started | Oct 09 10:56:32 PM UTC 24 |
| Finished | Oct 09 10:58:25 PM UTC 24 |
| Peak memory | 289688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768963477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr l_jtag_state_failure.1768963477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.4021277981 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3162960536 ps |
| CPU time | 23.15 seconds |
| Started | Oct 09 10:56:33 PM UTC 24 |
| Finished | Oct 09 10:56:58 PM UTC 24 |
| Peak memory | 263332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021277981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ ctrl_jtag_state_post_trans.4021277981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1934473428 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 60523423 ps |
| CPU time | 4.13 seconds |
| Started | Oct 09 10:56:31 PM UTC 24 |
| Finished | Oct 09 10:56:36 PM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934473428 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1934473428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.2603162751 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1658704401 ps |
| CPU time | 26.48 seconds |
| Started | Oct 09 10:56:32 PM UTC 24 |
| Finished | Oct 09 10:57:00 PM UTC 24 |
| Peak memory | 225892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603162751 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2603162751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.3042587943 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 112283716 ps |
| CPU time | 24.84 seconds |
| Started | Oct 09 10:56:40 PM UTC 24 |
| Finished | Oct 09 10:57:06 PM UTC 24 |
| Peak memory | 290396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042587943 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3042587943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.2332092559 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 698684678 ps |
| CPU time | 17.52 seconds |
| Started | Oct 09 10:56:38 PM UTC 24 |
| Finished | Oct 09 10:56:57 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332092559 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_tok en_digest.2332092559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.873307383 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 2180394711 ps |
| CPU time | 17.11 seconds |
| Started | Oct 09 10:56:38 PM UTC 24 |
| Finished | Oct 09 10:56:56 PM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873307383 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.873307383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.557248299 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2142786855 ps |
| CPU time | 15.07 seconds |
| Started | Oct 09 10:56:32 PM UTC 24 |
| Finished | Oct 09 10:56:48 PM UTC 24 |
| Peak memory | 230104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557248299 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.557248299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.1491402784 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 148660271 ps |
| CPU time | 3.97 seconds |
| Started | Oct 09 10:56:26 PM UTC 24 |
| Finished | Oct 09 10:56:31 PM UTC 24 |
| Peak memory | 230120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491402784 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1491402784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3283337189 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 218250305 ps |
| CPU time | 11.02 seconds |
| Started | Oct 09 10:56:30 PM UTC 24 |
| Finished | Oct 09 10:56:42 PM UTC 24 |
| Peak memory | 260952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283337189 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3283337189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.3983562736 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 11739995362 ps |
| CPU time | 99.13 seconds |
| Started | Oct 09 10:56:39 PM UTC 24 |
| Finished | Oct 09 10:58:21 PM UTC 24 |
| Peak memory | 287716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3983562736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 3.lc_ctrl_stress_all.3983562736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.962132365 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 14756483 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 10:56:27 PM UTC 24 |
| Finished | Oct 09 10:56:30 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962132365 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.l c_ctrl_volatile_unlock_smoke.962132365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.2688193766 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 34074177 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 11:00:17 PM UTC 24 |
| Finished | Oct 09 11:00:20 PM UTC 24 |
| Peak memory | 218960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688193766 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2688193766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_errors.3143792735 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 959836367 ps |
| CPU time | 12.37 seconds |
| Started | Oct 09 11:00:14 PM UTC 24 |
| Finished | Oct 09 11:00:28 PM UTC 24 |
| Peak memory | 237880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143792735 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3143792735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.1602891601 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 576139967 ps |
| CPU time | 5.69 seconds |
| Started | Oct 09 11:00:16 PM UTC 24 |
| Finished | Oct 09 11:00:22 PM UTC 24 |
| Peak memory | 229356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602891601 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1602891601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.1069244962 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 23236243 ps |
| CPU time | 2.22 seconds |
| Started | Oct 09 11:00:14 PM UTC 24 |
| Finished | Oct 09 11:00:17 PM UTC 24 |
| Peak memory | 234504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069244962 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1069244962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.3652313599 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 416379288 ps |
| CPU time | 17.77 seconds |
| Started | Oct 09 11:00:16 PM UTC 24 |
| Finished | Oct 09 11:00:35 PM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652313599 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3652313599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.1227398333 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1054628817 ps |
| CPU time | 10.82 seconds |
| Started | Oct 09 11:00:16 PM UTC 24 |
| Finished | Oct 09 11:00:28 PM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227398333 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_to ken_digest.1227398333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.2475839744 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1957324694 ps |
| CPU time | 12.87 seconds |
| Started | Oct 09 11:00:16 PM UTC 24 |
| Finished | Oct 09 11:00:30 PM UTC 24 |
| Peak memory | 238288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475839744 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token _mux.2475839744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.2617632470 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 338998114 ps |
| CPU time | 13.31 seconds |
| Started | Oct 09 11:00:16 PM UTC 24 |
| Finished | Oct 09 11:00:30 PM UTC 24 |
| Peak memory | 238004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617632470 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2617632470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.4173575914 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 28666793 ps |
| CPU time | 1.99 seconds |
| Started | Oct 09 11:00:14 PM UTC 24 |
| Finished | Oct 09 11:00:17 PM UTC 24 |
| Peak memory | 222404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173575914 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.4173575914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.1070776588 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 1432778996 ps |
| CPU time | 29.11 seconds |
| Started | Oct 09 11:00:14 PM UTC 24 |
| Finished | Oct 09 11:00:45 PM UTC 24 |
| Peak memory | 261280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070776588 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1070776588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.2327804993 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 72646704 ps |
| CPU time | 4.3 seconds |
| Started | Oct 09 11:00:14 PM UTC 24 |
| Finished | Oct 09 11:00:20 PM UTC 24 |
| Peak memory | 238760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327804993 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2327804993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.2348970782 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 831943035 ps |
| CPU time | 39.56 seconds |
| Started | Oct 09 11:00:17 PM UTC 24 |
| Finished | Oct 09 11:00:58 PM UTC 24 |
| Peak memory | 263332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2348970782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 30.lc_ctrl_stress_all.2348970782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.1798621868 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 15454902498 ps |
| CPU time | 74.76 seconds |
| Started | Oct 09 11:00:17 PM UTC 24 |
| Finished | Oct 09 11:01:34 PM UTC 24 |
| Peak memory | 281624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798621868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.1798621868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3238933608 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 17863892 ps |
| CPU time | 1.52 seconds |
| Started | Oct 09 11:00:14 PM UTC 24 |
| Finished | Oct 09 11:00:17 PM UTC 24 |
| Peak memory | 220772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238933608 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30 .lc_ctrl_volatile_unlock_smoke.3238933608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.4147305370 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 69313631 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 11:00:23 PM UTC 24 |
| Finished | Oct 09 11:00:25 PM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147305370 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.4147305370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.3298482758 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 489029409 ps |
| CPU time | 11.5 seconds |
| Started | Oct 09 11:00:20 PM UTC 24 |
| Finished | Oct 09 11:00:32 PM UTC 24 |
| Peak memory | 230420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298482758 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3298482758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.2547588037 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 297284196 ps |
| CPU time | 8.7 seconds |
| Started | Oct 09 11:00:21 PM UTC 24 |
| Finished | Oct 09 11:00:31 PM UTC 24 |
| Peak memory | 229300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547588037 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2547588037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.661863400 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 485302148 ps |
| CPU time | 4.01 seconds |
| Started | Oct 09 11:00:20 PM UTC 24 |
| Finished | Oct 09 11:00:25 PM UTC 24 |
| Peak memory | 234692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661863400 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.661863400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.2921990158 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 256323036 ps |
| CPU time | 7.95 seconds |
| Started | Oct 09 11:00:21 PM UTC 24 |
| Finished | Oct 09 11:00:31 PM UTC 24 |
| Peak memory | 238348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921990158 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2921990158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.1863404638 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 644804613 ps |
| CPU time | 10.19 seconds |
| Started | Oct 09 11:00:21 PM UTC 24 |
| Finished | Oct 09 11:00:33 PM UTC 24 |
| Peak memory | 230404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863404638 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_to ken_digest.1863404638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.1973221401 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 195822913 ps |
| CPU time | 7.02 seconds |
| Started | Oct 09 11:00:21 PM UTC 24 |
| Finished | Oct 09 11:00:30 PM UTC 24 |
| Peak memory | 236788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973221401 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token _mux.1973221401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.2014000894 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 187330976 ps |
| CPU time | 8.02 seconds |
| Started | Oct 09 11:00:21 PM UTC 24 |
| Finished | Oct 09 11:00:30 PM UTC 24 |
| Peak memory | 230672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014000894 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2014000894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.2478337235 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 90610018 ps |
| CPU time | 3.5 seconds |
| Started | Oct 09 11:00:17 PM UTC 24 |
| Finished | Oct 09 11:00:22 PM UTC 24 |
| Peak memory | 230124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478337235 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2478337235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.2190040494 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 2677980298 ps |
| CPU time | 23.09 seconds |
| Started | Oct 09 11:00:18 PM UTC 24 |
| Finished | Oct 09 11:00:43 PM UTC 24 |
| Peak memory | 263136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190040494 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2190040494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.3277936147 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 100946205 ps |
| CPU time | 7.43 seconds |
| Started | Oct 09 11:00:19 PM UTC 24 |
| Finished | Oct 09 11:00:27 PM UTC 24 |
| Peak memory | 263076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277936147 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3277936147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.1697689912 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 10640815735 ps |
| CPU time | 167.83 seconds |
| Started | Oct 09 11:00:21 PM UTC 24 |
| Finished | Oct 09 11:03:12 PM UTC 24 |
| Peak memory | 287704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1697689912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 31.lc_ctrl_stress_all.1697689912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.4036715913 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 15883693474 ps |
| CPU time | 26.81 seconds |
| Started | Oct 09 11:00:22 PM UTC 24 |
| Finished | Oct 09 11:00:50 PM UTC 24 |
| Peak memory | 263324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036715913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.4036715913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.735992009 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 36366360 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 11:00:18 PM UTC 24 |
| Finished | Oct 09 11:00:21 PM UTC 24 |
| Peak memory | 217876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735992009 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31. lc_ctrl_volatile_unlock_smoke.735992009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/31.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.3948646569 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 63582553 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 11:00:30 PM UTC 24 |
| Finished | Oct 09 11:00:32 PM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948646569 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3948646569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_errors.805683801 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 1146571573 ps |
| CPU time | 12.04 seconds |
| Started | Oct 09 11:00:26 PM UTC 24 |
| Finished | Oct 09 11:00:39 PM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805683801 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.805683801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.1524775111 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 60467675 ps |
| CPU time | 1.51 seconds |
| Started | Oct 09 11:00:26 PM UTC 24 |
| Finished | Oct 09 11:00:28 PM UTC 24 |
| Peak memory | 228104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524775111 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1524775111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.820279126 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 47090161 ps |
| CPU time | 2.43 seconds |
| Started | Oct 09 11:00:25 PM UTC 24 |
| Finished | Oct 09 11:00:29 PM UTC 24 |
| Peak memory | 230404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820279126 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.820279126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.977117856 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 431131774 ps |
| CPU time | 16.78 seconds |
| Started | Oct 09 11:00:27 PM UTC 24 |
| Finished | Oct 09 11:00:45 PM UTC 24 |
| Peak memory | 232472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977117856 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.977117856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.2150053602 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 297447603 ps |
| CPU time | 9.26 seconds |
| Started | Oct 09 11:00:27 PM UTC 24 |
| Finished | Oct 09 11:00:37 PM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150053602 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_to ken_digest.2150053602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.680886158 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 231238257 ps |
| CPU time | 6.93 seconds |
| Started | Oct 09 11:00:27 PM UTC 24 |
| Finished | Oct 09 11:00:35 PM UTC 24 |
| Peak memory | 238120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680886158 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_ mux.680886158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.1189253700 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1043610949 ps |
| CPU time | 6.27 seconds |
| Started | Oct 09 11:00:26 PM UTC 24 |
| Finished | Oct 09 11:00:33 PM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189253700 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1189253700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.936228406 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 129844032 ps |
| CPU time | 3.37 seconds |
| Started | Oct 09 11:00:24 PM UTC 24 |
| Finished | Oct 09 11:00:28 PM UTC 24 |
| Peak memory | 226092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936228406 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.936228406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.1956427156 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 152241488 ps |
| CPU time | 24.38 seconds |
| Started | Oct 09 11:00:24 PM UTC 24 |
| Finished | Oct 09 11:00:50 PM UTC 24 |
| Peak memory | 261284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956427156 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1956427156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.2473695374 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 174780126 ps |
| CPU time | 9.82 seconds |
| Started | Oct 09 11:00:25 PM UTC 24 |
| Finished | Oct 09 11:00:36 PM UTC 24 |
| Peak memory | 263196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473695374 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2473695374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.3808827314 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 10687019176 ps |
| CPU time | 65.07 seconds |
| Started | Oct 09 11:00:28 PM UTC 24 |
| Finished | Oct 09 11:01:35 PM UTC 24 |
| Peak memory | 263132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3808827314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 32.lc_ctrl_stress_all.3808827314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2176092071 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 14958004 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 11:00:24 PM UTC 24 |
| Finished | Oct 09 11:00:27 PM UTC 24 |
| Peak memory | 220772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176092071 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32 .lc_ctrl_volatile_unlock_smoke.2176092071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/32.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.868965491 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 22549107 ps |
| CPU time | 1.32 seconds |
| Started | Oct 09 11:00:33 PM UTC 24 |
| Finished | Oct 09 11:00:36 PM UTC 24 |
| Peak memory | 218856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868965491 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.868965491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.4185158158 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 968730442 ps |
| CPU time | 11.48 seconds |
| Started | Oct 09 11:00:32 PM UTC 24 |
| Finished | Oct 09 11:00:44 PM UTC 24 |
| Peak memory | 238296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185158158 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.4185158158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.2215990659 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 269923678 ps |
| CPU time | 2.7 seconds |
| Started | Oct 09 11:00:32 PM UTC 24 |
| Finished | Oct 09 11:00:36 PM UTC 24 |
| Peak memory | 229284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215990659 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2215990659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.1934788182 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 206546713 ps |
| CPU time | 3.43 seconds |
| Started | Oct 09 11:00:31 PM UTC 24 |
| Finished | Oct 09 11:00:36 PM UTC 24 |
| Peak memory | 234576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934788182 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1934788182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.3289045133 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 523916075 ps |
| CPU time | 14.61 seconds |
| Started | Oct 09 11:00:32 PM UTC 24 |
| Finished | Oct 09 11:00:48 PM UTC 24 |
| Peak memory | 238024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289045133 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3289045133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.1326168532 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 538791920 ps |
| CPU time | 10.1 seconds |
| Started | Oct 09 11:00:33 PM UTC 24 |
| Finished | Oct 09 11:00:44 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326168532 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_to ken_digest.1326168532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.2200302008 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 326420427 ps |
| CPU time | 10.26 seconds |
| Started | Oct 09 11:00:33 PM UTC 24 |
| Finished | Oct 09 11:00:45 PM UTC 24 |
| Peak memory | 237204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200302008 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token _mux.2200302008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.3838912789 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 612516627 ps |
| CPU time | 9.12 seconds |
| Started | Oct 09 11:00:32 PM UTC 24 |
| Finished | Oct 09 11:00:42 PM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838912789 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3838912789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.2186360226 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 82724827 ps |
| CPU time | 3.76 seconds |
| Started | Oct 09 11:00:30 PM UTC 24 |
| Finished | Oct 09 11:00:35 PM UTC 24 |
| Peak memory | 226028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186360226 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2186360226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.613594567 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 1301732133 ps |
| CPU time | 31.44 seconds |
| Started | Oct 09 11:00:30 PM UTC 24 |
| Finished | Oct 09 11:01:03 PM UTC 24 |
| Peak memory | 263080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613594567 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.613594567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.1785688351 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 347509615 ps |
| CPU time | 7.14 seconds |
| Started | Oct 09 11:00:30 PM UTC 24 |
| Finished | Oct 09 11:00:38 PM UTC 24 |
| Peak memory | 262912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785688351 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1785688351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.2747094096 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 78334627643 ps |
| CPU time | 235.74 seconds |
| Started | Oct 09 11:00:33 PM UTC 24 |
| Finished | Oct 09 11:04:32 PM UTC 24 |
| Peak memory | 295900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2747094096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 33.lc_ctrl_stress_all.2747094096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3375282296 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 846993917 ps |
| CPU time | 17.4 seconds |
| Started | Oct 09 11:00:33 PM UTC 24 |
| Finished | Oct 09 11:00:52 PM UTC 24 |
| Peak memory | 238240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375282296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.3375282296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.22486138 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 13368041 ps |
| CPU time | 1.08 seconds |
| Started | Oct 09 11:00:30 PM UTC 24 |
| Finished | Oct 09 11:00:32 PM UTC 24 |
| Peak memory | 217876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22486138 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.l c_ctrl_volatile_unlock_smoke.22486138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/33.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.3639094825 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 16964372 ps |
| CPU time | 1.44 seconds |
| Started | Oct 09 11:00:37 PM UTC 24 |
| Finished | Oct 09 11:00:40 PM UTC 24 |
| Peak memory | 219020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639094825 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3639094825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.3920107453 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 337723713 ps |
| CPU time | 11.61 seconds |
| Started | Oct 09 11:00:35 PM UTC 24 |
| Finished | Oct 09 11:00:48 PM UTC 24 |
| Peak memory | 238320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920107453 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3920107453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.921573577 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 997781596 ps |
| CPU time | 22.41 seconds |
| Started | Oct 09 11:00:37 PM UTC 24 |
| Finished | Oct 09 11:01:01 PM UTC 24 |
| Peak memory | 229640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921573577 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.921573577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.2916538027 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 97184641 ps |
| CPU time | 4.23 seconds |
| Started | Oct 09 11:00:35 PM UTC 24 |
| Finished | Oct 09 11:00:41 PM UTC 24 |
| Peak memory | 236552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916538027 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2916538027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.4261883721 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 318525836 ps |
| CPU time | 15.58 seconds |
| Started | Oct 09 11:00:37 PM UTC 24 |
| Finished | Oct 09 11:00:54 PM UTC 24 |
| Peak memory | 238156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261883721 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4261883721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.387528639 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 1411948143 ps |
| CPU time | 14.55 seconds |
| Started | Oct 09 11:00:37 PM UTC 24 |
| Finished | Oct 09 11:00:53 PM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387528639 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_tok en_digest.387528639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.326696903 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 272380114 ps |
| CPU time | 6.39 seconds |
| Started | Oct 09 11:00:37 PM UTC 24 |
| Finished | Oct 09 11:00:44 PM UTC 24 |
| Peak memory | 238304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326696903 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_ mux.326696903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.527494290 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 1233495005 ps |
| CPU time | 8.12 seconds |
| Started | Oct 09 11:00:35 PM UTC 24 |
| Finished | Oct 09 11:00:45 PM UTC 24 |
| Peak memory | 236928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527494290 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.527494290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.1734391718 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 132730738 ps |
| CPU time | 3.11 seconds |
| Started | Oct 09 11:00:33 PM UTC 24 |
| Finished | Oct 09 11:00:38 PM UTC 24 |
| Peak memory | 230144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734391718 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1734391718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.4200909435 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 229409564 ps |
| CPU time | 27.18 seconds |
| Started | Oct 09 11:00:35 PM UTC 24 |
| Finished | Oct 09 11:01:04 PM UTC 24 |
| Peak memory | 263080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200909435 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.4200909435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.2123325565 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 186752742 ps |
| CPU time | 11.67 seconds |
| Started | Oct 09 11:00:35 PM UTC 24 |
| Finished | Oct 09 11:00:48 PM UTC 24 |
| Peak memory | 256788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123325565 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2123325565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.1532368784 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 2038492522 ps |
| CPU time | 56.56 seconds |
| Started | Oct 09 11:00:37 PM UTC 24 |
| Finished | Oct 09 11:01:36 PM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1532368784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 34.lc_ctrl_stress_all.1532368784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2251870894 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 22880798 ps |
| CPU time | 1.51 seconds |
| Started | Oct 09 11:00:35 PM UTC 24 |
| Finished | Oct 09 11:00:38 PM UTC 24 |
| Peak memory | 220768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251870894 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34 .lc_ctrl_volatile_unlock_smoke.2251870894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/34.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.1889990784 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 17451651 ps |
| CPU time | 1.63 seconds |
| Started | Oct 09 11:00:44 PM UTC 24 |
| Finished | Oct 09 11:00:47 PM UTC 24 |
| Peak memory | 218484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889990784 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1889990784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.394502833 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1189909054 ps |
| CPU time | 10.38 seconds |
| Started | Oct 09 11:00:39 PM UTC 24 |
| Finished | Oct 09 11:00:50 PM UTC 24 |
| Peak memory | 238048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394502833 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.394502833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.3511172081 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 12273707497 ps |
| CPU time | 8.37 seconds |
| Started | Oct 09 11:00:40 PM UTC 24 |
| Finished | Oct 09 11:00:50 PM UTC 24 |
| Peak memory | 229956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511172081 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3511172081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.411628039 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 41068405 ps |
| CPU time | 2.78 seconds |
| Started | Oct 09 11:00:39 PM UTC 24 |
| Finished | Oct 09 11:00:43 PM UTC 24 |
| Peak memory | 234692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411628039 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.411628039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.693136418 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 1396001331 ps |
| CPU time | 16.01 seconds |
| Started | Oct 09 11:00:41 PM UTC 24 |
| Finished | Oct 09 11:00:59 PM UTC 24 |
| Peak memory | 238144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693136418 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.693136418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.2201594868 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 1722141893 ps |
| CPU time | 14.92 seconds |
| Started | Oct 09 11:00:41 PM UTC 24 |
| Finished | Oct 09 11:00:58 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201594868 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_to ken_digest.2201594868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.3570077595 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 1954357282 ps |
| CPU time | 13.95 seconds |
| Started | Oct 09 11:00:41 PM UTC 24 |
| Finished | Oct 09 11:00:57 PM UTC 24 |
| Peak memory | 230536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570077595 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token _mux.3570077595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.3709815396 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 618902885 ps |
| CPU time | 9.94 seconds |
| Started | Oct 09 11:00:39 PM UTC 24 |
| Finished | Oct 09 11:00:50 PM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709815396 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3709815396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.549101329 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 404209097 ps |
| CPU time | 6.01 seconds |
| Started | Oct 09 11:00:39 PM UTC 24 |
| Finished | Oct 09 11:00:46 PM UTC 24 |
| Peak memory | 230136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549101329 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.549101329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.475411644 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 767143941 ps |
| CPU time | 24.12 seconds |
| Started | Oct 09 11:00:39 PM UTC 24 |
| Finished | Oct 09 11:01:04 PM UTC 24 |
| Peak memory | 263068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475411644 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.475411644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.2521713392 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 673016500 ps |
| CPU time | 9.03 seconds |
| Started | Oct 09 11:00:39 PM UTC 24 |
| Finished | Oct 09 11:00:49 PM UTC 24 |
| Peak memory | 256860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521713392 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2521713392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2356918794 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 88328383282 ps |
| CPU time | 335.44 seconds |
| Started | Oct 09 11:00:43 PM UTC 24 |
| Finished | Oct 09 11:06:23 PM UTC 24 |
| Peak memory | 296236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2356918794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 35.lc_ctrl_stress_all.2356918794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1226237143 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1816701317 ps |
| CPU time | 11.13 seconds |
| Started | Oct 09 11:00:43 PM UTC 24 |
| Finished | Oct 09 11:00:55 PM UTC 24 |
| Peak memory | 238552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226237143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1226237143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1741893065 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 11942033 ps |
| CPU time | 1.25 seconds |
| Started | Oct 09 11:00:39 PM UTC 24 |
| Finished | Oct 09 11:00:41 PM UTC 24 |
| Peak memory | 218844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741893065 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35 .lc_ctrl_volatile_unlock_smoke.1741893065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/35.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.1796691579 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 49492222 ps |
| CPU time | 1.46 seconds |
| Started | Oct 09 11:00:50 PM UTC 24 |
| Finished | Oct 09 11:00:52 PM UTC 24 |
| Peak memory | 218400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796691579 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1796691579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.3607374088 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 301886477 ps |
| CPU time | 11.42 seconds |
| Started | Oct 09 11:00:46 PM UTC 24 |
| Finished | Oct 09 11:00:58 PM UTC 24 |
| Peak memory | 238028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607374088 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3607374088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.1594730965 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 444864514 ps |
| CPU time | 2.31 seconds |
| Started | Oct 09 11:00:47 PM UTC 24 |
| Finished | Oct 09 11:00:51 PM UTC 24 |
| Peak memory | 229356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594730965 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1594730965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.3018972501 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 37469518 ps |
| CPU time | 2.41 seconds |
| Started | Oct 09 11:00:46 PM UTC 24 |
| Finished | Oct 09 11:00:49 PM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018972501 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3018972501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.1495440457 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 991415502 ps |
| CPU time | 10.79 seconds |
| Started | Oct 09 11:00:47 PM UTC 24 |
| Finished | Oct 09 11:00:59 PM UTC 24 |
| Peak memory | 232644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495440457 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1495440457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.227112378 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 1925118340 ps |
| CPU time | 12.23 seconds |
| Started | Oct 09 11:00:48 PM UTC 24 |
| Finished | Oct 09 11:01:02 PM UTC 24 |
| Peak memory | 237980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227112378 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_tok en_digest.227112378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.3644762736 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1331933277 ps |
| CPU time | 15.41 seconds |
| Started | Oct 09 11:00:48 PM UTC 24 |
| Finished | Oct 09 11:01:05 PM UTC 24 |
| Peak memory | 237052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644762736 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token _mux.3644762736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.891057322 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 369609840 ps |
| CPU time | 12.09 seconds |
| Started | Oct 09 11:00:47 PM UTC 24 |
| Finished | Oct 09 11:01:00 PM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891057322 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.891057322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.2427816623 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 18719956 ps |
| CPU time | 1.8 seconds |
| Started | Oct 09 11:00:44 PM UTC 24 |
| Finished | Oct 09 11:00:47 PM UTC 24 |
| Peak memory | 222404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427816623 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2427816623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.2572684703 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 362142386 ps |
| CPU time | 23.07 seconds |
| Started | Oct 09 11:00:45 PM UTC 24 |
| Finished | Oct 09 11:01:10 PM UTC 24 |
| Peak memory | 263060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572684703 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2572684703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.382478441 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 168778337 ps |
| CPU time | 7.29 seconds |
| Started | Oct 09 11:00:46 PM UTC 24 |
| Finished | Oct 09 11:00:54 PM UTC 24 |
| Peak memory | 261172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382478441 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.382478441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3119875097 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 25300031 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 11:00:45 PM UTC 24 |
| Finished | Oct 09 11:00:48 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119875097 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36 .lc_ctrl_volatile_unlock_smoke.3119875097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.3487432754 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 13765432 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 11:00:53 PM UTC 24 |
| Finished | Oct 09 11:00:56 PM UTC 24 |
| Peak memory | 218900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487432754 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3487432754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.1125744773 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1995520227 ps |
| CPU time | 17.81 seconds |
| Started | Oct 09 11:00:52 PM UTC 24 |
| Finished | Oct 09 11:01:11 PM UTC 24 |
| Peak memory | 238300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125744773 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1125744773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.2531791515 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 193194475 ps |
| CPU time | 2.78 seconds |
| Started | Oct 09 11:00:52 PM UTC 24 |
| Finished | Oct 09 11:00:56 PM UTC 24 |
| Peak memory | 229276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531791515 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.2531791515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.1780010458 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 62645522 ps |
| CPU time | 4.17 seconds |
| Started | Oct 09 11:00:50 PM UTC 24 |
| Finished | Oct 09 11:00:55 PM UTC 24 |
| Peak memory | 234696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780010458 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1780010458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.646834876 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 305532902 ps |
| CPU time | 12.97 seconds |
| Started | Oct 09 11:00:52 PM UTC 24 |
| Finished | Oct 09 11:01:06 PM UTC 24 |
| Peak memory | 238036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646834876 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.646834876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.1959325278 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 2341196033 ps |
| CPU time | 12.46 seconds |
| Started | Oct 09 11:00:52 PM UTC 24 |
| Finished | Oct 09 11:01:06 PM UTC 24 |
| Peak memory | 230532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959325278 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_to ken_digest.1959325278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.1817781724 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 1368515087 ps |
| CPU time | 8.21 seconds |
| Started | Oct 09 11:00:52 PM UTC 24 |
| Finished | Oct 09 11:01:01 PM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817781724 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token _mux.1817781724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.3992700241 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 862167578 ps |
| CPU time | 8.77 seconds |
| Started | Oct 09 11:00:52 PM UTC 24 |
| Finished | Oct 09 11:01:02 PM UTC 24 |
| Peak memory | 230344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992700241 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3992700241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.770460462 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 148974799 ps |
| CPU time | 2.07 seconds |
| Started | Oct 09 11:00:50 PM UTC 24 |
| Finished | Oct 09 11:00:53 PM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770460462 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.770460462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.3261227856 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 569472723 ps |
| CPU time | 27.14 seconds |
| Started | Oct 09 11:00:50 PM UTC 24 |
| Finished | Oct 09 11:01:19 PM UTC 24 |
| Peak memory | 263268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261227856 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3261227856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.1197334120 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 490646646 ps |
| CPU time | 6.75 seconds |
| Started | Oct 09 11:00:50 PM UTC 24 |
| Finished | Oct 09 11:00:58 PM UTC 24 |
| Peak memory | 261136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197334120 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1197334120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.3480304472 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 65652752980 ps |
| CPU time | 454.64 seconds |
| Started | Oct 09 11:00:52 PM UTC 24 |
| Finished | Oct 09 11:08:33 PM UTC 24 |
| Peak memory | 237052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3480304472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 37.lc_ctrl_stress_all.3480304472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1082644934 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 11403848 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 11:00:50 PM UTC 24 |
| Finished | Oct 09 11:00:52 PM UTC 24 |
| Peak memory | 218668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082644934 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37 .lc_ctrl_volatile_unlock_smoke.1082644934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/37.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.1668001799 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 16519712 ps |
| CPU time | 1.33 seconds |
| Started | Oct 09 11:00:59 PM UTC 24 |
| Finished | Oct 09 11:01:02 PM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668001799 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1668001799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.2815669221 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 394763191 ps |
| CPU time | 16.49 seconds |
| Started | Oct 09 11:00:56 PM UTC 24 |
| Finished | Oct 09 11:01:14 PM UTC 24 |
| Peak memory | 238364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815669221 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2815669221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.255558947 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 69381559 ps |
| CPU time | 2.68 seconds |
| Started | Oct 09 11:00:56 PM UTC 24 |
| Finished | Oct 09 11:01:00 PM UTC 24 |
| Peak memory | 229272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255558947 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.255558947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.3424916570 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 19028230 ps |
| CPU time | 2.18 seconds |
| Started | Oct 09 11:00:55 PM UTC 24 |
| Finished | Oct 09 11:00:58 PM UTC 24 |
| Peak memory | 234432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424916570 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3424916570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.1727908453 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 310285151 ps |
| CPU time | 12.72 seconds |
| Started | Oct 09 11:00:57 PM UTC 24 |
| Finished | Oct 09 11:01:11 PM UTC 24 |
| Peak memory | 230272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727908453 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1727908453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.3102449291 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 573202061 ps |
| CPU time | 16.48 seconds |
| Started | Oct 09 11:00:59 PM UTC 24 |
| Finished | Oct 09 11:01:17 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102449291 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_to ken_digest.3102449291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.2705132016 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 962270239 ps |
| CPU time | 9.08 seconds |
| Started | Oct 09 11:00:57 PM UTC 24 |
| Finished | Oct 09 11:01:08 PM UTC 24 |
| Peak memory | 237348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705132016 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token _mux.2705132016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.2507253865 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 1958964635 ps |
| CPU time | 14.4 seconds |
| Started | Oct 09 11:00:56 PM UTC 24 |
| Finished | Oct 09 11:01:12 PM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507253865 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2507253865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.799399799 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 755822893 ps |
| CPU time | 3.99 seconds |
| Started | Oct 09 11:00:53 PM UTC 24 |
| Finished | Oct 09 11:00:59 PM UTC 24 |
| Peak memory | 230124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799399799 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.799399799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.2636514792 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 507917732 ps |
| CPU time | 29.31 seconds |
| Started | Oct 09 11:00:55 PM UTC 24 |
| Finished | Oct 09 11:01:26 PM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636514792 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2636514792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.2358048017 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 160146923 ps |
| CPU time | 9.37 seconds |
| Started | Oct 09 11:00:55 PM UTC 24 |
| Finished | Oct 09 11:01:06 PM UTC 24 |
| Peak memory | 263028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358048017 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2358048017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.3147269575 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 30451071123 ps |
| CPU time | 145.32 seconds |
| Started | Oct 09 11:00:59 PM UTC 24 |
| Finished | Oct 09 11:03:27 PM UTC 24 |
| Peak memory | 291808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3147269575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 38.lc_ctrl_stress_all.3147269575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.429334002 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 25166861406 ps |
| CPU time | 194.98 seconds |
| Started | Oct 09 11:00:59 PM UTC 24 |
| Finished | Oct 09 11:04:17 PM UTC 24 |
| Peak memory | 329144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429334002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.429334002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3864159772 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 12670153 ps |
| CPU time | 1.5 seconds |
| Started | Oct 09 11:00:55 PM UTC 24 |
| Finished | Oct 09 11:00:58 PM UTC 24 |
| Peak memory | 220772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864159772 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38 .lc_ctrl_volatile_unlock_smoke.3864159772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.4152877747 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 15697419 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 11:01:04 PM UTC 24 |
| Finished | Oct 09 11:01:07 PM UTC 24 |
| Peak memory | 218424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152877747 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.4152877747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.3222257463 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 898067555 ps |
| CPU time | 11.66 seconds |
| Started | Oct 09 11:01:01 PM UTC 24 |
| Finished | Oct 09 11:01:14 PM UTC 24 |
| Peak memory | 237896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222257463 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3222257463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.2200222149 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 819895321 ps |
| CPU time | 3.48 seconds |
| Started | Oct 09 11:01:02 PM UTC 24 |
| Finished | Oct 09 11:01:07 PM UTC 24 |
| Peak memory | 229784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200222149 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2200222149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.2413697376 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 714686995 ps |
| CPU time | 2.86 seconds |
| Started | Oct 09 11:01:01 PM UTC 24 |
| Finished | Oct 09 11:01:05 PM UTC 24 |
| Peak memory | 230144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413697376 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2413697376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1702631403 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 879008832 ps |
| CPU time | 12.95 seconds |
| Started | Oct 09 11:01:02 PM UTC 24 |
| Finished | Oct 09 11:01:17 PM UTC 24 |
| Peak memory | 232644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702631403 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1702631403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.2655414704 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 1013145491 ps |
| CPU time | 8.24 seconds |
| Started | Oct 09 11:01:02 PM UTC 24 |
| Finished | Oct 09 11:01:12 PM UTC 24 |
| Peak memory | 237900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655414704 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_to ken_digest.2655414704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.734224038 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 917459965 ps |
| CPU time | 7.71 seconds |
| Started | Oct 09 11:01:02 PM UTC 24 |
| Finished | Oct 09 11:01:11 PM UTC 24 |
| Peak memory | 238012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734224038 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_ mux.734224038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.3188218073 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 1480607602 ps |
| CPU time | 14.03 seconds |
| Started | Oct 09 11:01:02 PM UTC 24 |
| Finished | Oct 09 11:01:18 PM UTC 24 |
| Peak memory | 237728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188218073 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3188218073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.3252066917 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 65577831 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 11:00:59 PM UTC 24 |
| Finished | Oct 09 11:01:02 PM UTC 24 |
| Peak memory | 224052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252066917 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3252066917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.1514125727 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 2178829351 ps |
| CPU time | 26.04 seconds |
| Started | Oct 09 11:00:59 PM UTC 24 |
| Finished | Oct 09 11:01:27 PM UTC 24 |
| Peak memory | 263112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514125727 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1514125727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.3494173514 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 70277487 ps |
| CPU time | 8.68 seconds |
| Started | Oct 09 11:00:59 PM UTC 24 |
| Finished | Oct 09 11:01:09 PM UTC 24 |
| Peak memory | 263000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494173514 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3494173514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.396181795 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 41771701135 ps |
| CPU time | 198.16 seconds |
| Started | Oct 09 11:01:04 PM UTC 24 |
| Finished | Oct 09 11:04:26 PM UTC 24 |
| Peak memory | 238416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=396181795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 39.lc_ctrl_stress_all.396181795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2745584993 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 40223678 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 11:00:59 PM UTC 24 |
| Finished | Oct 09 11:01:02 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745584993 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39 .lc_ctrl_volatile_unlock_smoke.2745584993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/39.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.3774242519 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 24008366 ps |
| CPU time | 1.19 seconds |
| Started | Oct 09 10:56:58 PM UTC 24 |
| Finished | Oct 09 10:57:00 PM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774242519 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3774242519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.2014605645 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 633815279 ps |
| CPU time | 14.73 seconds |
| Started | Oct 09 10:56:45 PM UTC 24 |
| Finished | Oct 09 10:57:01 PM UTC 24 |
| Peak memory | 230216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014605645 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2014605645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.2789930771 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2601867752 ps |
| CPU time | 16.01 seconds |
| Started | Oct 09 10:56:52 PM UTC 24 |
| Finished | Oct 09 10:57:09 PM UTC 24 |
| Peak memory | 230140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789930771 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2789930771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.2004558962 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2183692413 ps |
| CPU time | 38.56 seconds |
| Started | Oct 09 10:56:52 PM UTC 24 |
| Finished | Oct 09 10:57:32 PM UTC 24 |
| Peak memory | 230448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004558962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jt ag_errors.2004558962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.1558084148 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 466003991 ps |
| CPU time | 7.24 seconds |
| Started | Oct 09 10:56:53 PM UTC 24 |
| Finished | Oct 09 10:57:01 PM UTC 24 |
| Peak memory | 229928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558084148 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_prior ity.1558084148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.2979095512 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1841029243 ps |
| CPU time | 13.09 seconds |
| Started | Oct 09 10:56:51 PM UTC 24 |
| Finished | Oct 09 10:57:06 PM UTC 24 |
| Peak memory | 236488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979095512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl _jtag_prog_failure.2979095512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2590623066 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1167115300 ps |
| CPU time | 25.52 seconds |
| Started | Oct 09 10:56:53 PM UTC 24 |
| Finished | Oct 09 10:57:20 PM UTC 24 |
| Peak memory | 224192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590623066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ ctrl_jtag_regwen_during_op.2590623066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.3695837439 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2106066936 ps |
| CPU time | 14.64 seconds |
| Started | Oct 09 10:56:49 PM UTC 24 |
| Finished | Oct 09 10:57:05 PM UTC 24 |
| Peak memory | 223912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695837439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_s moke.3695837439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.4113359381 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 13077092064 ps |
| CPU time | 59.75 seconds |
| Started | Oct 09 10:56:50 PM UTC 24 |
| Finished | Oct 09 10:57:52 PM UTC 24 |
| Peak memory | 291804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113359381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr l_jtag_state_failure.4113359381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.517431540 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 895084559 ps |
| CPU time | 37.43 seconds |
| Started | Oct 09 10:56:51 PM UTC 24 |
| Finished | Oct 09 10:57:30 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517431540 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_c trl_jtag_state_post_trans.517431540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.2653016833 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 513618230 ps |
| CPU time | 5.39 seconds |
| Started | Oct 09 10:56:44 PM UTC 24 |
| Finished | Oct 09 10:56:51 PM UTC 24 |
| Peak memory | 234512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653016833 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2653016833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2885772637 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1241711628 ps |
| CPU time | 10.04 seconds |
| Started | Oct 09 10:56:46 PM UTC 24 |
| Finished | Oct 09 10:56:58 PM UTC 24 |
| Peak memory | 230212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885772637 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2885772637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.3610006434 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 116644038 ps |
| CPU time | 23.65 seconds |
| Started | Oct 09 10:56:58 PM UTC 24 |
| Finished | Oct 09 10:57:23 PM UTC 24 |
| Peak memory | 290076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610006434 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3610006434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.348267442 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 290310435 ps |
| CPU time | 16.82 seconds |
| Started | Oct 09 10:56:53 PM UTC 24 |
| Finished | Oct 09 10:57:11 PM UTC 24 |
| Peak memory | 232468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348267442 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.348267442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.1344919303 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1553449157 ps |
| CPU time | 10.8 seconds |
| Started | Oct 09 10:56:55 PM UTC 24 |
| Finished | Oct 09 10:57:07 PM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344919303 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_tok en_digest.1344919303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.3888495932 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1684050576 ps |
| CPU time | 6.38 seconds |
| Started | Oct 09 10:56:54 PM UTC 24 |
| Finished | Oct 09 10:57:02 PM UTC 24 |
| Peak memory | 238020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888495932 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_ mux.3888495932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.3865497072 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1148560457 ps |
| CPU time | 11.32 seconds |
| Started | Oct 09 10:56:45 PM UTC 24 |
| Finished | Oct 09 10:56:58 PM UTC 24 |
| Peak memory | 230260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865497072 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3865497072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.261653377 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 37377034 ps |
| CPU time | 1.73 seconds |
| Started | Oct 09 10:56:41 PM UTC 24 |
| Finished | Oct 09 10:56:43 PM UTC 24 |
| Peak memory | 228944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261653377 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.261653377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.2031895701 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 662656473 ps |
| CPU time | 10.88 seconds |
| Started | Oct 09 10:56:43 PM UTC 24 |
| Finished | Oct 09 10:56:55 PM UTC 24 |
| Peak memory | 263276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031895701 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.2031895701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2842295021 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 185468046 ps |
| CPU time | 0.99 seconds |
| Started | Oct 09 10:56:42 PM UTC 24 |
| Finished | Oct 09 10:56:44 PM UTC 24 |
| Peak memory | 217940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842295021 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4. lc_ctrl_volatile_unlock_smoke.2842295021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.1925186535 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 24663832 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 11:01:09 PM UTC 24 |
| Finished | Oct 09 11:01:11 PM UTC 24 |
| Peak memory | 218960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925186535 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1925186535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.29466044 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 633077067 ps |
| CPU time | 14.43 seconds |
| Started | Oct 09 11:01:06 PM UTC 24 |
| Finished | Oct 09 11:01:22 PM UTC 24 |
| Peak memory | 238024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29466044 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.29466044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.4204074184 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 88440179 ps |
| CPU time | 4.08 seconds |
| Started | Oct 09 11:01:07 PM UTC 24 |
| Finished | Oct 09 11:01:13 PM UTC 24 |
| Peak memory | 229388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204074184 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.4204074184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.1704816376 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 132350207 ps |
| CPU time | 4.44 seconds |
| Started | Oct 09 11:01:06 PM UTC 24 |
| Finished | Oct 09 11:01:12 PM UTC 24 |
| Peak memory | 233988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704816376 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1704816376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.4095847298 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 1657251298 ps |
| CPU time | 14.18 seconds |
| Started | Oct 09 11:01:07 PM UTC 24 |
| Finished | Oct 09 11:01:23 PM UTC 24 |
| Peak memory | 232580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095847298 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.4095847298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.2632756945 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 458386338 ps |
| CPU time | 17.33 seconds |
| Started | Oct 09 11:01:08 PM UTC 24 |
| Finished | Oct 09 11:01:26 PM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632756945 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_to ken_digest.2632756945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.1373745128 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 830886268 ps |
| CPU time | 7.89 seconds |
| Started | Oct 09 11:01:07 PM UTC 24 |
| Finished | Oct 09 11:01:17 PM UTC 24 |
| Peak memory | 236932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373745128 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token _mux.1373745128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.435789248 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1584816128 ps |
| CPU time | 16.46 seconds |
| Started | Oct 09 11:01:06 PM UTC 24 |
| Finished | Oct 09 11:01:24 PM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435789248 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.435789248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1655447472 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 47079562 ps |
| CPU time | 3.01 seconds |
| Started | Oct 09 11:01:04 PM UTC 24 |
| Finished | Oct 09 11:01:09 PM UTC 24 |
| Peak memory | 226104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655447472 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1655447472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.3274684329 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 174223052 ps |
| CPU time | 29.13 seconds |
| Started | Oct 09 11:01:04 PM UTC 24 |
| Finished | Oct 09 11:01:35 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274684329 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3274684329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.4100793205 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 181767488 ps |
| CPU time | 5.68 seconds |
| Started | Oct 09 11:01:06 PM UTC 24 |
| Finished | Oct 09 11:01:13 PM UTC 24 |
| Peak memory | 238204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100793205 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.4100793205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.337959622 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 19250723074 ps |
| CPU time | 78.04 seconds |
| Started | Oct 09 11:01:08 PM UTC 24 |
| Finished | Oct 09 11:02:28 PM UTC 24 |
| Peak memory | 263460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=337959622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 40.lc_ctrl_stress_all.337959622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.1222112615 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 3986222614 ps |
| CPU time | 67 seconds |
| Started | Oct 09 11:01:08 PM UTC 24 |
| Finished | Oct 09 11:02:17 PM UTC 24 |
| Peak memory | 238284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222112615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.1222112615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1235562456 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 39579844 ps |
| CPU time | 1.49 seconds |
| Started | Oct 09 11:01:04 PM UTC 24 |
| Finished | Oct 09 11:01:07 PM UTC 24 |
| Peak memory | 228944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235562456 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40 .lc_ctrl_volatile_unlock_smoke.1235562456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/40.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.2592205132 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 22140932 ps |
| CPU time | 1.67 seconds |
| Started | Oct 09 11:01:13 PM UTC 24 |
| Finished | Oct 09 11:01:16 PM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592205132 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2592205132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.542225259 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 438432698 ps |
| CPU time | 16.06 seconds |
| Started | Oct 09 11:01:12 PM UTC 24 |
| Finished | Oct 09 11:01:29 PM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542225259 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.542225259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.1780960035 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 91796698 ps |
| CPU time | 3.6 seconds |
| Started | Oct 09 11:01:13 PM UTC 24 |
| Finished | Oct 09 11:01:18 PM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780960035 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1780960035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.1893863802 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 85596743 ps |
| CPU time | 4.3 seconds |
| Started | Oct 09 11:01:12 PM UTC 24 |
| Finished | Oct 09 11:01:17 PM UTC 24 |
| Peak memory | 236484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893863802 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1893863802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.2798471866 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 808862769 ps |
| CPU time | 16.86 seconds |
| Started | Oct 09 11:01:13 PM UTC 24 |
| Finished | Oct 09 11:01:31 PM UTC 24 |
| Peak memory | 238092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798471866 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2798471866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.4206455982 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 998043319 ps |
| CPU time | 11.17 seconds |
| Started | Oct 09 11:01:13 PM UTC 24 |
| Finished | Oct 09 11:01:26 PM UTC 24 |
| Peak memory | 230264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206455982 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_to ken_digest.4206455982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.2057738517 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 1705248254 ps |
| CPU time | 11.96 seconds |
| Started | Oct 09 11:01:13 PM UTC 24 |
| Finished | Oct 09 11:01:27 PM UTC 24 |
| Peak memory | 238016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057738517 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token _mux.2057738517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.374846641 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 2391097152 ps |
| CPU time | 15.12 seconds |
| Started | Oct 09 11:01:13 PM UTC 24 |
| Finished | Oct 09 11:01:30 PM UTC 24 |
| Peak memory | 230540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374846641 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.374846641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.166360618 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 146650406 ps |
| CPU time | 2.84 seconds |
| Started | Oct 09 11:01:10 PM UTC 24 |
| Finished | Oct 09 11:01:14 PM UTC 24 |
| Peak memory | 226060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166360618 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.166360618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.1126331625 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 243550712 ps |
| CPU time | 26.1 seconds |
| Started | Oct 09 11:01:10 PM UTC 24 |
| Finished | Oct 09 11:01:38 PM UTC 24 |
| Peak memory | 262996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126331625 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1126331625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.3869743956 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 340309936 ps |
| CPU time | 4.43 seconds |
| Started | Oct 09 11:01:12 PM UTC 24 |
| Finished | Oct 09 11:01:17 PM UTC 24 |
| Peak memory | 236956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869743956 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3869743956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.3289031441 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 6424273005 ps |
| CPU time | 83.3 seconds |
| Started | Oct 09 11:01:13 PM UTC 24 |
| Finished | Oct 09 11:02:39 PM UTC 24 |
| Peak memory | 263204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3289031441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 41.lc_ctrl_stress_all.3289031441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.739542819 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 15072929861 ps |
| CPU time | 31.9 seconds |
| Started | Oct 09 11:01:13 PM UTC 24 |
| Finished | Oct 09 11:01:47 PM UTC 24 |
| Peak memory | 263548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739542819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_S EQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_un lock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.739542819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.241926474 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 60082904 ps |
| CPU time | 1.09 seconds |
| Started | Oct 09 11:01:10 PM UTC 24 |
| Finished | Oct 09 11:01:12 PM UTC 24 |
| Peak memory | 218788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241926474 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41. lc_ctrl_volatile_unlock_smoke.241926474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/41.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.3034136711 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 24639403 ps |
| CPU time | 1.31 seconds |
| Started | Oct 09 11:01:19 PM UTC 24 |
| Finished | Oct 09 11:01:22 PM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034136711 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3034136711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1743272215 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 4543328756 ps |
| CPU time | 15.4 seconds |
| Started | Oct 09 11:01:18 PM UTC 24 |
| Finished | Oct 09 11:01:34 PM UTC 24 |
| Peak memory | 238428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743272215 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.1743272215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.631793600 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 2361771416 ps |
| CPU time | 5.38 seconds |
| Started | Oct 09 11:01:18 PM UTC 24 |
| Finished | Oct 09 11:01:24 PM UTC 24 |
| Peak memory | 229468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631793600 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.631793600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.2685136415 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 66907617 ps |
| CPU time | 4.4 seconds |
| Started | Oct 09 11:01:16 PM UTC 24 |
| Finished | Oct 09 11:01:22 PM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685136415 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2685136415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.480652462 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 273449105 ps |
| CPU time | 12.84 seconds |
| Started | Oct 09 11:01:18 PM UTC 24 |
| Finished | Oct 09 11:01:32 PM UTC 24 |
| Peak memory | 238108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480652462 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.480652462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.1377700013 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 822072549 ps |
| CPU time | 11.39 seconds |
| Started | Oct 09 11:01:18 PM UTC 24 |
| Finished | Oct 09 11:01:31 PM UTC 24 |
| Peak memory | 238016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377700013 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_to ken_digest.1377700013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.1648881015 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 1852578124 ps |
| CPU time | 15.63 seconds |
| Started | Oct 09 11:01:18 PM UTC 24 |
| Finished | Oct 09 11:01:35 PM UTC 24 |
| Peak memory | 238088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648881015 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token _mux.1648881015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.2639329744 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 517784302 ps |
| CPU time | 13.4 seconds |
| Started | Oct 09 11:01:18 PM UTC 24 |
| Finished | Oct 09 11:01:32 PM UTC 24 |
| Peak memory | 238360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639329744 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2639329744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.3349279318 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 117499907 ps |
| CPU time | 2.82 seconds |
| Started | Oct 09 11:01:15 PM UTC 24 |
| Finished | Oct 09 11:01:19 PM UTC 24 |
| Peak memory | 224240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349279318 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3349279318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.367874075 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 1111884807 ps |
| CPU time | 24.95 seconds |
| Started | Oct 09 11:01:15 PM UTC 24 |
| Finished | Oct 09 11:01:41 PM UTC 24 |
| Peak memory | 263076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367874075 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.367874075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.1213086519 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 457466172 ps |
| CPU time | 7.7 seconds |
| Started | Oct 09 11:01:15 PM UTC 24 |
| Finished | Oct 09 11:01:24 PM UTC 24 |
| Peak memory | 263076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213086519 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1213086519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.2326007568 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 15554158699 ps |
| CPU time | 70.5 seconds |
| Started | Oct 09 11:01:18 PM UTC 24 |
| Finished | Oct 09 11:02:30 PM UTC 24 |
| Peak memory | 263460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2326007568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 42.lc_ctrl_stress_all.2326007568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.4005236288 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 8375720119 ps |
| CPU time | 20.18 seconds |
| Started | Oct 09 11:01:19 PM UTC 24 |
| Finished | Oct 09 11:01:41 PM UTC 24 |
| Peak memory | 263336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005236288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.4005236288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.977475947 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 21102787 ps |
| CPU time | 1.15 seconds |
| Started | Oct 09 11:01:15 PM UTC 24 |
| Finished | Oct 09 11:01:17 PM UTC 24 |
| Peak memory | 217876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977475947 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42. lc_ctrl_volatile_unlock_smoke.977475947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.330311316 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 176627250 ps |
| CPU time | 1.29 seconds |
| Started | Oct 09 11:01:27 PM UTC 24 |
| Finished | Oct 09 11:01:29 PM UTC 24 |
| Peak memory | 218664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330311316 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.330311316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.3917147536 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 646317149 ps |
| CPU time | 11.97 seconds |
| Started | Oct 09 11:01:23 PM UTC 24 |
| Finished | Oct 09 11:01:37 PM UTC 24 |
| Peak memory | 230420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917147536 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3917147536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.4170708229 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 602333394 ps |
| CPU time | 3.33 seconds |
| Started | Oct 09 11:01:24 PM UTC 24 |
| Finished | Oct 09 11:01:28 PM UTC 24 |
| Peak memory | 229616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170708229 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.4170708229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.880550239 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 213269335 ps |
| CPU time | 3.51 seconds |
| Started | Oct 09 11:01:23 PM UTC 24 |
| Finished | Oct 09 11:01:28 PM UTC 24 |
| Peak memory | 234692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880550239 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.880550239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.286124580 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 218707343 ps |
| CPU time | 11.77 seconds |
| Started | Oct 09 11:01:25 PM UTC 24 |
| Finished | Oct 09 11:01:38 PM UTC 24 |
| Peak memory | 238108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286124580 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.286124580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.2466748378 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 596602092 ps |
| CPU time | 13.87 seconds |
| Started | Oct 09 11:01:25 PM UTC 24 |
| Finished | Oct 09 11:01:41 PM UTC 24 |
| Peak memory | 237952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466748378 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_to ken_digest.2466748378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.1500753213 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 731269120 ps |
| CPU time | 12.53 seconds |
| Started | Oct 09 11:01:25 PM UTC 24 |
| Finished | Oct 09 11:01:39 PM UTC 24 |
| Peak memory | 237764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500753213 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token _mux.1500753213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.767809072 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 239610071 ps |
| CPU time | 9.18 seconds |
| Started | Oct 09 11:01:24 PM UTC 24 |
| Finished | Oct 09 11:01:34 PM UTC 24 |
| Peak memory | 238292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767809072 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.767809072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.1081691468 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 382317984 ps |
| CPU time | 3.02 seconds |
| Started | Oct 09 11:01:19 PM UTC 24 |
| Finished | Oct 09 11:01:24 PM UTC 24 |
| Peak memory | 226100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081691468 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1081691468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.1125788544 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 233269668 ps |
| CPU time | 28.49 seconds |
| Started | Oct 09 11:01:21 PM UTC 24 |
| Finished | Oct 09 11:01:51 PM UTC 24 |
| Peak memory | 260960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125788544 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1125788544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.3325513065 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 70965590 ps |
| CPU time | 8.16 seconds |
| Started | Oct 09 11:01:23 PM UTC 24 |
| Finished | Oct 09 11:01:33 PM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325513065 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3325513065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.3655635941 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 6761506835 ps |
| CPU time | 91.04 seconds |
| Started | Oct 09 11:01:25 PM UTC 24 |
| Finished | Oct 09 11:02:59 PM UTC 24 |
| Peak memory | 296184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3655635941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 43.lc_ctrl_stress_all.3655635941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2532420386 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 19763412735 ps |
| CPU time | 162.48 seconds |
| Started | Oct 09 11:01:25 PM UTC 24 |
| Finished | Oct 09 11:04:11 PM UTC 24 |
| Peak memory | 263256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532420386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.2532420386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.602038106 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 22079208 ps |
| CPU time | 1.93 seconds |
| Started | Oct 09 11:01:19 PM UTC 24 |
| Finished | Oct 09 11:01:23 PM UTC 24 |
| Peak memory | 229192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602038106 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43. lc_ctrl_volatile_unlock_smoke.602038106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.3265157557 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 29525519 ps |
| CPU time | 1.46 seconds |
| Started | Oct 09 11:01:34 PM UTC 24 |
| Finished | Oct 09 11:01:36 PM UTC 24 |
| Peak memory | 218720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265157557 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3265157557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.3747484428 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 212542430 ps |
| CPU time | 10.5 seconds |
| Started | Oct 09 11:01:29 PM UTC 24 |
| Finished | Oct 09 11:01:41 PM UTC 24 |
| Peak memory | 230352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747484428 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3747484428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.1886643075 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 256114900 ps |
| CPU time | 4.06 seconds |
| Started | Oct 09 11:01:31 PM UTC 24 |
| Finished | Oct 09 11:01:36 PM UTC 24 |
| Peak memory | 229276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886643075 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1886643075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.3708793945 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 36268252 ps |
| CPU time | 3.12 seconds |
| Started | Oct 09 11:01:29 PM UTC 24 |
| Finished | Oct 09 11:01:34 PM UTC 24 |
| Peak memory | 234364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708793945 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3708793945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.970959992 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 570205384 ps |
| CPU time | 10.67 seconds |
| Started | Oct 09 11:01:31 PM UTC 24 |
| Finished | Oct 09 11:01:43 PM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970959992 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.970959992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2652617271 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 861947604 ps |
| CPU time | 6.8 seconds |
| Started | Oct 09 11:01:32 PM UTC 24 |
| Finished | Oct 09 11:01:40 PM UTC 24 |
| Peak memory | 237756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652617271 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_to ken_digest.2652617271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.1847421305 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 8283836967 ps |
| CPU time | 12.71 seconds |
| Started | Oct 09 11:01:31 PM UTC 24 |
| Finished | Oct 09 11:01:45 PM UTC 24 |
| Peak memory | 238232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847421305 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token _mux.1847421305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.1588684347 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 440599820 ps |
| CPU time | 7.24 seconds |
| Started | Oct 09 11:01:30 PM UTC 24 |
| Finished | Oct 09 11:01:38 PM UTC 24 |
| Peak memory | 236844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588684347 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1588684347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.2636731795 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 104083622 ps |
| CPU time | 3.91 seconds |
| Started | Oct 09 11:01:27 PM UTC 24 |
| Finished | Oct 09 11:01:32 PM UTC 24 |
| Peak memory | 230124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636731795 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2636731795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.444811072 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 1004409424 ps |
| CPU time | 21.49 seconds |
| Started | Oct 09 11:01:28 PM UTC 24 |
| Finished | Oct 09 11:01:51 PM UTC 24 |
| Peak memory | 259168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444811072 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.444811072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.3980103934 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 267322964 ps |
| CPU time | 4.09 seconds |
| Started | Oct 09 11:01:28 PM UTC 24 |
| Finished | Oct 09 11:01:33 PM UTC 24 |
| Peak memory | 238496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980103934 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3980103934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.1129239440 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 4447167271 ps |
| CPU time | 95.89 seconds |
| Started | Oct 09 11:01:32 PM UTC 24 |
| Finished | Oct 09 11:03:10 PM UTC 24 |
| Peak memory | 293920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1129239440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 44.lc_ctrl_stress_all.1129239440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.4141286951 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4770154209 ps |
| CPU time | 168.65 seconds |
| Started | Oct 09 11:01:33 PM UTC 24 |
| Finished | Oct 09 11:04:25 PM UTC 24 |
| Peak memory | 433312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141286951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.4141286951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3200242525 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 13653275 ps |
| CPU time | 1.04 seconds |
| Started | Oct 09 11:01:28 PM UTC 24 |
| Finished | Oct 09 11:01:30 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200242525 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44 .lc_ctrl_volatile_unlock_smoke.3200242525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/44.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.1296319465 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 49145800 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 11:01:37 PM UTC 24 |
| Finished | Oct 09 11:01:39 PM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296319465 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.1296319465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.3727557156 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 1062711182 ps |
| CPU time | 11.8 seconds |
| Started | Oct 09 11:01:35 PM UTC 24 |
| Finished | Oct 09 11:01:48 PM UTC 24 |
| Peak memory | 238036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727557156 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3727557156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.3565663954 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 871038809 ps |
| CPU time | 6.9 seconds |
| Started | Oct 09 11:01:37 PM UTC 24 |
| Finished | Oct 09 11:01:45 PM UTC 24 |
| Peak memory | 229496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565663954 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3565663954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.3482887300 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 88022834 ps |
| CPU time | 3.28 seconds |
| Started | Oct 09 11:01:35 PM UTC 24 |
| Finished | Oct 09 11:01:40 PM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482887300 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3482887300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.1162663916 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 341661576 ps |
| CPU time | 15.7 seconds |
| Started | Oct 09 11:01:37 PM UTC 24 |
| Finished | Oct 09 11:01:54 PM UTC 24 |
| Peak memory | 232376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162663916 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1162663916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.3498088361 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 1724253750 ps |
| CPU time | 16.88 seconds |
| Started | Oct 09 11:01:37 PM UTC 24 |
| Finished | Oct 09 11:01:55 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498088361 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_to ken_digest.3498088361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.3758519242 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 4013384749 ps |
| CPU time | 10.55 seconds |
| Started | Oct 09 11:01:37 PM UTC 24 |
| Finished | Oct 09 11:01:48 PM UTC 24 |
| Peak memory | 230728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758519242 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token _mux.3758519242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.437012855 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1081730645 ps |
| CPU time | 10.57 seconds |
| Started | Oct 09 11:01:35 PM UTC 24 |
| Finished | Oct 09 11:01:47 PM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437012855 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.437012855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.3513634380 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 79042538 ps |
| CPU time | 2.22 seconds |
| Started | Oct 09 11:01:34 PM UTC 24 |
| Finished | Oct 09 11:01:37 PM UTC 24 |
| Peak memory | 224052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513634380 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3513634380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.3686847917 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 191005350 ps |
| CPU time | 23.43 seconds |
| Started | Oct 09 11:01:35 PM UTC 24 |
| Finished | Oct 09 11:02:00 PM UTC 24 |
| Peak memory | 263084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686847917 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3686847917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.558988402 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 531362234 ps |
| CPU time | 4.47 seconds |
| Started | Oct 09 11:01:35 PM UTC 24 |
| Finished | Oct 09 11:01:41 PM UTC 24 |
| Peak memory | 236884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558988402 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.558988402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.2110594341 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 2233480276 ps |
| CPU time | 45.34 seconds |
| Started | Oct 09 11:01:37 PM UTC 24 |
| Finished | Oct 09 11:02:24 PM UTC 24 |
| Peak memory | 232808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2110594341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 45.lc_ctrl_stress_all.2110594341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.3383740103 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 3867616905 ps |
| CPU time | 106.07 seconds |
| Started | Oct 09 11:01:37 PM UTC 24 |
| Finished | Oct 09 11:03:25 PM UTC 24 |
| Peak memory | 248528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383740103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.3383740103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.4104642633 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 35126959 ps |
| CPU time | 1.16 seconds |
| Started | Oct 09 11:01:34 PM UTC 24 |
| Finished | Oct 09 11:01:36 PM UTC 24 |
| Peak memory | 220772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104642633 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45 .lc_ctrl_volatile_unlock_smoke.4104642633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.707822719 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 81549725 ps |
| CPU time | 1.81 seconds |
| Started | Oct 09 11:01:43 PM UTC 24 |
| Finished | Oct 09 11:01:46 PM UTC 24 |
| Peak memory | 218784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707822719 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.707822719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.4154731699 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 2410516393 ps |
| CPU time | 20.07 seconds |
| Started | Oct 09 11:01:40 PM UTC 24 |
| Finished | Oct 09 11:02:01 PM UTC 24 |
| Peak memory | 232860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154731699 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.4154731699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.458243110 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 2667477372 ps |
| CPU time | 5.2 seconds |
| Started | Oct 09 11:01:40 PM UTC 24 |
| Finished | Oct 09 11:01:46 PM UTC 24 |
| Peak memory | 229592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458243110 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.458243110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.453094220 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 539632287 ps |
| CPU time | 3.09 seconds |
| Started | Oct 09 11:01:39 PM UTC 24 |
| Finished | Oct 09 11:01:43 PM UTC 24 |
| Peak memory | 230404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453094220 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.453094220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.954170981 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 607901665 ps |
| CPU time | 12.37 seconds |
| Started | Oct 09 11:01:41 PM UTC 24 |
| Finished | Oct 09 11:01:55 PM UTC 24 |
| Peak memory | 232396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954170981 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.954170981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.2063694227 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 5608941463 ps |
| CPU time | 17.18 seconds |
| Started | Oct 09 11:01:41 PM UTC 24 |
| Finished | Oct 09 11:02:00 PM UTC 24 |
| Peak memory | 230456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063694227 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_to ken_digest.2063694227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.1992894008 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 863649766 ps |
| CPU time | 8.52 seconds |
| Started | Oct 09 11:01:41 PM UTC 24 |
| Finished | Oct 09 11:01:51 PM UTC 24 |
| Peak memory | 238016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992894008 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token _mux.1992894008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.4237827543 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 1022792096 ps |
| CPU time | 10.88 seconds |
| Started | Oct 09 11:01:40 PM UTC 24 |
| Finished | Oct 09 11:01:52 PM UTC 24 |
| Peak memory | 230508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237827543 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.4237827543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.1527128359 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 50001020 ps |
| CPU time | 1.7 seconds |
| Started | Oct 09 11:01:38 PM UTC 24 |
| Finished | Oct 09 11:01:41 PM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527128359 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1527128359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.2869784006 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 2251110297 ps |
| CPU time | 29.22 seconds |
| Started | Oct 09 11:01:38 PM UTC 24 |
| Finished | Oct 09 11:02:09 PM UTC 24 |
| Peak memory | 259032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869784006 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2869784006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.3975911240 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 250179088 ps |
| CPU time | 3.94 seconds |
| Started | Oct 09 11:01:38 PM UTC 24 |
| Finished | Oct 09 11:01:44 PM UTC 24 |
| Peak memory | 234908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975911240 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3975911240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.178058762 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 29029156822 ps |
| CPU time | 135.89 seconds |
| Started | Oct 09 11:01:41 PM UTC 24 |
| Finished | Oct 09 11:04:00 PM UTC 24 |
| Peak memory | 263192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=178058762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 46.lc_ctrl_stress_all.178058762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.1653665725 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 3182941809 ps |
| CPU time | 60.22 seconds |
| Started | Oct 09 11:01:43 PM UTC 24 |
| Finished | Oct 09 11:02:45 PM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653665725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.1653665725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2907238491 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 117899550 ps |
| CPU time | 1.53 seconds |
| Started | Oct 09 11:01:38 PM UTC 24 |
| Finished | Oct 09 11:01:41 PM UTC 24 |
| Peak memory | 228996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907238491 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46 .lc_ctrl_volatile_unlock_smoke.2907238491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.1344998169 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 31604464 ps |
| CPU time | 1.1 seconds |
| Started | Oct 09 11:01:48 PM UTC 24 |
| Finished | Oct 09 11:01:50 PM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344998169 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1344998169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.2839793291 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 1539809000 ps |
| CPU time | 20.28 seconds |
| Started | Oct 09 11:01:45 PM UTC 24 |
| Finished | Oct 09 11:02:07 PM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839793291 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2839793291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.888340190 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 4066959118 ps |
| CPU time | 5.56 seconds |
| Started | Oct 09 11:01:45 PM UTC 24 |
| Finished | Oct 09 11:01:52 PM UTC 24 |
| Peak memory | 229964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888340190 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.888340190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.686546929 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 81829063 ps |
| CPU time | 3.16 seconds |
| Started | Oct 09 11:01:44 PM UTC 24 |
| Finished | Oct 09 11:01:49 PM UTC 24 |
| Peak memory | 234500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686546929 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.686546929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.480463573 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 2144940488 ps |
| CPU time | 10.04 seconds |
| Started | Oct 09 11:01:47 PM UTC 24 |
| Finished | Oct 09 11:01:58 PM UTC 24 |
| Peak memory | 238104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480463573 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.480463573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.2101655320 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 654979292 ps |
| CPU time | 13.14 seconds |
| Started | Oct 09 11:01:47 PM UTC 24 |
| Finished | Oct 09 11:02:01 PM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101655320 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_to ken_digest.2101655320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.2921475966 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 1285599033 ps |
| CPU time | 9.06 seconds |
| Started | Oct 09 11:01:47 PM UTC 24 |
| Finished | Oct 09 11:01:57 PM UTC 24 |
| Peak memory | 238096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921475966 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token _mux.2921475966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.2445365075 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 636790620 ps |
| CPU time | 10.15 seconds |
| Started | Oct 09 11:01:45 PM UTC 24 |
| Finished | Oct 09 11:01:57 PM UTC 24 |
| Peak memory | 237180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445365075 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2445365075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.1831081568 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 469089486 ps |
| CPU time | 8.41 seconds |
| Started | Oct 09 11:01:43 PM UTC 24 |
| Finished | Oct 09 11:01:52 PM UTC 24 |
| Peak memory | 230124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831081568 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1831081568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1405799219 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 742638858 ps |
| CPU time | 18.9 seconds |
| Started | Oct 09 11:01:43 PM UTC 24 |
| Finished | Oct 09 11:02:03 PM UTC 24 |
| Peak memory | 263000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405799219 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1405799219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.4122994485 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 459185059 ps |
| CPU time | 9.68 seconds |
| Started | Oct 09 11:01:44 PM UTC 24 |
| Finished | Oct 09 11:01:55 PM UTC 24 |
| Peak memory | 260800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122994485 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.4122994485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.1067598183 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 34839242193 ps |
| CPU time | 162.91 seconds |
| Started | Oct 09 11:01:48 PM UTC 24 |
| Finished | Oct 09 11:04:34 PM UTC 24 |
| Peak memory | 263464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1067598183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 47.lc_ctrl_stress_all.1067598183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1840615775 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 40926903 ps |
| CPU time | 1.22 seconds |
| Started | Oct 09 11:01:43 PM UTC 24 |
| Finished | Oct 09 11:01:45 PM UTC 24 |
| Peak memory | 218468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840615775 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47 .lc_ctrl_volatile_unlock_smoke.1840615775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/47.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.952261341 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 22360334 ps |
| CPU time | 1.43 seconds |
| Started | Oct 09 11:01:56 PM UTC 24 |
| Finished | Oct 09 11:01:58 PM UTC 24 |
| Peak memory | 218960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952261341 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.952261341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.44997742 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 363936120 ps |
| CPU time | 10.74 seconds |
| Started | Oct 09 11:01:52 PM UTC 24 |
| Finished | Oct 09 11:02:04 PM UTC 24 |
| Peak memory | 238020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44997742 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.44997742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.765639250 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 718642311 ps |
| CPU time | 9.97 seconds |
| Started | Oct 09 11:01:54 PM UTC 24 |
| Finished | Oct 09 11:02:05 PM UTC 24 |
| Peak memory | 229392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765639250 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.765639250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.4076439219 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 1367138922 ps |
| CPU time | 4.19 seconds |
| Started | Oct 09 11:01:52 PM UTC 24 |
| Finished | Oct 09 11:01:58 PM UTC 24 |
| Peak memory | 234504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076439219 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.4076439219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.664116883 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 576703543 ps |
| CPU time | 18.43 seconds |
| Started | Oct 09 11:01:54 PM UTC 24 |
| Finished | Oct 09 11:02:14 PM UTC 24 |
| Peak memory | 232384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664116883 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.664116883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.3005662376 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 401732454 ps |
| CPU time | 11.46 seconds |
| Started | Oct 09 11:01:54 PM UTC 24 |
| Finished | Oct 09 11:02:07 PM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005662376 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_to ken_digest.3005662376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.1276727808 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 1570861786 ps |
| CPU time | 10.2 seconds |
| Started | Oct 09 11:01:54 PM UTC 24 |
| Finished | Oct 09 11:02:05 PM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276727808 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token _mux.1276727808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.1650439336 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 1629113820 ps |
| CPU time | 8.23 seconds |
| Started | Oct 09 11:01:52 PM UTC 24 |
| Finished | Oct 09 11:02:02 PM UTC 24 |
| Peak memory | 236916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650439336 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1650439336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.2291017684 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 49047691 ps |
| CPU time | 3.26 seconds |
| Started | Oct 09 11:01:50 PM UTC 24 |
| Finished | Oct 09 11:01:54 PM UTC 24 |
| Peak memory | 230128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291017684 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2291017684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.3040361783 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 807310304 ps |
| CPU time | 17.75 seconds |
| Started | Oct 09 11:01:50 PM UTC 24 |
| Finished | Oct 09 11:02:09 PM UTC 24 |
| Peak memory | 258896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040361783 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3040361783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.1328199299 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 333607570 ps |
| CPU time | 8.98 seconds |
| Started | Oct 09 11:01:51 PM UTC 24 |
| Finished | Oct 09 11:02:01 PM UTC 24 |
| Peak memory | 261220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328199299 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1328199299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.128400865 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 23581373461 ps |
| CPU time | 706.62 seconds |
| Started | Oct 09 11:01:54 PM UTC 24 |
| Finished | Oct 09 11:13:51 PM UTC 24 |
| Peak memory | 291792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=128400865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 48.lc_ctrl_stress_all.128400865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1625052014 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 16298356250 ps |
| CPU time | 179.1 seconds |
| Started | Oct 09 11:01:56 PM UTC 24 |
| Finished | Oct 09 11:04:57 PM UTC 24 |
| Peak memory | 345260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625052014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1625052014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1299514319 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 33858098 ps |
| CPU time | 1.27 seconds |
| Started | Oct 09 11:01:50 PM UTC 24 |
| Finished | Oct 09 11:01:52 PM UTC 24 |
| Peak memory | 220772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299514319 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48 .lc_ctrl_volatile_unlock_smoke.1299514319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.3418292647 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 39378753 ps |
| CPU time | 1.41 seconds |
| Started | Oct 09 11:02:02 PM UTC 24 |
| Finished | Oct 09 11:02:05 PM UTC 24 |
| Peak memory | 218960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418292647 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3418292647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.4089708893 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 319849934 ps |
| CPU time | 11.93 seconds |
| Started | Oct 09 11:01:58 PM UTC 24 |
| Finished | Oct 09 11:02:11 PM UTC 24 |
| Peak memory | 230276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089708893 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.4089708893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.176176928 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 896361995 ps |
| CPU time | 4.98 seconds |
| Started | Oct 09 11:01:59 PM UTC 24 |
| Finished | Oct 09 11:02:06 PM UTC 24 |
| Peak memory | 229284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176176928 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.176176928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.4017940152 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 125462044 ps |
| CPU time | 4.05 seconds |
| Started | Oct 09 11:01:58 PM UTC 24 |
| Finished | Oct 09 11:02:03 PM UTC 24 |
| Peak memory | 234504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017940152 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.4017940152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.3198027827 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 1491590215 ps |
| CPU time | 11.8 seconds |
| Started | Oct 09 11:02:00 PM UTC 24 |
| Finished | Oct 09 11:02:12 PM UTC 24 |
| Peak memory | 237956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198027827 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3198027827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.38245018 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1221283533 ps |
| CPU time | 10.41 seconds |
| Started | Oct 09 11:02:01 PM UTC 24 |
| Finished | Oct 09 11:02:12 PM UTC 24 |
| Peak memory | 238096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38245018 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_toke n_digest.38245018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.1869224023 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 1418645909 ps |
| CPU time | 10.44 seconds |
| Started | Oct 09 11:02:00 PM UTC 24 |
| Finished | Oct 09 11:02:11 PM UTC 24 |
| Peak memory | 236980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869224023 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token _mux.1869224023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.1560829986 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 272483497 ps |
| CPU time | 11.45 seconds |
| Started | Oct 09 11:01:59 PM UTC 24 |
| Finished | Oct 09 11:02:12 PM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560829986 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1560829986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.2763677605 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 85918308 ps |
| CPU time | 1.47 seconds |
| Started | Oct 09 11:01:56 PM UTC 24 |
| Finished | Oct 09 11:01:58 PM UTC 24 |
| Peak memory | 228548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763677605 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2763677605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.1755097487 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1338198175 ps |
| CPU time | 23.01 seconds |
| Started | Oct 09 11:01:57 PM UTC 24 |
| Finished | Oct 09 11:02:21 PM UTC 24 |
| Peak memory | 260964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755097487 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1755097487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.126863778 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 223557482 ps |
| CPU time | 8.42 seconds |
| Started | Oct 09 11:01:58 PM UTC 24 |
| Finished | Oct 09 11:02:08 PM UTC 24 |
| Peak memory | 258976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126863778 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.126863778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.3163075250 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 15281827520 ps |
| CPU time | 55.76 seconds |
| Started | Oct 09 11:02:01 PM UTC 24 |
| Finished | Oct 09 11:02:58 PM UTC 24 |
| Peak memory | 263460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3163075250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 49.lc_ctrl_stress_all.3163075250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1794800170 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 39291247 ps |
| CPU time | 1.17 seconds |
| Started | Oct 09 11:01:56 PM UTC 24 |
| Finished | Oct 09 11:01:58 PM UTC 24 |
| Peak memory | 217936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794800170 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49 .lc_ctrl_volatile_unlock_smoke.1794800170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/49.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.1689840739 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 18003289 ps |
| CPU time | 1.14 seconds |
| Started | Oct 09 10:57:10 PM UTC 24 |
| Finished | Oct 09 10:57:12 PM UTC 24 |
| Peak memory | 218900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689840739 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1689840739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.4071068969 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 12597952 ps |
| CPU time | 1.18 seconds |
| Started | Oct 09 10:57:01 PM UTC 24 |
| Finished | Oct 09 10:57:03 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071068969 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.4071068969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.702085239 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 379700706 ps |
| CPU time | 12.99 seconds |
| Started | Oct 09 10:57:00 PM UTC 24 |
| Finished | Oct 09 10:57:14 PM UTC 24 |
| Peak memory | 238020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702085239 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.702085239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.3448663967 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 295868170 ps |
| CPU time | 7.31 seconds |
| Started | Oct 09 10:57:04 PM UTC 24 |
| Finished | Oct 09 10:57:12 PM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448663967 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3448663967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.1959575999 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2130868373 ps |
| CPU time | 26.56 seconds |
| Started | Oct 09 10:57:03 PM UTC 24 |
| Finished | Oct 09 10:57:31 PM UTC 24 |
| Peak memory | 230340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959575999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jt ag_errors.1959575999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.3562202182 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 171927224 ps |
| CPU time | 4.26 seconds |
| Started | Oct 09 10:57:04 PM UTC 24 |
| Finished | Oct 09 10:57:09 PM UTC 24 |
| Peak memory | 229532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562202182 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_prior ity.3562202182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.971021855 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 508347459 ps |
| CPU time | 6.17 seconds |
| Started | Oct 09 10:57:03 PM UTC 24 |
| Finished | Oct 09 10:57:10 PM UTC 24 |
| Peak memory | 236684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971021855 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_prog_failure.971021855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.518652738 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 6403327473 ps |
| CPU time | 32.33 seconds |
| Started | Oct 09 10:57:04 PM UTC 24 |
| Finished | Oct 09 10:57:38 PM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518652738 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_c trl_jtag_regwen_during_op.518652738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.3304411593 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1325340296 ps |
| CPU time | 5.98 seconds |
| Started | Oct 09 10:57:02 PM UTC 24 |
| Finished | Oct 09 10:57:10 PM UTC 24 |
| Peak memory | 223908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304411593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_s moke.3304411593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1197731108 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4776449409 ps |
| CPU time | 51.14 seconds |
| Started | Oct 09 10:57:02 PM UTC 24 |
| Finished | Oct 09 10:57:55 PM UTC 24 |
| Peak memory | 285852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197731108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr l_jtag_state_failure.1197731108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.3994157528 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 766954365 ps |
| CPU time | 18.77 seconds |
| Started | Oct 09 10:57:03 PM UTC 24 |
| Finished | Oct 09 10:57:23 PM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994157528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ ctrl_jtag_state_post_trans.3994157528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.456941653 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 81467299 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 10:57:00 PM UTC 24 |
| Finished | Oct 09 10:57:03 PM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456941653 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.456941653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.2554391224 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 182452891 ps |
| CPU time | 6.17 seconds |
| Started | Oct 09 10:57:01 PM UTC 24 |
| Finished | Oct 09 10:57:08 PM UTC 24 |
| Peak memory | 230288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554391224 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2554391224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.1750545733 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1698461801 ps |
| CPU time | 12.44 seconds |
| Started | Oct 09 10:57:06 PM UTC 24 |
| Finished | Oct 09 10:57:20 PM UTC 24 |
| Peak memory | 230480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750545733 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1750545733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.1621967231 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 1271551934 ps |
| CPU time | 12.77 seconds |
| Started | Oct 09 10:57:07 PM UTC 24 |
| Finished | Oct 09 10:57:21 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621967231 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_tok en_digest.1621967231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.470005788 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 899881109 ps |
| CPU time | 10.39 seconds |
| Started | Oct 09 10:57:06 PM UTC 24 |
| Finished | Oct 09 10:57:18 PM UTC 24 |
| Peak memory | 238032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470005788 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.470005788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.807327118 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1242426715 ps |
| CPU time | 8.34 seconds |
| Started | Oct 09 10:57:01 PM UTC 24 |
| Finished | Oct 09 10:57:11 PM UTC 24 |
| Peak memory | 238020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807327118 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.807327118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.1757613588 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 232092556 ps |
| CPU time | 5.73 seconds |
| Started | Oct 09 10:56:58 PM UTC 24 |
| Finished | Oct 09 10:57:05 PM UTC 24 |
| Peak memory | 230120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757613588 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1757613588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.4266135146 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 187702486 ps |
| CPU time | 20.61 seconds |
| Started | Oct 09 10:57:00 PM UTC 24 |
| Finished | Oct 09 10:57:22 PM UTC 24 |
| Peak memory | 263272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266135146 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.4266135146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2142619698 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 442405245 ps |
| CPU time | 7.44 seconds |
| Started | Oct 09 10:57:00 PM UTC 24 |
| Finished | Oct 09 10:57:08 PM UTC 24 |
| Peak memory | 258844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142619698 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2142619698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.3360257027 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 4056961951 ps |
| CPU time | 50.26 seconds |
| Started | Oct 09 10:57:07 PM UTC 24 |
| Finished | Oct 09 10:57:59 PM UTC 24 |
| Peak memory | 230656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3360257027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 5.lc_ctrl_stress_all.3360257027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.993338153 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 13850611 ps |
| CPU time | 1.37 seconds |
| Started | Oct 09 10:57:00 PM UTC 24 |
| Finished | Oct 09 10:57:02 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993338153 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.l c_ctrl_volatile_unlock_smoke.993338153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.3943890527 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 79715018 ps |
| CPU time | 1.63 seconds |
| Started | Oct 09 10:57:22 PM UTC 24 |
| Finished | Oct 09 10:57:24 PM UTC 24 |
| Peak memory | 218256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943890527 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3943890527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.4235652563 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 18914488 ps |
| CPU time | 1.24 seconds |
| Started | Oct 09 10:57:13 PM UTC 24 |
| Finished | Oct 09 10:57:16 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235652563 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.4235652563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.9471651 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 360047593 ps |
| CPU time | 15.19 seconds |
| Started | Oct 09 10:57:11 PM UTC 24 |
| Finished | Oct 09 10:57:28 PM UTC 24 |
| Peak memory | 230328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9471651 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.9471651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.2339944469 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 45044107 ps |
| CPU time | 2.52 seconds |
| Started | Oct 09 10:57:16 PM UTC 24 |
| Finished | Oct 09 10:57:20 PM UTC 24 |
| Peak memory | 229356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339944469 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2339944469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.1076103391 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 20990457428 ps |
| CPU time | 20.11 seconds |
| Started | Oct 09 10:57:15 PM UTC 24 |
| Finished | Oct 09 10:57:37 PM UTC 24 |
| Peak memory | 230660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076103391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jt ag_errors.1076103391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.2843835631 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1844626696 ps |
| CPU time | 6.71 seconds |
| Started | Oct 09 10:57:18 PM UTC 24 |
| Finished | Oct 09 10:57:26 PM UTC 24 |
| Peak memory | 229856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843835631 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_prior ity.2843835631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3248328258 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 205263124 ps |
| CPU time | 6.09 seconds |
| Started | Oct 09 10:57:15 PM UTC 24 |
| Finished | Oct 09 10:57:22 PM UTC 24 |
| Peak memory | 234640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248328258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl _jtag_prog_failure.3248328258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3190622349 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 548216033 ps |
| CPU time | 14.75 seconds |
| Started | Oct 09 10:57:19 PM UTC 24 |
| Finished | Oct 09 10:57:35 PM UTC 24 |
| Peak memory | 230064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190622349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ ctrl_jtag_regwen_during_op.3190622349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.2703860280 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 283853407 ps |
| CPU time | 5.84 seconds |
| Started | Oct 09 10:57:13 PM UTC 24 |
| Finished | Oct 09 10:57:20 PM UTC 24 |
| Peak memory | 223908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703860280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_s moke.2703860280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.137720244 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1411399138 ps |
| CPU time | 30.13 seconds |
| Started | Oct 09 10:57:14 PM UTC 24 |
| Finished | Oct 09 10:57:45 PM UTC 24 |
| Peak memory | 263268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137720244 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl _jtag_state_failure.137720244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.336160223 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 412561568 ps |
| CPU time | 18.14 seconds |
| Started | Oct 09 10:57:14 PM UTC 24 |
| Finished | Oct 09 10:57:33 PM UTC 24 |
| Peak memory | 263012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336160223 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_c trl_jtag_state_post_trans.336160223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.839143684 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 645272079 ps |
| CPU time | 5.27 seconds |
| Started | Oct 09 10:57:11 PM UTC 24 |
| Finished | Oct 09 10:57:18 PM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839143684 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.839143684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.1930007473 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 930464734 ps |
| CPU time | 7.85 seconds |
| Started | Oct 09 10:57:13 PM UTC 24 |
| Finished | Oct 09 10:57:22 PM UTC 24 |
| Peak memory | 224260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930007473 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1930007473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.1903977782 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1551697974 ps |
| CPU time | 15.76 seconds |
| Started | Oct 09 10:57:19 PM UTC 24 |
| Finished | Oct 09 10:57:36 PM UTC 24 |
| Peak memory | 237760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903977782 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1903977782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.536324902 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2244694358 ps |
| CPU time | 12.3 seconds |
| Started | Oct 09 10:57:20 PM UTC 24 |
| Finished | Oct 09 10:57:34 PM UTC 24 |
| Peak memory | 230460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536324902 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_toke n_digest.536324902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.2255054797 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1828419810 ps |
| CPU time | 11.78 seconds |
| Started | Oct 09 10:57:20 PM UTC 24 |
| Finished | Oct 09 10:57:33 PM UTC 24 |
| Peak memory | 230528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255054797 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_ mux.2255054797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.772806042 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 1164363157 ps |
| CPU time | 9.41 seconds |
| Started | Oct 09 10:57:11 PM UTC 24 |
| Finished | Oct 09 10:57:22 PM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772806042 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.772806042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2917366318 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 189633003 ps |
| CPU time | 1.92 seconds |
| Started | Oct 09 10:57:10 PM UTC 24 |
| Finished | Oct 09 10:57:13 PM UTC 24 |
| Peak memory | 222396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917366318 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2917366318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.2466585297 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 845461920 ps |
| CPU time | 22.14 seconds |
| Started | Oct 09 10:57:10 PM UTC 24 |
| Finished | Oct 09 10:57:33 PM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466585297 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2466585297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.383217723 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 80623134 ps |
| CPU time | 9.13 seconds |
| Started | Oct 09 10:57:11 PM UTC 24 |
| Finished | Oct 09 10:57:22 PM UTC 24 |
| Peak memory | 263268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383217723 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.383217723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.484589743 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 17839166025 ps |
| CPU time | 112.93 seconds |
| Started | Oct 09 10:57:20 PM UTC 24 |
| Finished | Oct 09 10:59:16 PM UTC 24 |
| Peak memory | 238224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=484589743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 6.lc_ctrl_stress_all.484589743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.503196423 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 123643724 ps |
| CPU time | 1.26 seconds |
| Started | Oct 09 10:57:10 PM UTC 24 |
| Finished | Oct 09 10:57:12 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503196423 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.l c_ctrl_volatile_unlock_smoke.503196423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.3163769403 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 49064016 ps |
| CPU time | 1.3 seconds |
| Started | Oct 09 10:57:31 PM UTC 24 |
| Finished | Oct 09 10:57:34 PM UTC 24 |
| Peak memory | 218660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163769403 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3163769403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.2510461939 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 510929194 ps |
| CPU time | 12.97 seconds |
| Started | Oct 09 10:57:23 PM UTC 24 |
| Finished | Oct 09 10:57:38 PM UTC 24 |
| Peak memory | 238108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510461939 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2510461939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.17079009 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2681493309 ps |
| CPU time | 3.32 seconds |
| Started | Oct 09 10:57:26 PM UTC 24 |
| Finished | Oct 09 10:57:31 PM UTC 24 |
| Peak memory | 229724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17079009 -assert nopost proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.17079009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3962531575 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2307871421 ps |
| CPU time | 26.7 seconds |
| Started | Oct 09 10:57:25 PM UTC 24 |
| Finished | Oct 09 10:57:53 PM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962531575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jt ag_errors.3962531575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.2513178537 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 432081047 ps |
| CPU time | 2.51 seconds |
| Started | Oct 09 10:57:26 PM UTC 24 |
| Finished | Oct 09 10:57:30 PM UTC 24 |
| Peak memory | 229580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513178537 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_prior ity.2513178537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1892907805 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1686184293 ps |
| CPU time | 8.22 seconds |
| Started | Oct 09 10:57:25 PM UTC 24 |
| Finished | Oct 09 10:57:34 PM UTC 24 |
| Peak memory | 236408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892907805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl _jtag_prog_failure.1892907805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1995573697 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3349510385 ps |
| CPU time | 22.73 seconds |
| Started | Oct 09 10:57:27 PM UTC 24 |
| Finished | Oct 09 10:57:51 PM UTC 24 |
| Peak memory | 224316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995573697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ ctrl_jtag_regwen_during_op.1995573697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.1202670729 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 460974059 ps |
| CPU time | 2.89 seconds |
| Started | Oct 09 10:57:25 PM UTC 24 |
| Finished | Oct 09 10:57:29 PM UTC 24 |
| Peak memory | 230056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202670729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_s moke.1202670729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.3520967386 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1785259919 ps |
| CPU time | 69.98 seconds |
| Started | Oct 09 10:57:25 PM UTC 24 |
| Finished | Oct 09 10:58:37 PM UTC 24 |
| Peak memory | 287580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520967386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr l_jtag_state_failure.3520967386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.4143926347 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 842732229 ps |
| CPU time | 23.15 seconds |
| Started | Oct 09 10:57:25 PM UTC 24 |
| Finished | Oct 09 10:57:50 PM UTC 24 |
| Peak memory | 258836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143926347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ ctrl_jtag_state_post_trans.4143926347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.335242847 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 100614783 ps |
| CPU time | 4.19 seconds |
| Started | Oct 09 10:57:23 PM UTC 24 |
| Finished | Oct 09 10:57:29 PM UTC 24 |
| Peak memory | 230344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335242847 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.335242847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.2938215705 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 649272856 ps |
| CPU time | 7.91 seconds |
| Started | Oct 09 10:57:24 PM UTC 24 |
| Finished | Oct 09 10:57:33 PM UTC 24 |
| Peak memory | 223988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938215705 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2938215705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.4085746701 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 822205538 ps |
| CPU time | 11.98 seconds |
| Started | Oct 09 10:57:29 PM UTC 24 |
| Finished | Oct 09 10:57:42 PM UTC 24 |
| Peak memory | 230480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085746701 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.4085746701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1043117143 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 446891326 ps |
| CPU time | 8.95 seconds |
| Started | Oct 09 10:57:30 PM UTC 24 |
| Finished | Oct 09 10:57:40 PM UTC 24 |
| Peak memory | 230588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043117143 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_tok en_digest.1043117143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.3310028182 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 8618850263 ps |
| CPU time | 13.74 seconds |
| Started | Oct 09 10:57:29 PM UTC 24 |
| Finished | Oct 09 10:57:44 PM UTC 24 |
| Peak memory | 238144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310028182 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_ mux.3310028182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.3551133645 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 4062703013 ps |
| CPU time | 9.14 seconds |
| Started | Oct 09 10:57:23 PM UTC 24 |
| Finished | Oct 09 10:57:34 PM UTC 24 |
| Peak memory | 230456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551133645 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3551133645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.2413318276 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 146334596 ps |
| CPU time | 2.96 seconds |
| Started | Oct 09 10:57:22 PM UTC 24 |
| Finished | Oct 09 10:57:26 PM UTC 24 |
| Peak memory | 230136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413318276 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2413318276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.773770340 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 317313057 ps |
| CPU time | 23.36 seconds |
| Started | Oct 09 10:57:23 PM UTC 24 |
| Finished | Oct 09 10:57:48 PM UTC 24 |
| Peak memory | 263084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773770340 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.773770340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3563533382 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 623374432 ps |
| CPU time | 10.05 seconds |
| Started | Oct 09 10:57:23 PM UTC 24 |
| Finished | Oct 09 10:57:35 PM UTC 24 |
| Peak memory | 262940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563533382 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3563533382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.966403089 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 5541199914 ps |
| CPU time | 55.23 seconds |
| Started | Oct 09 10:57:30 PM UTC 24 |
| Finished | Oct 09 10:58:27 PM UTC 24 |
| Peak memory | 293768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=966403089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_ name 7.lc_ctrl_stress_all.966403089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3980319802 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 45416793 ps |
| CPU time | 1.21 seconds |
| Started | Oct 09 10:57:22 PM UTC 24 |
| Finished | Oct 09 10:57:24 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980319802 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7. lc_ctrl_volatile_unlock_smoke.3980319802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.1808525295 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 60349262 ps |
| CPU time | 1.65 seconds |
| Started | Oct 09 10:57:39 PM UTC 24 |
| Finished | Oct 09 10:57:42 PM UTC 24 |
| Peak memory | 218780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808525295 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1808525295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.2336409321 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 282351859 ps |
| CPU time | 18.46 seconds |
| Started | Oct 09 10:57:35 PM UTC 24 |
| Finished | Oct 09 10:57:55 PM UTC 24 |
| Peak memory | 238032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336409321 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2336409321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.1246712117 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 413313095 ps |
| CPU time | 5.43 seconds |
| Started | Oct 09 10:57:37 PM UTC 24 |
| Finished | Oct 09 10:57:44 PM UTC 24 |
| Peak memory | 229680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246712117 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1246712117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.3694631759 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 965298107 ps |
| CPU time | 30.42 seconds |
| Started | Oct 09 10:57:37 PM UTC 24 |
| Finished | Oct 09 10:58:09 PM UTC 24 |
| Peak memory | 230268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694631759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jt ag_errors.3694631759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3374729358 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 541840655 ps |
| CPU time | 14.22 seconds |
| Started | Oct 09 10:57:37 PM UTC 24 |
| Finished | Oct 09 10:57:53 PM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374729358 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_prior ity.3374729358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.1730002695 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 203240995 ps |
| CPU time | 4.53 seconds |
| Started | Oct 09 10:57:36 PM UTC 24 |
| Finished | Oct 09 10:57:42 PM UTC 24 |
| Peak memory | 236412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730002695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl _jtag_prog_failure.1730002695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1885015 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 825409567 ps |
| CPU time | 13.57 seconds |
| Started | Oct 09 10:57:37 PM UTC 24 |
| Finished | Oct 09 10:57:53 PM UTC 24 |
| Peak memory | 230056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885015 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr l_jtag_regwen_during_op.1885015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.3295157879 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 394895352 ps |
| CPU time | 2.93 seconds |
| Started | Oct 09 10:57:36 PM UTC 24 |
| Finished | Oct 09 10:57:40 PM UTC 24 |
| Peak memory | 230056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295157879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_s moke.3295157879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.3681259887 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2020319562 ps |
| CPU time | 30.25 seconds |
| Started | Oct 09 10:57:36 PM UTC 24 |
| Finished | Oct 09 10:58:08 PM UTC 24 |
| Peak memory | 261080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681259887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr l_jtag_state_failure.3681259887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3459407284 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1330936822 ps |
| CPU time | 16.16 seconds |
| Started | Oct 09 10:57:36 PM UTC 24 |
| Finished | Oct 09 10:57:54 PM UTC 24 |
| Peak memory | 258960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459407284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ ctrl_jtag_state_post_trans.3459407284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.2843954805 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 51022079 ps |
| CPU time | 3.38 seconds |
| Started | Oct 09 10:57:35 PM UTC 24 |
| Finished | Oct 09 10:57:40 PM UTC 24 |
| Peak memory | 234708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843954805 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2843954805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.967949504 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 504404610 ps |
| CPU time | 10.09 seconds |
| Started | Oct 09 10:57:35 PM UTC 24 |
| Finished | Oct 09 10:57:47 PM UTC 24 |
| Peak memory | 230116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967949504 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.967949504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.223925308 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 224253875 ps |
| CPU time | 10.48 seconds |
| Started | Oct 09 10:57:37 PM UTC 24 |
| Finished | Oct 09 10:57:49 PM UTC 24 |
| Peak memory | 232400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223925308 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.223925308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.3663045916 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 883399289 ps |
| CPU time | 11.02 seconds |
| Started | Oct 09 10:57:37 PM UTC 24 |
| Finished | Oct 09 10:57:50 PM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663045916 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_tok en_digest.3663045916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.401939389 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1036916990 ps |
| CPU time | 9.69 seconds |
| Started | Oct 09 10:57:37 PM UTC 24 |
| Finished | Oct 09 10:57:49 PM UTC 24 |
| Peak memory | 238052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401939389 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.401939389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.2208331810 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 335382014 ps |
| CPU time | 15.62 seconds |
| Started | Oct 09 10:57:35 PM UTC 24 |
| Finished | Oct 09 10:57:53 PM UTC 24 |
| Peak memory | 230276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208331810 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2208331810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.1937624582 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 177860201 ps |
| CPU time | 4.99 seconds |
| Started | Oct 09 10:57:32 PM UTC 24 |
| Finished | Oct 09 10:57:39 PM UTC 24 |
| Peak memory | 229928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937624582 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1937624582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.1316936173 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 204916228 ps |
| CPU time | 23.54 seconds |
| Started | Oct 09 10:57:32 PM UTC 24 |
| Finished | Oct 09 10:57:57 PM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316936173 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1316936173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.3108910901 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 189687928 ps |
| CPU time | 6.43 seconds |
| Started | Oct 09 10:57:33 PM UTC 24 |
| Finished | Oct 09 10:57:41 PM UTC 24 |
| Peak memory | 261228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108910901 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3108910901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.3947240591 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 17157970006 ps |
| CPU time | 309 seconds |
| Started | Oct 09 10:57:39 PM UTC 24 |
| Finished | Oct 09 11:02:53 PM UTC 24 |
| Peak memory | 273700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3947240591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 8.lc_ctrl_stress_all.3947240591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1663990585 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 3227886953 ps |
| CPU time | 51.92 seconds |
| Started | Oct 09 10:57:39 PM UTC 24 |
| Finished | Oct 09 10:58:33 PM UTC 24 |
| Peak memory | 263356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_r and_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663990585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_u nlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.1663990585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1443455104 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 19010371 ps |
| CPU time | 0.98 seconds |
| Started | Oct 09 10:57:32 PM UTC 24 |
| Finished | Oct 09 10:57:35 PM UTC 24 |
| Peak memory | 217780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443455104 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8. lc_ctrl_volatile_unlock_smoke.1443455104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.646656565 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 57813016 ps |
| CPU time | 1.4 seconds |
| Started | Oct 09 10:57:50 PM UTC 24 |
| Finished | Oct 09 10:57:53 PM UTC 24 |
| Peak memory | 218788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646656565 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.646656565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.3214232943 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1441818688 ps |
| CPU time | 10.49 seconds |
| Started | Oct 09 10:57:42 PM UTC 24 |
| Finished | Oct 09 10:57:53 PM UTC 24 |
| Peak memory | 230676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214232943 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3214232943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.1550863263 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 916619197 ps |
| CPU time | 22.3 seconds |
| Started | Oct 09 10:57:47 PM UTC 24 |
| Finished | Oct 09 10:58:10 PM UTC 24 |
| Peak memory | 229436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550863263 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1550863263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.2945779072 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 9076002984 ps |
| CPU time | 59.56 seconds |
| Started | Oct 09 10:57:45 PM UTC 24 |
| Finished | Oct 09 10:58:47 PM UTC 24 |
| Peak memory | 238412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945779072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jt ag_errors.2945779072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.2078293375 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 3908014136 ps |
| CPU time | 11.63 seconds |
| Started | Oct 09 10:57:47 PM UTC 24 |
| Finished | Oct 09 10:57:59 PM UTC 24 |
| Peak memory | 230052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078293375 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_prior ity.2078293375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.1529647482 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 954902428 ps |
| CPU time | 5.68 seconds |
| Started | Oct 09 10:57:44 PM UTC 24 |
| Finished | Oct 09 10:57:51 PM UTC 24 |
| Peak memory | 236488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529647482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl _jtag_prog_failure.1529647482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2338146035 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 922243005 ps |
| CPU time | 17.58 seconds |
| Started | Oct 09 10:57:48 PM UTC 24 |
| Finished | Oct 09 10:58:07 PM UTC 24 |
| Peak memory | 224264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338146035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ ctrl_jtag_regwen_during_op.2338146035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.3002045903 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 2350381084 ps |
| CPU time | 2.73 seconds |
| Started | Oct 09 10:57:43 PM UTC 24 |
| Finished | Oct 09 10:57:47 PM UTC 24 |
| Peak memory | 230260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002045903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_s moke.3002045903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.862708854 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 3528302906 ps |
| CPU time | 46.63 seconds |
| Started | Oct 09 10:57:44 PM UTC 24 |
| Finished | Oct 09 10:58:32 PM UTC 24 |
| Peak memory | 289956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862708854 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl _jtag_state_failure.862708854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.54025869 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1133078919 ps |
| CPU time | 17.76 seconds |
| Started | Oct 09 10:57:44 PM UTC 24 |
| Finished | Oct 09 10:58:03 PM UTC 24 |
| Peak memory | 262920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54025869 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct rl_jtag_state_post_trans.54025869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.3434661023 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 186737416 ps |
| CPU time | 3.55 seconds |
| Started | Oct 09 10:57:41 PM UTC 24 |
| Finished | Oct 09 10:57:46 PM UTC 24 |
| Peak memory | 230344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434661023 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.3434661023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.956391776 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 791834601 ps |
| CPU time | 17.38 seconds |
| Started | Oct 09 10:57:43 PM UTC 24 |
| Finished | Oct 09 10:58:01 PM UTC 24 |
| Peak memory | 230192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956391776 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.956391776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3294115055 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 757733601 ps |
| CPU time | 10.89 seconds |
| Started | Oct 09 10:57:48 PM UTC 24 |
| Finished | Oct 09 10:58:00 PM UTC 24 |
| Peak memory | 238016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294115055 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3294115055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.3863652695 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3200481542 ps |
| CPU time | 7.6 seconds |
| Started | Oct 09 10:57:49 PM UTC 24 |
| Finished | Oct 09 10:57:58 PM UTC 24 |
| Peak memory | 230456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863652695 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_tok en_digest.3863652695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.3895056983 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 376578668 ps |
| CPU time | 6.77 seconds |
| Started | Oct 09 10:57:49 PM UTC 24 |
| Finished | Oct 09 10:57:57 PM UTC 24 |
| Peak memory | 236660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895056983 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_ mux.3895056983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.1581528887 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1286588064 ps |
| CPU time | 11.71 seconds |
| Started | Oct 09 10:57:43 PM UTC 24 |
| Finished | Oct 09 10:57:56 PM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581528887 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1581528887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.960669763 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 122487344 ps |
| CPU time | 2.68 seconds |
| Started | Oct 09 10:57:39 PM UTC 24 |
| Finished | Oct 09 10:57:43 PM UTC 24 |
| Peak memory | 230396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960669763 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.960669763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.4281828983 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1283419714 ps |
| CPU time | 27.91 seconds |
| Started | Oct 09 10:57:40 PM UTC 24 |
| Finished | Oct 09 10:58:10 PM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281828983 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.4281828983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.792640357 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 194126999 ps |
| CPU time | 8.49 seconds |
| Started | Oct 09 10:57:40 PM UTC 24 |
| Finished | Oct 09 10:57:50 PM UTC 24 |
| Peak memory | 262944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792640357 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.792640357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3645048109 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 13900683990 ps |
| CPU time | 397.14 seconds |
| Started | Oct 09 10:57:50 PM UTC 24 |
| Finished | Oct 09 11:04:33 PM UTC 24 |
| Peak memory | 263200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000 000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3645048109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm _name 9.lc_ctrl_stress_all.3645048109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3931344394 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 14917221 ps |
| CPU time | 1.7 seconds |
| Started | Oct 09 10:57:40 PM UTC 24 |
| Finished | Oct 09 10:57:43 PM UTC 24 |
| Peak memory | 220780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931344394 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9. lc_ctrl_volatile_unlock_smoke.3931344394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/9.lc_ctrl_volatile_unlock_smoke/latest |
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