| T818 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.1344998169 |
|
|
Oct 09 11:01:48 PM UTC 24 |
Oct 09 11:01:50 PM UTC 24 |
31604464 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.444811072 |
|
|
Oct 09 11:01:28 PM UTC 24 |
Oct 09 11:01:51 PM UTC 24 |
1004409424 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.1992894008 |
|
|
Oct 09 11:01:41 PM UTC 24 |
Oct 09 11:01:51 PM UTC 24 |
863649766 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.1125788544 |
|
|
Oct 09 11:01:21 PM UTC 24 |
Oct 09 11:01:51 PM UTC 24 |
233269668 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1299514319 |
|
|
Oct 09 11:01:50 PM UTC 24 |
Oct 09 11:01:52 PM UTC 24 |
33858098 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.4237827543 |
|
|
Oct 09 11:01:40 PM UTC 24 |
Oct 09 11:01:52 PM UTC 24 |
1022792096 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.888340190 |
|
|
Oct 09 11:01:45 PM UTC 24 |
Oct 09 11:01:52 PM UTC 24 |
4066959118 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.1533074066 |
|
|
Oct 09 10:59:02 PM UTC 24 |
Oct 09 11:01:52 PM UTC 24 |
8543558988 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.1831081568 |
|
|
Oct 09 11:01:43 PM UTC 24 |
Oct 09 11:01:52 PM UTC 24 |
469089486 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.1162663916 |
|
|
Oct 09 11:01:37 PM UTC 24 |
Oct 09 11:01:54 PM UTC 24 |
341661576 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.2291017684 |
|
|
Oct 09 11:01:50 PM UTC 24 |
Oct 09 11:01:54 PM UTC 24 |
49047691 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.3498088361 |
|
|
Oct 09 11:01:37 PM UTC 24 |
Oct 09 11:01:55 PM UTC 24 |
1724253750 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.954170981 |
|
|
Oct 09 11:01:41 PM UTC 24 |
Oct 09 11:01:55 PM UTC 24 |
607901665 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.4122994485 |
|
|
Oct 09 11:01:44 PM UTC 24 |
Oct 09 11:01:55 PM UTC 24 |
459185059 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.2445365075 |
|
|
Oct 09 11:01:45 PM UTC 24 |
Oct 09 11:01:57 PM UTC 24 |
636790620 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.2921475966 |
|
|
Oct 09 11:01:47 PM UTC 24 |
Oct 09 11:01:57 PM UTC 24 |
1285599033 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.4076439219 |
|
|
Oct 09 11:01:52 PM UTC 24 |
Oct 09 11:01:58 PM UTC 24 |
1367138922 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1794800170 |
|
|
Oct 09 11:01:56 PM UTC 24 |
Oct 09 11:01:58 PM UTC 24 |
39291247 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.480463573 |
|
|
Oct 09 11:01:47 PM UTC 24 |
Oct 09 11:01:58 PM UTC 24 |
2144940488 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.952261341 |
|
|
Oct 09 11:01:56 PM UTC 24 |
Oct 09 11:01:58 PM UTC 24 |
22360334 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.2763677605 |
|
|
Oct 09 11:01:56 PM UTC 24 |
Oct 09 11:01:58 PM UTC 24 |
85918308 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.3686847917 |
|
|
Oct 09 11:01:35 PM UTC 24 |
Oct 09 11:02:00 PM UTC 24 |
191005350 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.2063694227 |
|
|
Oct 09 11:01:41 PM UTC 24 |
Oct 09 11:02:00 PM UTC 24 |
5608941463 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.1328199299 |
|
|
Oct 09 11:01:51 PM UTC 24 |
Oct 09 11:02:01 PM UTC 24 |
333607570 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.2101655320 |
|
|
Oct 09 11:01:47 PM UTC 24 |
Oct 09 11:02:01 PM UTC 24 |
654979292 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.4154731699 |
|
|
Oct 09 11:01:40 PM UTC 24 |
Oct 09 11:02:01 PM UTC 24 |
2410516393 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.1650439336 |
|
|
Oct 09 11:01:52 PM UTC 24 |
Oct 09 11:02:02 PM UTC 24 |
1629113820 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.1405799219 |
|
|
Oct 09 11:01:43 PM UTC 24 |
Oct 09 11:02:03 PM UTC 24 |
742638858 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.4017940152 |
|
|
Oct 09 11:01:58 PM UTC 24 |
Oct 09 11:02:03 PM UTC 24 |
125462044 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.44997742 |
|
|
Oct 09 11:01:52 PM UTC 24 |
Oct 09 11:02:04 PM UTC 24 |
363936120 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.3418292647 |
|
|
Oct 09 11:02:02 PM UTC 24 |
Oct 09 11:02:05 PM UTC 24 |
39378753 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.765639250 |
|
|
Oct 09 11:01:54 PM UTC 24 |
Oct 09 11:02:05 PM UTC 24 |
718642311 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.1276727808 |
|
|
Oct 09 11:01:54 PM UTC 24 |
Oct 09 11:02:05 PM UTC 24 |
1570861786 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.176176928 |
|
|
Oct 09 11:01:59 PM UTC 24 |
Oct 09 11:02:06 PM UTC 24 |
896361995 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.3005662376 |
|
|
Oct 09 11:01:54 PM UTC 24 |
Oct 09 11:02:07 PM UTC 24 |
401732454 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.2839793291 |
|
|
Oct 09 11:01:45 PM UTC 24 |
Oct 09 11:02:07 PM UTC 24 |
1539809000 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.3040361783 |
|
|
Oct 09 11:01:50 PM UTC 24 |
Oct 09 11:02:09 PM UTC 24 |
807310304 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.1869224023 |
|
|
Oct 09 11:02:00 PM UTC 24 |
Oct 09 11:02:11 PM UTC 24 |
1418645909 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.1560829986 |
|
|
Oct 09 11:01:59 PM UTC 24 |
Oct 09 11:02:12 PM UTC 24 |
272483497 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.38245018 |
|
|
Oct 09 11:02:01 PM UTC 24 |
Oct 09 11:02:12 PM UTC 24 |
1221283533 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.3198027827 |
|
|
Oct 09 11:02:00 PM UTC 24 |
Oct 09 11:02:12 PM UTC 24 |
1491590215 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.664116883 |
|
|
Oct 09 11:01:54 PM UTC 24 |
Oct 09 11:02:14 PM UTC 24 |
576703543 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.1222112615 |
|
|
Oct 09 11:01:08 PM UTC 24 |
Oct 09 11:02:17 PM UTC 24 |
3986222614 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.1755097487 |
|
|
Oct 09 11:01:57 PM UTC 24 |
Oct 09 11:02:21 PM UTC 24 |
1338198175 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.2110594341 |
|
|
Oct 09 11:01:37 PM UTC 24 |
Oct 09 11:02:24 PM UTC 24 |
2233480276 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.337959622 |
|
|
Oct 09 11:01:08 PM UTC 24 |
Oct 09 11:02:28 PM UTC 24 |
19250723074 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.2326007568 |
|
|
Oct 09 11:01:18 PM UTC 24 |
Oct 09 11:02:30 PM UTC 24 |
15554158699 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.3289031441 |
|
|
Oct 09 11:01:13 PM UTC 24 |
Oct 09 11:02:39 PM UTC 24 |
6424273005 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.1653665725 |
|
|
Oct 09 11:01:43 PM UTC 24 |
Oct 09 11:02:45 PM UTC 24 |
3182941809 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.3947240591 |
|
|
Oct 09 10:57:39 PM UTC 24 |
Oct 09 11:02:53 PM UTC 24 |
17157970006 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.3163075250 |
|
|
Oct 09 11:02:01 PM UTC 24 |
Oct 09 11:02:58 PM UTC 24 |
15281827520 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.3655635941 |
|
|
Oct 09 11:01:25 PM UTC 24 |
Oct 09 11:02:59 PM UTC 24 |
6761506835 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.3129398355 |
|
|
Oct 09 10:59:21 PM UTC 24 |
Oct 09 11:03:09 PM UTC 24 |
37577313116 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.1129239440 |
|
|
Oct 09 11:01:32 PM UTC 24 |
Oct 09 11:03:10 PM UTC 24 |
4447167271 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.1697689912 |
|
|
Oct 09 11:00:21 PM UTC 24 |
Oct 09 11:03:12 PM UTC 24 |
10640815735 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.1841276770 |
|
|
Oct 09 10:58:04 PM UTC 24 |
Oct 09 11:03:18 PM UTC 24 |
41442966545 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.3383740103 |
|
|
Oct 09 11:01:37 PM UTC 24 |
Oct 09 11:03:25 PM UTC 24 |
3867616905 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.3147269575 |
|
|
Oct 09 11:00:59 PM UTC 24 |
Oct 09 11:03:27 PM UTC 24 |
30451071123 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.178058762 |
|
|
Oct 09 11:01:41 PM UTC 24 |
Oct 09 11:04:00 PM UTC 24 |
29029156822 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2532420386 |
|
|
Oct 09 11:01:25 PM UTC 24 |
Oct 09 11:04:11 PM UTC 24 |
19763412735 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.429334002 |
|
|
Oct 09 11:00:59 PM UTC 24 |
Oct 09 11:04:17 PM UTC 24 |
25166861406 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.4141286951 |
|
|
Oct 09 11:01:33 PM UTC 24 |
Oct 09 11:04:25 PM UTC 24 |
4770154209 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.396181795 |
|
|
Oct 09 11:01:04 PM UTC 24 |
Oct 09 11:04:26 PM UTC 24 |
41771701135 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.2747094096 |
|
|
Oct 09 11:00:33 PM UTC 24 |
Oct 09 11:04:32 PM UTC 24 |
78334627643 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3645048109 |
|
|
Oct 09 10:57:50 PM UTC 24 |
Oct 09 11:04:33 PM UTC 24 |
13900683990 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.1067598183 |
|
|
Oct 09 11:01:48 PM UTC 24 |
Oct 09 11:04:34 PM UTC 24 |
34839242193 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.403820313 |
|
|
Oct 09 10:59:34 PM UTC 24 |
Oct 09 11:04:40 PM UTC 24 |
55028714701 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1625052014 |
|
|
Oct 09 11:01:56 PM UTC 24 |
Oct 09 11:04:57 PM UTC 24 |
16298356250 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.628885109 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:05:05 PM UTC 24 |
7168660032 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.3953558684 |
|
|
Oct 09 11:00:49 PM UTC 24 |
Oct 09 11:05:42 PM UTC 24 |
43674862679 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.611199200 |
|
|
Oct 09 10:59:27 PM UTC 24 |
Oct 09 11:06:19 PM UTC 24 |
82371369299 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2356918794 |
|
|
Oct 09 11:00:43 PM UTC 24 |
Oct 09 11:06:23 PM UTC 24 |
88328383282 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.3480304472 |
|
|
Oct 09 11:00:52 PM UTC 24 |
Oct 09 11:08:33 PM UTC 24 |
65652752980 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.128400865 |
|
|
Oct 09 11:01:54 PM UTC 24 |
Oct 09 11:13:51 PM UTC 24 |
23581373461 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1854060228 |
|
|
Oct 09 11:02:03 PM UTC 24 |
Oct 09 11:02:06 PM UTC 24 |
56289726 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1113312311 |
|
|
Oct 09 11:02:03 PM UTC 24 |
Oct 09 11:02:06 PM UTC 24 |
263324883 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.545052483 |
|
|
Oct 09 11:02:05 PM UTC 24 |
Oct 09 11:02:08 PM UTC 24 |
18097639 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3111544263 |
|
|
Oct 09 11:02:06 PM UTC 24 |
Oct 09 11:02:09 PM UTC 24 |
36720806 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1730141495 |
|
|
Oct 09 11:02:06 PM UTC 24 |
Oct 09 11:02:10 PM UTC 24 |
26814794 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1780359367 |
|
|
Oct 09 11:02:06 PM UTC 24 |
Oct 09 11:02:10 PM UTC 24 |
237120441 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3219315720 |
|
|
Oct 09 11:02:08 PM UTC 24 |
Oct 09 11:02:10 PM UTC 24 |
16823085 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3539733612 |
|
|
Oct 09 11:02:08 PM UTC 24 |
Oct 09 11:02:10 PM UTC 24 |
120546780 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4000622350 |
|
|
Oct 09 11:02:08 PM UTC 24 |
Oct 09 11:02:11 PM UTC 24 |
56470173 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1272629470 |
|
|
Oct 09 11:02:06 PM UTC 24 |
Oct 09 11:02:11 PM UTC 24 |
106787181 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3037018273 |
|
|
Oct 09 11:02:08 PM UTC 24 |
Oct 09 11:02:12 PM UTC 24 |
188945681 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.32378415 |
|
|
Oct 09 11:02:09 PM UTC 24 |
Oct 09 11:02:12 PM UTC 24 |
62698939 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.998362491 |
|
|
Oct 09 11:02:09 PM UTC 24 |
Oct 09 11:02:12 PM UTC 24 |
478882301 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1900757736 |
|
|
Oct 09 11:02:09 PM UTC 24 |
Oct 09 11:02:12 PM UTC 24 |
35121598 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3589382189 |
|
|
Oct 09 11:02:04 PM UTC 24 |
Oct 09 11:02:13 PM UTC 24 |
447214020 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2838045436 |
|
|
Oct 09 11:02:10 PM UTC 24 |
Oct 09 11:02:13 PM UTC 24 |
186770442 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2810198371 |
|
|
Oct 09 11:02:12 PM UTC 24 |
Oct 09 11:02:14 PM UTC 24 |
12598950 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.315914499 |
|
|
Oct 09 11:02:12 PM UTC 24 |
Oct 09 11:02:15 PM UTC 24 |
56336223 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3426238738 |
|
|
Oct 09 11:02:12 PM UTC 24 |
Oct 09 11:02:15 PM UTC 24 |
33066768 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.515303731 |
|
|
Oct 09 11:02:12 PM UTC 24 |
Oct 09 11:02:15 PM UTC 24 |
38400241 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3334468027 |
|
|
Oct 09 11:02:12 PM UTC 24 |
Oct 09 11:02:16 PM UTC 24 |
75310309 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.818779414 |
|
|
Oct 09 11:02:12 PM UTC 24 |
Oct 09 11:02:17 PM UTC 24 |
127861431 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3724229998 |
|
|
Oct 09 11:02:12 PM UTC 24 |
Oct 09 11:02:17 PM UTC 24 |
68494546 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3397233770 |
|
|
Oct 09 11:02:14 PM UTC 24 |
Oct 09 11:02:17 PM UTC 24 |
109466925 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3573875542 |
|
|
Oct 09 11:02:14 PM UTC 24 |
Oct 09 11:02:17 PM UTC 24 |
56092358 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2810733033 |
|
|
Oct 09 11:02:14 PM UTC 24 |
Oct 09 11:02:17 PM UTC 24 |
51702693 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2482983223 |
|
|
Oct 09 11:02:14 PM UTC 24 |
Oct 09 11:02:17 PM UTC 24 |
29485073 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.673454031 |
|
|
Oct 09 11:02:14 PM UTC 24 |
Oct 09 11:02:17 PM UTC 24 |
16886998 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1890052730 |
|
|
Oct 09 11:02:14 PM UTC 24 |
Oct 09 11:02:17 PM UTC 24 |
54401428 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1364797003 |
|
|
Oct 09 11:02:14 PM UTC 24 |
Oct 09 11:02:18 PM UTC 24 |
301514511 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.391265952 |
|
|
Oct 09 11:02:15 PM UTC 24 |
Oct 09 11:02:18 PM UTC 24 |
124586881 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.64012778 |
|
|
Oct 09 11:02:14 PM UTC 24 |
Oct 09 11:02:18 PM UTC 24 |
150873025 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2386513404 |
|
|
Oct 09 11:02:16 PM UTC 24 |
Oct 09 11:02:18 PM UTC 24 |
34855266 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2330234906 |
|
|
Oct 09 11:02:15 PM UTC 24 |
Oct 09 11:02:19 PM UTC 24 |
256850280 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1266271589 |
|
|
Oct 09 11:02:17 PM UTC 24 |
Oct 09 11:02:19 PM UTC 24 |
65315551 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3193979483 |
|
|
Oct 09 11:02:17 PM UTC 24 |
Oct 09 11:02:19 PM UTC 24 |
52155221 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3975030486 |
|
|
Oct 09 11:02:12 PM UTC 24 |
Oct 09 11:02:19 PM UTC 24 |
984369379 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2113731916 |
|
|
Oct 09 11:02:16 PM UTC 24 |
Oct 09 11:02:20 PM UTC 24 |
127364559 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.443487838 |
|
|
Oct 09 11:02:18 PM UTC 24 |
Oct 09 11:02:21 PM UTC 24 |
135731331 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2169361016 |
|
|
Oct 09 11:02:18 PM UTC 24 |
Oct 09 11:02:21 PM UTC 24 |
43185573 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.34527681 |
|
|
Oct 09 11:02:18 PM UTC 24 |
Oct 09 11:02:21 PM UTC 24 |
79784785 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3542380308 |
|
|
Oct 09 11:02:18 PM UTC 24 |
Oct 09 11:02:21 PM UTC 24 |
203456803 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3139230542 |
|
|
Oct 09 11:02:18 PM UTC 24 |
Oct 09 11:02:21 PM UTC 24 |
21131140 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2468612855 |
|
|
Oct 09 11:02:18 PM UTC 24 |
Oct 09 11:02:22 PM UTC 24 |
35656390 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.811643094 |
|
|
Oct 09 11:02:20 PM UTC 24 |
Oct 09 11:02:22 PM UTC 24 |
43246354 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.795073589 |
|
|
Oct 09 11:02:20 PM UTC 24 |
Oct 09 11:02:22 PM UTC 24 |
32660564 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1162749155 |
|
|
Oct 09 11:02:20 PM UTC 24 |
Oct 09 11:02:22 PM UTC 24 |
160152427 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1656790869 |
|
|
Oct 09 11:02:20 PM UTC 24 |
Oct 09 11:02:23 PM UTC 24 |
422929886 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2531088016 |
|
|
Oct 09 11:02:20 PM UTC 24 |
Oct 09 11:02:23 PM UTC 24 |
38013880 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.254189088 |
|
|
Oct 09 11:02:20 PM UTC 24 |
Oct 09 11:02:23 PM UTC 24 |
41635185 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2149881422 |
|
|
Oct 09 11:02:20 PM UTC 24 |
Oct 09 11:02:24 PM UTC 24 |
78672469 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3360883447 |
|
|
Oct 09 11:02:18 PM UTC 24 |
Oct 09 11:02:24 PM UTC 24 |
95469459 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.985824404 |
|
|
Oct 09 11:02:21 PM UTC 24 |
Oct 09 11:02:24 PM UTC 24 |
73001117 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.508140084 |
|
|
Oct 09 11:02:21 PM UTC 24 |
Oct 09 11:02:24 PM UTC 24 |
243554306 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1929034218 |
|
|
Oct 09 11:02:21 PM UTC 24 |
Oct 09 11:02:24 PM UTC 24 |
70798928 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.849319179 |
|
|
Oct 09 11:02:04 PM UTC 24 |
Oct 09 11:02:24 PM UTC 24 |
2887715057 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2308695402 |
|
|
Oct 09 11:02:27 PM UTC 24 |
Oct 09 11:02:29 PM UTC 24 |
41209176 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1696392712 |
|
|
Oct 09 11:02:21 PM UTC 24 |
Oct 09 11:02:24 PM UTC 24 |
198679176 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1919616739 |
|
|
Oct 09 11:02:22 PM UTC 24 |
Oct 09 11:02:25 PM UTC 24 |
72496299 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3828224555 |
|
|
Oct 09 11:02:18 PM UTC 24 |
Oct 09 11:02:25 PM UTC 24 |
913852919 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.354209254 |
|
|
Oct 09 11:02:14 PM UTC 24 |
Oct 09 11:02:25 PM UTC 24 |
2681803233 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4227343483 |
|
|
Oct 09 11:02:22 PM UTC 24 |
Oct 09 11:02:25 PM UTC 24 |
81160160 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.602283346 |
|
|
Oct 09 11:02:24 PM UTC 24 |
Oct 09 11:02:26 PM UTC 24 |
26408269 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1102228798 |
|
|
Oct 09 11:02:22 PM UTC 24 |
Oct 09 11:02:26 PM UTC 24 |
272040890 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2700128842 |
|
|
Oct 09 11:02:24 PM UTC 24 |
Oct 09 11:02:26 PM UTC 24 |
25444864 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4268852673 |
|
|
Oct 09 11:02:24 PM UTC 24 |
Oct 09 11:02:26 PM UTC 24 |
32988551 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4149658599 |
|
|
Oct 09 11:02:18 PM UTC 24 |
Oct 09 11:02:26 PM UTC 24 |
263270611 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1908720190 |
|
|
Oct 09 11:02:24 PM UTC 24 |
Oct 09 11:02:27 PM UTC 24 |
78132998 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2830032817 |
|
|
Oct 09 11:02:25 PM UTC 24 |
Oct 09 11:02:28 PM UTC 24 |
72676019 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2837936361 |
|
|
Oct 09 11:02:23 PM UTC 24 |
Oct 09 11:02:29 PM UTC 24 |
122687402 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.22338825 |
|
|
Oct 09 11:02:24 PM UTC 24 |
Oct 09 11:02:27 PM UTC 24 |
58178881 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3830092921 |
|
|
Oct 09 11:02:22 PM UTC 24 |
Oct 09 11:02:27 PM UTC 24 |
2024166858 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2599695672 |
|
|
Oct 09 11:02:25 PM UTC 24 |
Oct 09 11:02:28 PM UTC 24 |
39417808 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1156781882 |
|
|
Oct 09 11:02:25 PM UTC 24 |
Oct 09 11:02:28 PM UTC 24 |
28040806 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.56329778 |
|
|
Oct 09 11:02:26 PM UTC 24 |
Oct 09 11:02:29 PM UTC 24 |
428664353 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.913696595 |
|
|
Oct 09 11:02:25 PM UTC 24 |
Oct 09 11:02:29 PM UTC 24 |
1267707717 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2907779830 |
|
|
Oct 09 11:02:27 PM UTC 24 |
Oct 09 11:02:30 PM UTC 24 |
25081476 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3314146436 |
|
|
Oct 09 11:02:27 PM UTC 24 |
Oct 09 11:02:30 PM UTC 24 |
61047818 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3747225286 |
|
|
Oct 09 11:02:43 PM UTC 24 |
Oct 09 11:02:45 PM UTC 24 |
41821220 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3473170532 |
|
|
Oct 09 11:02:25 PM UTC 24 |
Oct 09 11:02:31 PM UTC 24 |
151819890 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.77551716 |
|
|
Oct 09 11:02:27 PM UTC 24 |
Oct 09 11:02:31 PM UTC 24 |
82074749 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1753746637 |
|
|
Oct 09 11:02:27 PM UTC 24 |
Oct 09 11:02:31 PM UTC 24 |
343675527 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1748312947 |
|
|
Oct 09 11:02:29 PM UTC 24 |
Oct 09 11:02:31 PM UTC 24 |
123357895 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1104851491 |
|
|
Oct 09 11:02:27 PM UTC 24 |
Oct 09 11:02:31 PM UTC 24 |
108823838 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3993732634 |
|
|
Oct 09 11:02:29 PM UTC 24 |
Oct 09 11:02:31 PM UTC 24 |
65343069 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1894735468 |
|
|
Oct 09 11:02:29 PM UTC 24 |
Oct 09 11:02:32 PM UTC 24 |
29299609 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1635361422 |
|
|
Oct 09 11:02:29 PM UTC 24 |
Oct 09 11:02:32 PM UTC 24 |
74605374 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4085524124 |
|
|
Oct 09 11:02:27 PM UTC 24 |
Oct 09 11:02:33 PM UTC 24 |
984444442 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3234661177 |
|
|
Oct 09 11:02:29 PM UTC 24 |
Oct 09 11:02:33 PM UTC 24 |
123011323 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3214712348 |
|
|
Oct 09 11:02:30 PM UTC 24 |
Oct 09 11:02:33 PM UTC 24 |
27515646 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2861936893 |
|
|
Oct 09 11:02:11 PM UTC 24 |
Oct 09 11:02:33 PM UTC 24 |
1801977749 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2840755580 |
|
|
Oct 09 11:02:30 PM UTC 24 |
Oct 09 11:02:33 PM UTC 24 |
130307665 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1827493097 |
|
|
Oct 09 11:02:29 PM UTC 24 |
Oct 09 11:02:33 PM UTC 24 |
104007128 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1339904699 |
|
|
Oct 09 11:02:25 PM UTC 24 |
Oct 09 11:02:34 PM UTC 24 |
539213920 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.958365120 |
|
|
Oct 09 11:02:29 PM UTC 24 |
Oct 09 11:02:35 PM UTC 24 |
417050729 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1908063098 |
|
|
Oct 09 11:02:32 PM UTC 24 |
Oct 09 11:02:35 PM UTC 24 |
103594096 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3496036090 |
|
|
Oct 09 11:02:32 PM UTC 24 |
Oct 09 11:02:35 PM UTC 24 |
48226086 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.4055906741 |
|
|
Oct 09 11:02:30 PM UTC 24 |
Oct 09 11:02:35 PM UTC 24 |
245970876 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2216495139 |
|
|
Oct 09 11:02:32 PM UTC 24 |
Oct 09 11:02:35 PM UTC 24 |
300428884 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.956680910 |
|
|
Oct 09 11:02:32 PM UTC 24 |
Oct 09 11:02:35 PM UTC 24 |
48870254 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4031325378 |
|
|
Oct 09 11:02:32 PM UTC 24 |
Oct 09 11:02:35 PM UTC 24 |
38884890 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3327346671 |
|
|
Oct 09 11:02:32 PM UTC 24 |
Oct 09 11:02:35 PM UTC 24 |
829690600 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1429711529 |
|
|
Oct 09 11:02:22 PM UTC 24 |
Oct 09 11:02:36 PM UTC 24 |
495114452 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3874279415 |
|
|
Oct 09 11:02:32 PM UTC 24 |
Oct 09 11:02:36 PM UTC 24 |
170523649 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2554018279 |
|
|
Oct 09 11:02:25 PM UTC 24 |
Oct 09 11:02:36 PM UTC 24 |
2751236300 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1657071144 |
|
|
Oct 09 11:02:34 PM UTC 24 |
Oct 09 11:02:36 PM UTC 24 |
85422498 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.870378736 |
|
|
Oct 09 11:02:32 PM UTC 24 |
Oct 09 11:02:36 PM UTC 24 |
1102737260 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.80285212 |
|
|
Oct 09 11:02:34 PM UTC 24 |
Oct 09 11:02:37 PM UTC 24 |
47511199 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1110916713 |
|
|
Oct 09 11:02:34 PM UTC 24 |
Oct 09 11:02:37 PM UTC 24 |
79839384 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.402756716 |
|
|
Oct 09 11:02:34 PM UTC 24 |
Oct 09 11:02:37 PM UTC 24 |
238370750 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2300784472 |
|
|
Oct 09 11:02:34 PM UTC 24 |
Oct 09 11:02:38 PM UTC 24 |
81303016 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3946016476 |
|
|
Oct 09 11:02:34 PM UTC 24 |
Oct 09 11:02:38 PM UTC 24 |
431156436 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3804678393 |
|
|
Oct 09 11:02:34 PM UTC 24 |
Oct 09 11:02:38 PM UTC 24 |
29139236 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1347915115 |
|
|
Oct 09 11:02:30 PM UTC 24 |
Oct 09 11:02:38 PM UTC 24 |
423178500 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3064042640 |
|
|
Oct 09 11:02:35 PM UTC 24 |
Oct 09 11:02:38 PM UTC 24 |
20266586 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2384139154 |
|
|
Oct 09 11:02:35 PM UTC 24 |
Oct 09 11:02:38 PM UTC 24 |
16016827 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1629047624 |
|
|
Oct 09 11:02:36 PM UTC 24 |
Oct 09 11:02:38 PM UTC 24 |
24541790 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3457777017 |
|
|
Oct 09 11:02:36 PM UTC 24 |
Oct 09 11:02:38 PM UTC 24 |
56791397 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3696143536 |
|
|
Oct 09 11:02:34 PM UTC 24 |
Oct 09 11:02:38 PM UTC 24 |
353526551 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1375304618 |
|
|
Oct 09 11:02:36 PM UTC 24 |
Oct 09 11:02:39 PM UTC 24 |
254670263 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2679341418 |
|
|
Oct 09 11:02:36 PM UTC 24 |
Oct 09 11:02:39 PM UTC 24 |
1172217203 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1162157143 |
|
|
Oct 09 11:02:37 PM UTC 24 |
Oct 09 11:02:40 PM UTC 24 |
16770727 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2508519673 |
|
|
Oct 09 11:02:34 PM UTC 24 |
Oct 09 11:02:40 PM UTC 24 |
263175473 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3193866921 |
|
|
Oct 09 11:02:37 PM UTC 24 |
Oct 09 11:02:40 PM UTC 24 |
23242419 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.741299429 |
|
|
Oct 09 11:02:37 PM UTC 24 |
Oct 09 11:02:41 PM UTC 24 |
148374716 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1263068242 |
|
|
Oct 09 11:02:37 PM UTC 24 |
Oct 09 11:02:41 PM UTC 24 |
86647836 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3743041429 |
|
|
Oct 09 11:02:37 PM UTC 24 |
Oct 09 11:02:41 PM UTC 24 |
32152522 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.877499476 |
|
|
Oct 09 11:02:37 PM UTC 24 |
Oct 09 11:02:41 PM UTC 24 |
123843267 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3731382287 |
|
|
Oct 09 11:02:37 PM UTC 24 |
Oct 09 11:02:41 PM UTC 24 |
78358766 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3339820191 |
|
|
Oct 09 11:02:39 PM UTC 24 |
Oct 09 11:02:41 PM UTC 24 |
17221433 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1788134475 |
|
|
Oct 09 11:02:29 PM UTC 24 |
Oct 09 11:02:41 PM UTC 24 |
2902609289 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2192593942 |
|
|
Oct 09 11:02:39 PM UTC 24 |
Oct 09 11:02:41 PM UTC 24 |
14962114 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3942678421 |
|
|
Oct 09 11:02:39 PM UTC 24 |
Oct 09 11:02:42 PM UTC 24 |
156353944 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2908563877 |
|
|
Oct 09 11:02:39 PM UTC 24 |
Oct 09 11:02:42 PM UTC 24 |
72878144 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3872423716 |
|
|
Oct 09 11:02:39 PM UTC 24 |
Oct 09 11:02:42 PM UTC 24 |
36653194 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.503061583 |
|
|
Oct 09 11:02:39 PM UTC 24 |
Oct 09 11:02:42 PM UTC 24 |
140362758 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.931602614 |
|
|
Oct 09 11:02:36 PM UTC 24 |
Oct 09 11:02:43 PM UTC 24 |
514589491 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.885937806 |
|
|
Oct 09 11:02:37 PM UTC 24 |
Oct 09 11:02:43 PM UTC 24 |
139840340 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3352849019 |
|
|
Oct 09 11:02:39 PM UTC 24 |
Oct 09 11:02:43 PM UTC 24 |
785082954 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2003480764 |
|
|
Oct 09 11:02:41 PM UTC 24 |
Oct 09 11:02:43 PM UTC 24 |
23966712 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2520593918 |
|
|
Oct 09 11:02:25 PM UTC 24 |
Oct 09 11:02:43 PM UTC 24 |
2550919265 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3220185495 |
|
|
Oct 09 11:02:14 PM UTC 24 |
Oct 09 11:02:43 PM UTC 24 |
4924658511 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3989727639 |
|
|
Oct 09 11:02:39 PM UTC 24 |
Oct 09 11:02:43 PM UTC 24 |
69382038 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1517667744 |
|
|
Oct 09 11:02:41 PM UTC 24 |
Oct 09 11:02:43 PM UTC 24 |
15887741 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.4076306653 |
|
|
Oct 09 11:02:41 PM UTC 24 |
Oct 09 11:02:44 PM UTC 24 |
153763537 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4250149796 |
|
|
Oct 09 11:02:41 PM UTC 24 |
Oct 09 11:02:44 PM UTC 24 |
44088592 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2832653042 |
|
|
Oct 09 11:02:41 PM UTC 24 |
Oct 09 11:02:44 PM UTC 24 |
30127855 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2383582959 |
|
|
Oct 09 11:02:41 PM UTC 24 |
Oct 09 11:02:44 PM UTC 24 |
36776255 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2599480980 |
|
|
Oct 09 11:02:43 PM UTC 24 |
Oct 09 11:02:45 PM UTC 24 |
14482518 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3635789201 |
|
|
Oct 09 11:02:27 PM UTC 24 |
Oct 09 11:02:45 PM UTC 24 |
765420978 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.655794595 |
|
|
Oct 09 11:02:43 PM UTC 24 |
Oct 09 11:02:45 PM UTC 24 |
25781480 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1115045900 |
|
|
Oct 09 11:02:45 PM UTC 24 |
Oct 09 11:02:47 PM UTC 24 |
19787436 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2223943464 |
|
|
Oct 09 11:02:43 PM UTC 24 |
Oct 09 11:02:45 PM UTC 24 |
129013395 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1692285796 |
|
|
Oct 09 11:02:43 PM UTC 24 |
Oct 09 11:02:45 PM UTC 24 |
21424522 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3009772822 |
|
|
Oct 09 11:02:43 PM UTC 24 |
Oct 09 11:02:45 PM UTC 24 |
94526004 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2982908751 |
|
|
Oct 09 11:02:41 PM UTC 24 |
Oct 09 11:02:46 PM UTC 24 |
43303344 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2849603658 |
|
|
Oct 09 11:02:43 PM UTC 24 |
Oct 09 11:02:46 PM UTC 24 |
78285510 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.389210459 |
|
|
Oct 09 11:02:43 PM UTC 24 |
Oct 09 11:02:46 PM UTC 24 |
63087093 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3294230275 |
|
|
Oct 09 11:02:43 PM UTC 24 |
Oct 09 11:02:46 PM UTC 24 |
140135214 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.649722967 |
|
|
Oct 09 11:02:41 PM UTC 24 |
Oct 09 11:02:46 PM UTC 24 |
396943494 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2912862115 |
|
|
Oct 09 11:02:43 PM UTC 24 |
Oct 09 11:02:46 PM UTC 24 |
57763188 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4241763992 |
|
|
Oct 09 11:02:43 PM UTC 24 |
Oct 09 11:02:47 PM UTC 24 |
69680921 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3985860192 |
|
|
Oct 09 11:02:45 PM UTC 24 |
Oct 09 11:02:47 PM UTC 24 |
24700406 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4265580071 |
|
|
Oct 09 11:02:45 PM UTC 24 |
Oct 09 11:02:47 PM UTC 24 |
26169341 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.19212831 |
|
|
Oct 09 11:02:45 PM UTC 24 |
Oct 09 11:02:48 PM UTC 24 |
123192795 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2528548014 |
|
|
Oct 09 11:02:45 PM UTC 24 |
Oct 09 11:02:48 PM UTC 24 |
23429705 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1005506680 |
|
|
Oct 09 11:02:45 PM UTC 24 |
Oct 09 11:02:48 PM UTC 24 |
412286113 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2321935979 |
|
|
Oct 09 11:02:45 PM UTC 24 |
Oct 09 11:02:48 PM UTC 24 |
17605758 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2951319189 |
|
|
Oct 09 11:02:43 PM UTC 24 |
Oct 09 11:02:48 PM UTC 24 |
136137398 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1313140256 |
|
|
Oct 09 11:02:45 PM UTC 24 |
Oct 09 11:02:48 PM UTC 24 |
141015459 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3873604127 |
|
|
Oct 09 11:02:45 PM UTC 24 |
Oct 09 11:02:48 PM UTC 24 |
31952068 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.306061917 |
|
|
Oct 09 11:02:45 PM UTC 24 |
Oct 09 11:02:48 PM UTC 24 |
65229505 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4080782332 |
|
|
Oct 09 11:02:45 PM UTC 24 |
Oct 09 11:02:49 PM UTC 24 |
55621350 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2126480423 |
|
|
Oct 09 11:02:36 PM UTC 24 |
Oct 09 11:02:49 PM UTC 24 |
2456284204 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3906820937 |
|
|
Oct 09 11:02:47 PM UTC 24 |
Oct 09 11:02:49 PM UTC 24 |
29454535 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3180998594 |
|
|
Oct 09 11:02:47 PM UTC 24 |
Oct 09 11:02:50 PM UTC 24 |
60824590 ps |