| T590 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2412599452 |
|
|
Oct 09 11:00:00 PM UTC 24 |
Oct 09 11:00:11 PM UTC 24 |
11316517 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.3948646569 |
|
|
Oct 09 11:00:30 PM UTC 24 |
Oct 09 11:00:32 PM UTC 24 |
63582553 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3970938270 |
|
|
Oct 09 10:59:11 PM UTC 24 |
Oct 09 11:00:11 PM UTC 24 |
4311881660 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.3395325119 |
|
|
Oct 09 10:59:39 PM UTC 24 |
Oct 09 11:00:11 PM UTC 24 |
511495523 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.22486138 |
|
|
Oct 09 11:00:30 PM UTC 24 |
Oct 09 11:00:32 PM UTC 24 |
13368041 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.80323262 |
|
|
Oct 09 11:00:00 PM UTC 24 |
Oct 09 11:00:13 PM UTC 24 |
242257975 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.1894426229 |
|
|
Oct 09 11:00:00 PM UTC 24 |
Oct 09 11:00:14 PM UTC 24 |
379074090 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.1976590494 |
|
|
Oct 09 10:59:57 PM UTC 24 |
Oct 09 11:00:14 PM UTC 24 |
2064413161 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.2921990158 |
|
|
Oct 09 11:00:21 PM UTC 24 |
Oct 09 11:00:31 PM UTC 24 |
256323036 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1161938805 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:14 PM UTC 24 |
63692275 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.1022038229 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:14 PM UTC 24 |
15884481 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.2517595772 |
|
|
Oct 09 10:59:50 PM UTC 24 |
Oct 09 11:00:15 PM UTC 24 |
1006946789 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.4181974872 |
|
|
Oct 09 11:00:13 PM UTC 24 |
Oct 09 11:00:15 PM UTC 24 |
55739573 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.1513808605 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:16 PM UTC 24 |
18806088 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.2557281472 |
|
|
Oct 09 11:00:02 PM UTC 24 |
Oct 09 11:00:16 PM UTC 24 |
1086322545 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.3974137041 |
|
|
Oct 09 10:59:46 PM UTC 24 |
Oct 09 11:00:16 PM UTC 24 |
524151035 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3238933608 |
|
|
Oct 09 11:00:14 PM UTC 24 |
Oct 09 11:00:17 PM UTC 24 |
17863892 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.4173575914 |
|
|
Oct 09 11:00:14 PM UTC 24 |
Oct 09 11:00:17 PM UTC 24 |
28666793 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.1339120966 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:32 PM UTC 24 |
2771968462 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.1069244962 |
|
|
Oct 09 11:00:14 PM UTC 24 |
Oct 09 11:00:17 PM UTC 24 |
23236243 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.2753912692 |
|
|
Oct 09 11:00:01 PM UTC 24 |
Oct 09 11:00:18 PM UTC 24 |
795596583 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.991860322 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:19 PM UTC 24 |
293825665 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.3774364684 |
|
|
Oct 09 11:00:02 PM UTC 24 |
Oct 09 11:00:19 PM UTC 24 |
2063683560 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.3385404643 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:19 PM UTC 24 |
1406612100 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.1279260307 |
|
|
Oct 09 10:59:52 PM UTC 24 |
Oct 09 11:00:20 PM UTC 24 |
714756993 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.2688193766 |
|
|
Oct 09 11:00:17 PM UTC 24 |
Oct 09 11:00:20 PM UTC 24 |
34074177 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.2327804993 |
|
|
Oct 09 11:00:14 PM UTC 24 |
Oct 09 11:00:20 PM UTC 24 |
72646704 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.2616236517 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:21 PM UTC 24 |
193546589 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.735992009 |
|
|
Oct 09 11:00:18 PM UTC 24 |
Oct 09 11:00:21 PM UTC 24 |
36366360 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.2478337235 |
|
|
Oct 09 11:00:17 PM UTC 24 |
Oct 09 11:00:22 PM UTC 24 |
90610018 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.1602891601 |
|
|
Oct 09 11:00:16 PM UTC 24 |
Oct 09 11:00:22 PM UTC 24 |
576139967 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.277135500 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:23 PM UTC 24 |
1030658921 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.1690375770 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:23 PM UTC 24 |
334338406 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.2183916101 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:24 PM UTC 24 |
290030080 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.497420642 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:24 PM UTC 24 |
239697186 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.1005096095 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:24 PM UTC 24 |
887961411 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.661863400 |
|
|
Oct 09 11:00:20 PM UTC 24 |
Oct 09 11:00:25 PM UTC 24 |
485302148 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.3298482758 |
|
|
Oct 09 11:00:20 PM UTC 24 |
Oct 09 11:00:32 PM UTC 24 |
489029409 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.4147305370 |
|
|
Oct 09 11:00:23 PM UTC 24 |
Oct 09 11:00:25 PM UTC 24 |
69313631 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.1793628991 |
|
|
Oct 09 10:59:45 PM UTC 24 |
Oct 09 11:00:25 PM UTC 24 |
1462359093 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2176092071 |
|
|
Oct 09 11:00:24 PM UTC 24 |
Oct 09 11:00:27 PM UTC 24 |
14958004 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.3277936147 |
|
|
Oct 09 11:00:19 PM UTC 24 |
Oct 09 11:00:27 PM UTC 24 |
100946205 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.1227398333 |
|
|
Oct 09 11:00:16 PM UTC 24 |
Oct 09 11:00:28 PM UTC 24 |
1054628817 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_errors.3143792735 |
|
|
Oct 09 11:00:14 PM UTC 24 |
Oct 09 11:00:28 PM UTC 24 |
959836367 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.4091780863 |
|
|
Oct 09 10:59:50 PM UTC 24 |
Oct 09 11:00:28 PM UTC 24 |
1270977827 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.1524775111 |
|
|
Oct 09 11:00:26 PM UTC 24 |
Oct 09 11:00:28 PM UTC 24 |
60467675 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.936228406 |
|
|
Oct 09 11:00:24 PM UTC 24 |
Oct 09 11:00:28 PM UTC 24 |
129844032 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.820279126 |
|
|
Oct 09 11:00:25 PM UTC 24 |
Oct 09 11:00:29 PM UTC 24 |
47090161 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.1973221401 |
|
|
Oct 09 11:00:21 PM UTC 24 |
Oct 09 11:00:30 PM UTC 24 |
195822913 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.2475839744 |
|
|
Oct 09 11:00:16 PM UTC 24 |
Oct 09 11:00:30 PM UTC 24 |
1957324694 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.2617632470 |
|
|
Oct 09 11:00:16 PM UTC 24 |
Oct 09 11:00:30 PM UTC 24 |
338998114 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.2014000894 |
|
|
Oct 09 11:00:21 PM UTC 24 |
Oct 09 11:00:30 PM UTC 24 |
187330976 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.615792252 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:31 PM UTC 24 |
852805020 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.73616403 |
|
|
Oct 09 10:59:45 PM UTC 24 |
Oct 09 11:00:33 PM UTC 24 |
1545248022 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.1189253700 |
|
|
Oct 09 11:00:26 PM UTC 24 |
Oct 09 11:00:33 PM UTC 24 |
1043610949 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.1863404638 |
|
|
Oct 09 11:00:21 PM UTC 24 |
Oct 09 11:00:33 PM UTC 24 |
644804613 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.3512620771 |
|
|
Oct 09 10:59:05 PM UTC 24 |
Oct 09 11:00:34 PM UTC 24 |
2955585999 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.3795987313 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:34 PM UTC 24 |
2318893525 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.2186360226 |
|
|
Oct 09 11:00:30 PM UTC 24 |
Oct 09 11:00:35 PM UTC 24 |
82724827 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.3652313599 |
|
|
Oct 09 11:00:16 PM UTC 24 |
Oct 09 11:00:35 PM UTC 24 |
416379288 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.672733618 |
|
|
Oct 09 10:59:16 PM UTC 24 |
Oct 09 11:00:35 PM UTC 24 |
11841360916 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.680886158 |
|
|
Oct 09 11:00:27 PM UTC 24 |
Oct 09 11:00:35 PM UTC 24 |
231238257 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.2215990659 |
|
|
Oct 09 11:00:32 PM UTC 24 |
Oct 09 11:00:36 PM UTC 24 |
269923678 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.2280025922 |
|
|
Oct 09 10:58:43 PM UTC 24 |
Oct 09 11:00:36 PM UTC 24 |
11061049575 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.868965491 |
|
|
Oct 09 11:00:33 PM UTC 24 |
Oct 09 11:00:36 PM UTC 24 |
22549107 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.1934788182 |
|
|
Oct 09 11:00:31 PM UTC 24 |
Oct 09 11:00:36 PM UTC 24 |
206546713 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.2473695374 |
|
|
Oct 09 11:00:25 PM UTC 24 |
Oct 09 11:00:36 PM UTC 24 |
174780126 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.4042443900 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:37 PM UTC 24 |
257181718 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.2150053602 |
|
|
Oct 09 11:00:27 PM UTC 24 |
Oct 09 11:00:37 PM UTC 24 |
297447603 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.1734391718 |
|
|
Oct 09 11:00:33 PM UTC 24 |
Oct 09 11:00:38 PM UTC 24 |
132730738 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2251870894 |
|
|
Oct 09 11:00:35 PM UTC 24 |
Oct 09 11:00:38 PM UTC 24 |
22880798 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.3642608087 |
|
|
Oct 09 11:00:12 PM UTC 24 |
Oct 09 11:00:38 PM UTC 24 |
1647643329 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.1785688351 |
|
|
Oct 09 11:00:30 PM UTC 24 |
Oct 09 11:00:38 PM UTC 24 |
347509615 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.3333259832 |
|
|
Oct 09 10:58:28 PM UTC 24 |
Oct 09 11:01:01 PM UTC 24 |
31542106659 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_errors.805683801 |
|
|
Oct 09 11:00:26 PM UTC 24 |
Oct 09 11:00:39 PM UTC 24 |
1146571573 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.3639094825 |
|
|
Oct 09 11:00:37 PM UTC 24 |
Oct 09 11:00:40 PM UTC 24 |
16964372 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.255558947 |
|
|
Oct 09 11:00:56 PM UTC 24 |
Oct 09 11:01:00 PM UTC 24 |
69381559 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.2916538027 |
|
|
Oct 09 11:00:35 PM UTC 24 |
Oct 09 11:00:41 PM UTC 24 |
97184641 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1741893065 |
|
|
Oct 09 11:00:39 PM UTC 24 |
Oct 09 11:00:41 PM UTC 24 |
11942033 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.3838912789 |
|
|
Oct 09 11:00:32 PM UTC 24 |
Oct 09 11:00:42 PM UTC 24 |
612516627 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.411628039 |
|
|
Oct 09 11:00:39 PM UTC 24 |
Oct 09 11:00:43 PM UTC 24 |
41068405 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.2190040494 |
|
|
Oct 09 11:00:18 PM UTC 24 |
Oct 09 11:00:43 PM UTC 24 |
2677980298 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.4185158158 |
|
|
Oct 09 11:00:32 PM UTC 24 |
Oct 09 11:00:44 PM UTC 24 |
968730442 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.1326168532 |
|
|
Oct 09 11:00:33 PM UTC 24 |
Oct 09 11:00:44 PM UTC 24 |
538791920 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.326696903 |
|
|
Oct 09 11:00:37 PM UTC 24 |
Oct 09 11:00:44 PM UTC 24 |
272380114 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.2200302008 |
|
|
Oct 09 11:00:33 PM UTC 24 |
Oct 09 11:00:45 PM UTC 24 |
326420427 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.527494290 |
|
|
Oct 09 11:00:35 PM UTC 24 |
Oct 09 11:00:45 PM UTC 24 |
1233495005 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.1070776588 |
|
|
Oct 09 11:00:14 PM UTC 24 |
Oct 09 11:00:45 PM UTC 24 |
1432778996 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.977117856 |
|
|
Oct 09 11:00:27 PM UTC 24 |
Oct 09 11:00:45 PM UTC 24 |
431131774 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.549101329 |
|
|
Oct 09 11:00:39 PM UTC 24 |
Oct 09 11:00:46 PM UTC 24 |
404209097 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.1889990784 |
|
|
Oct 09 11:00:44 PM UTC 24 |
Oct 09 11:00:47 PM UTC 24 |
17451651 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.2427816623 |
|
|
Oct 09 11:00:44 PM UTC 24 |
Oct 09 11:00:47 PM UTC 24 |
18719956 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.3289045133 |
|
|
Oct 09 11:00:32 PM UTC 24 |
Oct 09 11:00:48 PM UTC 24 |
523916075 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3119875097 |
|
|
Oct 09 11:00:45 PM UTC 24 |
Oct 09 11:00:48 PM UTC 24 |
25300031 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.2123325565 |
|
|
Oct 09 11:00:35 PM UTC 24 |
Oct 09 11:00:48 PM UTC 24 |
186752742 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.3920107453 |
|
|
Oct 09 11:00:35 PM UTC 24 |
Oct 09 11:00:48 PM UTC 24 |
337723713 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.309197018 |
|
|
Oct 09 11:00:00 PM UTC 24 |
Oct 09 11:00:48 PM UTC 24 |
368768480 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.2521713392 |
|
|
Oct 09 11:00:39 PM UTC 24 |
Oct 09 11:00:49 PM UTC 24 |
673016500 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.3018972501 |
|
|
Oct 09 11:00:46 PM UTC 24 |
Oct 09 11:00:49 PM UTC 24 |
37469518 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2881885356 |
|
|
Oct 09 10:59:52 PM UTC 24 |
Oct 09 11:00:49 PM UTC 24 |
7139126086 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.3511172081 |
|
|
Oct 09 11:00:40 PM UTC 24 |
Oct 09 11:00:50 PM UTC 24 |
12273707497 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.1956427156 |
|
|
Oct 09 11:00:24 PM UTC 24 |
Oct 09 11:00:50 PM UTC 24 |
152241488 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.891057322 |
|
|
Oct 09 11:00:47 PM UTC 24 |
Oct 09 11:01:00 PM UTC 24 |
369609840 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.4036715913 |
|
|
Oct 09 11:00:22 PM UTC 24 |
Oct 09 11:00:50 PM UTC 24 |
15883693474 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.3709815396 |
|
|
Oct 09 11:00:39 PM UTC 24 |
Oct 09 11:00:50 PM UTC 24 |
618902885 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.394502833 |
|
|
Oct 09 11:00:39 PM UTC 24 |
Oct 09 11:00:50 PM UTC 24 |
1189909054 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.1594730965 |
|
|
Oct 09 11:00:47 PM UTC 24 |
Oct 09 11:00:51 PM UTC 24 |
444864514 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3375282296 |
|
|
Oct 09 11:00:33 PM UTC 24 |
Oct 09 11:00:52 PM UTC 24 |
846993917 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1082644934 |
|
|
Oct 09 11:00:50 PM UTC 24 |
Oct 09 11:00:52 PM UTC 24 |
11403848 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.1796691579 |
|
|
Oct 09 11:00:50 PM UTC 24 |
Oct 09 11:00:52 PM UTC 24 |
49492222 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.387528639 |
|
|
Oct 09 11:00:37 PM UTC 24 |
Oct 09 11:00:53 PM UTC 24 |
1411948143 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.770460462 |
|
|
Oct 09 11:00:50 PM UTC 24 |
Oct 09 11:00:53 PM UTC 24 |
148974799 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.4261883721 |
|
|
Oct 09 11:00:37 PM UTC 24 |
Oct 09 11:00:54 PM UTC 24 |
318525836 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.382478441 |
|
|
Oct 09 11:00:46 PM UTC 24 |
Oct 09 11:00:54 PM UTC 24 |
168778337 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1226237143 |
|
|
Oct 09 11:00:43 PM UTC 24 |
Oct 09 11:00:55 PM UTC 24 |
1816701317 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.1780010458 |
|
|
Oct 09 11:00:50 PM UTC 24 |
Oct 09 11:00:55 PM UTC 24 |
62645522 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.3487432754 |
|
|
Oct 09 11:00:53 PM UTC 24 |
Oct 09 11:00:56 PM UTC 24 |
13765432 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.2531791515 |
|
|
Oct 09 11:00:52 PM UTC 24 |
Oct 09 11:00:56 PM UTC 24 |
193194475 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.3570077595 |
|
|
Oct 09 11:00:41 PM UTC 24 |
Oct 09 11:00:57 PM UTC 24 |
1954357282 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3864159772 |
|
|
Oct 09 11:00:55 PM UTC 24 |
Oct 09 11:00:58 PM UTC 24 |
12670153 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.2201594868 |
|
|
Oct 09 11:00:41 PM UTC 24 |
Oct 09 11:00:58 PM UTC 24 |
1722141893 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.1197334120 |
|
|
Oct 09 11:00:50 PM UTC 24 |
Oct 09 11:00:58 PM UTC 24 |
490646646 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.2348970782 |
|
|
Oct 09 11:00:17 PM UTC 24 |
Oct 09 11:00:58 PM UTC 24 |
831943035 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.3607374088 |
|
|
Oct 09 11:00:46 PM UTC 24 |
Oct 09 11:00:58 PM UTC 24 |
301886477 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.3424916570 |
|
|
Oct 09 11:00:55 PM UTC 24 |
Oct 09 11:00:58 PM UTC 24 |
19028230 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.799399799 |
|
|
Oct 09 11:00:53 PM UTC 24 |
Oct 09 11:00:59 PM UTC 24 |
755822893 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.921573577 |
|
|
Oct 09 11:00:37 PM UTC 24 |
Oct 09 11:01:01 PM UTC 24 |
997781596 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.693136418 |
|
|
Oct 09 11:00:41 PM UTC 24 |
Oct 09 11:00:59 PM UTC 24 |
1396001331 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.1495440457 |
|
|
Oct 09 11:00:47 PM UTC 24 |
Oct 09 11:00:59 PM UTC 24 |
991415502 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.1817781724 |
|
|
Oct 09 11:00:52 PM UTC 24 |
Oct 09 11:01:01 PM UTC 24 |
1368515087 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2745584993 |
|
|
Oct 09 11:00:59 PM UTC 24 |
Oct 09 11:01:02 PM UTC 24 |
40223678 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.1668001799 |
|
|
Oct 09 11:00:59 PM UTC 24 |
Oct 09 11:01:02 PM UTC 24 |
16519712 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.3992700241 |
|
|
Oct 09 11:00:52 PM UTC 24 |
Oct 09 11:01:02 PM UTC 24 |
862167578 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.227112378 |
|
|
Oct 09 11:00:48 PM UTC 24 |
Oct 09 11:01:02 PM UTC 24 |
1925118340 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.3252066917 |
|
|
Oct 09 11:00:59 PM UTC 24 |
Oct 09 11:01:02 PM UTC 24 |
65577831 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.613594567 |
|
|
Oct 09 11:00:30 PM UTC 24 |
Oct 09 11:01:03 PM UTC 24 |
1301732133 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.4200909435 |
|
|
Oct 09 11:00:35 PM UTC 24 |
Oct 09 11:01:04 PM UTC 24 |
229409564 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.475411644 |
|
|
Oct 09 11:00:39 PM UTC 24 |
Oct 09 11:01:04 PM UTC 24 |
767143941 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.2413697376 |
|
|
Oct 09 11:01:01 PM UTC 24 |
Oct 09 11:01:05 PM UTC 24 |
714686995 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.3644762736 |
|
|
Oct 09 11:00:48 PM UTC 24 |
Oct 09 11:01:05 PM UTC 24 |
1331933277 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.2358048017 |
|
|
Oct 09 11:00:55 PM UTC 24 |
Oct 09 11:01:06 PM UTC 24 |
160146923 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.1959325278 |
|
|
Oct 09 11:00:52 PM UTC 24 |
Oct 09 11:01:06 PM UTC 24 |
2341196033 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.646834876 |
|
|
Oct 09 11:00:52 PM UTC 24 |
Oct 09 11:01:06 PM UTC 24 |
305532902 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.2200222149 |
|
|
Oct 09 11:01:02 PM UTC 24 |
Oct 09 11:01:07 PM UTC 24 |
819895321 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.4152877747 |
|
|
Oct 09 11:01:04 PM UTC 24 |
Oct 09 11:01:07 PM UTC 24 |
15697419 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1235562456 |
|
|
Oct 09 11:01:04 PM UTC 24 |
Oct 09 11:01:07 PM UTC 24 |
39579844 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.2705132016 |
|
|
Oct 09 11:00:57 PM UTC 24 |
Oct 09 11:01:08 PM UTC 24 |
962270239 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1655447472 |
|
|
Oct 09 11:01:04 PM UTC 24 |
Oct 09 11:01:09 PM UTC 24 |
47079562 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.56037066 |
|
|
Oct 09 10:59:59 PM UTC 24 |
Oct 09 11:01:09 PM UTC 24 |
2571603908 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.3494173514 |
|
|
Oct 09 11:00:59 PM UTC 24 |
Oct 09 11:01:09 PM UTC 24 |
70277487 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.2572684703 |
|
|
Oct 09 11:00:45 PM UTC 24 |
Oct 09 11:01:10 PM UTC 24 |
362142386 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.4008018547 |
|
|
Oct 09 10:59:27 PM UTC 24 |
Oct 09 11:01:11 PM UTC 24 |
3988291499 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.1125744773 |
|
|
Oct 09 11:00:52 PM UTC 24 |
Oct 09 11:01:11 PM UTC 24 |
1995520227 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.1727908453 |
|
|
Oct 09 11:00:57 PM UTC 24 |
Oct 09 11:01:11 PM UTC 24 |
310285151 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.1925186535 |
|
|
Oct 09 11:01:09 PM UTC 24 |
Oct 09 11:01:11 PM UTC 24 |
24663832 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.734224038 |
|
|
Oct 09 11:01:02 PM UTC 24 |
Oct 09 11:01:11 PM UTC 24 |
917459965 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.1704816376 |
|
|
Oct 09 11:01:06 PM UTC 24 |
Oct 09 11:01:12 PM UTC 24 |
132350207 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.2655414704 |
|
|
Oct 09 11:01:02 PM UTC 24 |
Oct 09 11:01:12 PM UTC 24 |
1013145491 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.2507253865 |
|
|
Oct 09 11:00:56 PM UTC 24 |
Oct 09 11:01:12 PM UTC 24 |
1958964635 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.241926474 |
|
|
Oct 09 11:01:10 PM UTC 24 |
Oct 09 11:01:12 PM UTC 24 |
60082904 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.4204074184 |
|
|
Oct 09 11:01:07 PM UTC 24 |
Oct 09 11:01:13 PM UTC 24 |
88440179 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.4100793205 |
|
|
Oct 09 11:01:06 PM UTC 24 |
Oct 09 11:01:13 PM UTC 24 |
181767488 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.3693606706 |
|
|
Oct 09 10:58:36 PM UTC 24 |
Oct 09 11:01:13 PM UTC 24 |
36712285639 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.3222257463 |
|
|
Oct 09 11:01:01 PM UTC 24 |
Oct 09 11:01:14 PM UTC 24 |
898067555 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.166360618 |
|
|
Oct 09 11:01:10 PM UTC 24 |
Oct 09 11:01:14 PM UTC 24 |
146650406 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.2815669221 |
|
|
Oct 09 11:00:56 PM UTC 24 |
Oct 09 11:01:14 PM UTC 24 |
394763191 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.2592205132 |
|
|
Oct 09 11:01:13 PM UTC 24 |
Oct 09 11:01:16 PM UTC 24 |
22140932 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1702631403 |
|
|
Oct 09 11:01:02 PM UTC 24 |
Oct 09 11:01:17 PM UTC 24 |
879008832 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.1373745128 |
|
|
Oct 09 11:01:07 PM UTC 24 |
Oct 09 11:01:17 PM UTC 24 |
830886268 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.3102449291 |
|
|
Oct 09 11:00:59 PM UTC 24 |
Oct 09 11:01:17 PM UTC 24 |
573202061 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.1893863802 |
|
|
Oct 09 11:01:12 PM UTC 24 |
Oct 09 11:01:17 PM UTC 24 |
85596743 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.3869743956 |
|
|
Oct 09 11:01:12 PM UTC 24 |
Oct 09 11:01:17 PM UTC 24 |
340309936 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.977475947 |
|
|
Oct 09 11:01:15 PM UTC 24 |
Oct 09 11:01:17 PM UTC 24 |
21102787 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.3188218073 |
|
|
Oct 09 11:01:02 PM UTC 24 |
Oct 09 11:01:18 PM UTC 24 |
1480607602 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.1780960035 |
|
|
Oct 09 11:01:13 PM UTC 24 |
Oct 09 11:01:18 PM UTC 24 |
91796698 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.3261227856 |
|
|
Oct 09 11:00:50 PM UTC 24 |
Oct 09 11:01:19 PM UTC 24 |
569472723 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.3349279318 |
|
|
Oct 09 11:01:15 PM UTC 24 |
Oct 09 11:01:19 PM UTC 24 |
117499907 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.2524664433 |
|
|
Oct 09 10:58:11 PM UTC 24 |
Oct 09 11:01:19 PM UTC 24 |
9924014676 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.29466044 |
|
|
Oct 09 11:01:06 PM UTC 24 |
Oct 09 11:01:22 PM UTC 24 |
633077067 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.2685136415 |
|
|
Oct 09 11:01:16 PM UTC 24 |
Oct 09 11:01:22 PM UTC 24 |
66907617 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.3034136711 |
|
|
Oct 09 11:01:19 PM UTC 24 |
Oct 09 11:01:22 PM UTC 24 |
24639403 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.44605437 |
|
|
Oct 09 10:55:40 PM UTC 24 |
Oct 09 11:01:22 PM UTC 24 |
12059017344 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.602038106 |
|
|
Oct 09 11:01:19 PM UTC 24 |
Oct 09 11:01:23 PM UTC 24 |
22079208 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.4095847298 |
|
|
Oct 09 11:01:07 PM UTC 24 |
Oct 09 11:01:23 PM UTC 24 |
1657251298 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.435789248 |
|
|
Oct 09 11:01:06 PM UTC 24 |
Oct 09 11:01:24 PM UTC 24 |
1584816128 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.1081691468 |
|
|
Oct 09 11:01:19 PM UTC 24 |
Oct 09 11:01:24 PM UTC 24 |
382317984 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.1213086519 |
|
|
Oct 09 11:01:15 PM UTC 24 |
Oct 09 11:01:24 PM UTC 24 |
457466172 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.631793600 |
|
|
Oct 09 11:01:18 PM UTC 24 |
Oct 09 11:01:24 PM UTC 24 |
2361771416 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.2636514792 |
|
|
Oct 09 11:00:55 PM UTC 24 |
Oct 09 11:01:26 PM UTC 24 |
507917732 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.4206455982 |
|
|
Oct 09 11:01:13 PM UTC 24 |
Oct 09 11:01:26 PM UTC 24 |
998043319 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.2632756945 |
|
|
Oct 09 11:01:08 PM UTC 24 |
Oct 09 11:01:26 PM UTC 24 |
458386338 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.2057738517 |
|
|
Oct 09 11:01:13 PM UTC 24 |
Oct 09 11:01:27 PM UTC 24 |
1705248254 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.1514125727 |
|
|
Oct 09 11:00:59 PM UTC 24 |
Oct 09 11:01:27 PM UTC 24 |
2178829351 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.880550239 |
|
|
Oct 09 11:01:23 PM UTC 24 |
Oct 09 11:01:28 PM UTC 24 |
213269335 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.4170708229 |
|
|
Oct 09 11:01:24 PM UTC 24 |
Oct 09 11:01:28 PM UTC 24 |
602333394 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.542225259 |
|
|
Oct 09 11:01:12 PM UTC 24 |
Oct 09 11:01:29 PM UTC 24 |
438432698 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.330311316 |
|
|
Oct 09 11:01:27 PM UTC 24 |
Oct 09 11:01:29 PM UTC 24 |
176627250 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.374846641 |
|
|
Oct 09 11:01:13 PM UTC 24 |
Oct 09 11:01:30 PM UTC 24 |
2391097152 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3200242525 |
|
|
Oct 09 11:01:28 PM UTC 24 |
Oct 09 11:01:30 PM UTC 24 |
13653275 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.1377700013 |
|
|
Oct 09 11:01:18 PM UTC 24 |
Oct 09 11:01:31 PM UTC 24 |
822072549 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.2798471866 |
|
|
Oct 09 11:01:13 PM UTC 24 |
Oct 09 11:01:31 PM UTC 24 |
808862769 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.480652462 |
|
|
Oct 09 11:01:18 PM UTC 24 |
Oct 09 11:01:32 PM UTC 24 |
273449105 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.2636731795 |
|
|
Oct 09 11:01:27 PM UTC 24 |
Oct 09 11:01:32 PM UTC 24 |
104083622 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.2639329744 |
|
|
Oct 09 11:01:18 PM UTC 24 |
Oct 09 11:01:32 PM UTC 24 |
517784302 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.3325513065 |
|
|
Oct 09 11:01:23 PM UTC 24 |
Oct 09 11:01:33 PM UTC 24 |
70965590 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.3980103934 |
|
|
Oct 09 11:01:28 PM UTC 24 |
Oct 09 11:01:33 PM UTC 24 |
267322964 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.3708793945 |
|
|
Oct 09 11:01:29 PM UTC 24 |
Oct 09 11:01:34 PM UTC 24 |
36268252 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.1798621868 |
|
|
Oct 09 11:00:17 PM UTC 24 |
Oct 09 11:01:34 PM UTC 24 |
15454902498 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.767809072 |
|
|
Oct 09 11:01:24 PM UTC 24 |
Oct 09 11:01:34 PM UTC 24 |
239610071 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1743272215 |
|
|
Oct 09 11:01:18 PM UTC 24 |
Oct 09 11:01:34 PM UTC 24 |
4543328756 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.1648881015 |
|
|
Oct 09 11:01:18 PM UTC 24 |
Oct 09 11:01:35 PM UTC 24 |
1852578124 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.3808827314 |
|
|
Oct 09 11:00:28 PM UTC 24 |
Oct 09 11:01:35 PM UTC 24 |
10687019176 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.3274684329 |
|
|
Oct 09 11:01:04 PM UTC 24 |
Oct 09 11:01:35 PM UTC 24 |
174223052 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.1532368784 |
|
|
Oct 09 11:00:37 PM UTC 24 |
Oct 09 11:01:36 PM UTC 24 |
2038492522 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.4104642633 |
|
|
Oct 09 11:01:34 PM UTC 24 |
Oct 09 11:01:36 PM UTC 24 |
35126959 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.1886643075 |
|
|
Oct 09 11:01:31 PM UTC 24 |
Oct 09 11:01:36 PM UTC 24 |
256114900 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.3265157557 |
|
|
Oct 09 11:01:34 PM UTC 24 |
Oct 09 11:01:36 PM UTC 24 |
29525519 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.126863778 |
|
|
Oct 09 11:01:58 PM UTC 24 |
Oct 09 11:02:08 PM UTC 24 |
223557482 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.2869784006 |
|
|
Oct 09 11:01:38 PM UTC 24 |
Oct 09 11:02:09 PM UTC 24 |
2251110297 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.3513634380 |
|
|
Oct 09 11:01:34 PM UTC 24 |
Oct 09 11:01:37 PM UTC 24 |
79042538 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.3917147536 |
|
|
Oct 09 11:01:23 PM UTC 24 |
Oct 09 11:01:37 PM UTC 24 |
646317149 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.1126331625 |
|
|
Oct 09 11:01:10 PM UTC 24 |
Oct 09 11:01:38 PM UTC 24 |
243550712 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.1588684347 |
|
|
Oct 09 11:01:30 PM UTC 24 |
Oct 09 11:01:38 PM UTC 24 |
440599820 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.286124580 |
|
|
Oct 09 11:01:25 PM UTC 24 |
Oct 09 11:01:38 PM UTC 24 |
218707343 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.1296319465 |
|
|
Oct 09 11:01:37 PM UTC 24 |
Oct 09 11:01:39 PM UTC 24 |
49145800 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.1500753213 |
|
|
Oct 09 11:01:25 PM UTC 24 |
Oct 09 11:01:39 PM UTC 24 |
731269120 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.3482887300 |
|
|
Oct 09 11:01:35 PM UTC 24 |
Oct 09 11:01:40 PM UTC 24 |
88022834 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2652617271 |
|
|
Oct 09 11:01:32 PM UTC 24 |
Oct 09 11:01:40 PM UTC 24 |
861947604 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.2466748378 |
|
|
Oct 09 11:01:25 PM UTC 24 |
Oct 09 11:01:41 PM UTC 24 |
596602092 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.558988402 |
|
|
Oct 09 11:01:35 PM UTC 24 |
Oct 09 11:01:41 PM UTC 24 |
531362234 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.4005236288 |
|
|
Oct 09 11:01:19 PM UTC 24 |
Oct 09 11:01:41 PM UTC 24 |
8375720119 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2907238491 |
|
|
Oct 09 11:01:38 PM UTC 24 |
Oct 09 11:01:41 PM UTC 24 |
117899550 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.3747484428 |
|
|
Oct 09 11:01:29 PM UTC 24 |
Oct 09 11:01:41 PM UTC 24 |
212542430 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.1527128359 |
|
|
Oct 09 11:01:38 PM UTC 24 |
Oct 09 11:01:41 PM UTC 24 |
50001020 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.367874075 |
|
|
Oct 09 11:01:15 PM UTC 24 |
Oct 09 11:01:41 PM UTC 24 |
1111884807 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.970959992 |
|
|
Oct 09 11:01:31 PM UTC 24 |
Oct 09 11:01:43 PM UTC 24 |
570205384 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.453094220 |
|
|
Oct 09 11:01:39 PM UTC 24 |
Oct 09 11:01:43 PM UTC 24 |
539632287 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.3975911240 |
|
|
Oct 09 11:01:38 PM UTC 24 |
Oct 09 11:01:44 PM UTC 24 |
250179088 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.3565663954 |
|
|
Oct 09 11:01:37 PM UTC 24 |
Oct 09 11:01:45 PM UTC 24 |
871038809 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.4089708893 |
|
|
Oct 09 11:01:58 PM UTC 24 |
Oct 09 11:02:11 PM UTC 24 |
319849934 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.1847421305 |
|
|
Oct 09 11:01:31 PM UTC 24 |
Oct 09 11:01:45 PM UTC 24 |
8283836967 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1840615775 |
|
|
Oct 09 11:01:43 PM UTC 24 |
Oct 09 11:01:45 PM UTC 24 |
40926903 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.707822719 |
|
|
Oct 09 11:01:43 PM UTC 24 |
Oct 09 11:01:46 PM UTC 24 |
81549725 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.1634063088 |
|
|
Oct 09 10:58:18 PM UTC 24 |
Oct 09 11:01:46 PM UTC 24 |
32909456043 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.458243110 |
|
|
Oct 09 11:01:40 PM UTC 24 |
Oct 09 11:01:46 PM UTC 24 |
2667477372 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.739542819 |
|
|
Oct 09 11:01:13 PM UTC 24 |
Oct 09 11:01:47 PM UTC 24 |
15072929861 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.437012855 |
|
|
Oct 09 11:01:35 PM UTC 24 |
Oct 09 11:01:47 PM UTC 24 |
1081730645 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.3727557156 |
|
|
Oct 09 11:01:35 PM UTC 24 |
Oct 09 11:01:48 PM UTC 24 |
1062711182 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.3758519242 |
|
|
Oct 09 11:01:37 PM UTC 24 |
Oct 09 11:01:48 PM UTC 24 |
4013384749 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.686546929 |
|
|
Oct 09 11:01:44 PM UTC 24 |
Oct 09 11:01:49 PM UTC 24 |
81829063 ps |