Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.36 100.00 97.45 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.10 97.79 97.70 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.10 100.00 83.10 99.89 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test_fatal_bus_integ_error 100.00 100.00
u_alert_test_fatal_prog_error 100.00 100.00
u_alert_test_fatal_state_error 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_claim_transition_if 100.00 100.00
u_claim_transition_if_regwen 100.00 100.00 100.00 100.00
u_device_id_0 100.00 100.00
u_device_id_1 100.00 100.00
u_device_id_2 100.00 100.00
u_device_id_3 100.00 100.00
u_device_id_4 100.00 100.00
u_device_id_5 100.00 100.00
u_device_id_6 100.00 100.00
u_device_id_7 100.00 100.00
u_hw_revision0_product_id 33.33 33.33
u_hw_revision0_silicon_creator_id 33.33 33.33
u_hw_revision1_reserved 33.33 33.33
u_hw_revision1_revision_id 33.33 33.33
u_lc_id_state 66.67 66.67
u_lc_state 100.00 100.00
u_lc_transition_cnt 100.00 100.00
u_manuf_state_0 100.00 100.00
u_manuf_state_1 100.00 100.00
u_manuf_state_2 100.00 100.00
u_manuf_state_3 100.00 100.00
u_manuf_state_4 100.00 100.00
u_manuf_state_5 100.00 100.00
u_manuf_state_6 100.00 100.00
u_manuf_state_7 100.00 100.00
u_otp_vendor_test_ctrl 100.00 100.00
u_otp_vendor_test_status 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.97 97.14 98.75 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_status_bus_integ_error 100.00 100.00
u_status_ext_clock_switched 100.00 100.00
u_status_flash_rma_error 100.00 100.00
u_status_initialized 100.00 100.00
u_status_otp_error 100.00 100.00
u_status_otp_partition_error 100.00 100.00
u_status_ready 100.00 100.00
u_status_state_error 100.00 100.00
u_status_token_error 100.00 100.00
u_status_transition_count_error 100.00 100.00
u_status_transition_error 100.00 100.00
u_status_transition_successful 100.00 100.00
u_transition_cmd 100.00 100.00
u_transition_ctrl_ext_clock_en 100.00 100.00
u_transition_ctrl_volatile_raw_unlock 100.00 100.00
u_transition_regwen 100.00 100.00
u_transition_target 100.00 100.00
u_transition_token_0 100.00 100.00
u_transition_token_1 100.00 100.00
u_transition_token_2 100.00 100.00
u_transition_token_3 100.00 100.00



Module Instance : tb.dut.u_reg_tap

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.73 100.00 98.92 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.90 97.36 98.54 73.61 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.10 100.00 83.10 99.89 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test_fatal_bus_integ_error 100.00 100.00
u_alert_test_fatal_prog_error 100.00 100.00
u_alert_test_fatal_state_error 100.00 100.00
u_chk 90.18 100.00 70.54 100.00
u_claim_transition_if 100.00 100.00
u_claim_transition_if_regwen 100.00 100.00 100.00 100.00
u_device_id_0 100.00 100.00
u_device_id_1 100.00 100.00
u_device_id_2 100.00 100.00
u_device_id_3 100.00 100.00
u_device_id_4 100.00 100.00
u_device_id_5 100.00 100.00
u_device_id_6 100.00 100.00
u_device_id_7 100.00 100.00
u_hw_revision0_product_id 33.33 33.33
u_hw_revision0_silicon_creator_id 33.33 33.33
u_hw_revision1_reserved 33.33 33.33
u_hw_revision1_revision_id 33.33 33.33
u_lc_id_state 100.00 100.00
u_lc_state 100.00 100.00
u_lc_transition_cnt 100.00 100.00
u_manuf_state_0 100.00 100.00
u_manuf_state_1 100.00 100.00
u_manuf_state_2 100.00 100.00
u_manuf_state_3 100.00 100.00
u_manuf_state_4 100.00 100.00
u_manuf_state_5 100.00 100.00
u_manuf_state_6 100.00 100.00
u_manuf_state_7 100.00 100.00
u_otp_vendor_test_ctrl 100.00 100.00
u_otp_vendor_test_status 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 97.14 92.19 96.36 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_status_bus_integ_error 100.00 100.00
u_status_ext_clock_switched 100.00 100.00
u_status_flash_rma_error 100.00 100.00
u_status_initialized 100.00 100.00
u_status_otp_error 100.00 100.00
u_status_otp_partition_error 100.00 100.00
u_status_ready 100.00 100.00
u_status_state_error 100.00 100.00
u_status_token_error 100.00 100.00
u_status_transition_count_error 100.00 100.00
u_status_transition_error 100.00 100.00
u_status_transition_successful 100.00 100.00
u_transition_cmd 100.00 100.00
u_transition_ctrl_ext_clock_en 100.00 100.00
u_transition_ctrl_volatile_raw_unlock 100.00 100.00
u_transition_regwen 100.00 100.00
u_transition_target 100.00 100.00
u_transition_token_0 100.00 100.00
u_transition_token_1 100.00 100.00
u_transition_token_2 100.00 100.00
u_transition_token_3 100.00 100.00

Line Coverage for Module : lc_ctrl_reg_top
Line No.TotalCoveredPercent
TOTAL227227100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN23311100.00
CONT_ASSIGN24811100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49911100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN55211100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN56111100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN59211100.00
CONT_ASSIGN59911100.00
CONT_ASSIGN60211100.00
CONT_ASSIGN61611100.00
CONT_ASSIGN62311100.00
CONT_ASSIGN62611100.00
CONT_ASSIGN64011100.00
CONT_ASSIGN64711100.00
CONT_ASSIGN65011100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN67111100.00
CONT_ASSIGN67411100.00
CONT_ASSIGN68811100.00
CONT_ASSIGN69411100.00
CONT_ASSIGN69711100.00
CONT_ASSIGN71111100.00
CONT_ASSIGN71711100.00
CONT_ASSIGN72011100.00
CONT_ASSIGN73411100.00
ALWAYS11403636100.00
CONT_ASSIGN117811100.00
ALWAYS118211100.00
CONT_ASSIGN122111100.00
CONT_ASSIGN122311100.00
CONT_ASSIGN122511100.00
CONT_ASSIGN122711100.00
CONT_ASSIGN122811100.00
CONT_ASSIGN122911100.00
CONT_ASSIGN123111100.00
CONT_ASSIGN123211100.00
CONT_ASSIGN123311100.00
CONT_ASSIGN123511100.00
CONT_ASSIGN123611100.00
CONT_ASSIGN123711100.00
CONT_ASSIGN123911100.00
CONT_ASSIGN124011100.00
CONT_ASSIGN124111100.00
CONT_ASSIGN124311100.00
CONT_ASSIGN124511100.00
CONT_ASSIGN124611100.00
CONT_ASSIGN124711100.00
CONT_ASSIGN124911100.00
CONT_ASSIGN125011100.00
CONT_ASSIGN125111100.00
CONT_ASSIGN125311100.00
CONT_ASSIGN125411100.00
CONT_ASSIGN125511100.00
CONT_ASSIGN125711100.00
CONT_ASSIGN125811100.00
CONT_ASSIGN125911100.00
CONT_ASSIGN126111100.00
CONT_ASSIGN126211100.00
CONT_ASSIGN126311100.00
CONT_ASSIGN126511100.00
CONT_ASSIGN126611100.00
CONT_ASSIGN126711100.00
CONT_ASSIGN126911100.00
CONT_ASSIGN127011100.00
CONT_ASSIGN127111100.00
CONT_ASSIGN127211100.00
CONT_ASSIGN127311100.00
CONT_ASSIGN127411100.00
CONT_ASSIGN127511100.00
CONT_ASSIGN127611100.00
CONT_ASSIGN127711100.00
CONT_ASSIGN127811100.00
CONT_ASSIGN127911100.00
CONT_ASSIGN128011100.00
CONT_ASSIGN128111100.00
CONT_ASSIGN128211100.00
CONT_ASSIGN128311100.00
CONT_ASSIGN128411100.00
CONT_ASSIGN128511100.00
CONT_ASSIGN128611100.00
CONT_ASSIGN128711100.00
CONT_ASSIGN128811100.00
CONT_ASSIGN128911100.00
CONT_ASSIGN129011100.00
CONT_ASSIGN129111100.00
ALWAYS12953636100.00
ALWAYS13355353100.00
CONT_ASSIGN150400
CONT_ASSIGN151211100.00
CONT_ASSIGN151311100.00

Click here to see the source line report.

Cond Coverage for Module : lc_ctrl_reg_top
TotalCoveredPercent
Conditions43242197.45
Logical43242197.45
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1232100.00
1233-129192.95

Branch Coverage for Module : lc_ctrl_reg_top
Line No.TotalCoveredPercent
Branches 41 41 100.00
TERNARY 1178 2 2 100.00
IF 68 3 3 100.00
CASE 1336 36 36 100.00


1178 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


68 if (!rst_ni) begin -1- 69 err_q <= '0; ==> 70 end else if (intg_err || reg_we_err) begin -2- 71 err_q <= 1'b1; ==> 72 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T91,T87,T73
0 0 Covered T1,T2,T3


1336 unique case (1'b1) -1- 1337 addr_hit[0]: begin 1338 reg_rdata_next[0] = '0; ==> 1339 reg_rdata_next[1] = '0; 1340 reg_rdata_next[2] = '0; 1341 end 1342 1343 addr_hit[1]: begin 1344 reg_rdata_next[0] = status_initialized_qs; ==> 1345 reg_rdata_next[1] = status_ready_qs; 1346 reg_rdata_next[2] = status_ext_clock_switched_qs; 1347 reg_rdata_next[3] = status_transition_successful_qs; 1348 reg_rdata_next[4] = status_transition_count_error_qs; 1349 reg_rdata_next[5] = status_transition_error_qs; 1350 reg_rdata_next[6] = status_token_error_qs; 1351 reg_rdata_next[7] = status_flash_rma_error_qs; 1352 reg_rdata_next[8] = status_otp_error_qs; 1353 reg_rdata_next[9] = status_state_error_qs; 1354 reg_rdata_next[10] = status_bus_integ_error_qs; 1355 reg_rdata_next[11] = status_otp_partition_error_qs; 1356 end 1357 1358 addr_hit[2]: begin 1359 reg_rdata_next[0] = claim_transition_if_regwen_qs; ==> 1360 end 1361 1362 addr_hit[3]: begin 1363 reg_rdata_next[7:0] = claim_transition_if_qs; ==> 1364 end 1365 1366 addr_hit[4]: begin 1367 reg_rdata_next[0] = transition_regwen_qs; ==> 1368 end 1369 1370 addr_hit[5]: begin 1371 reg_rdata_next[0] = '0; ==> 1372 end 1373 1374 addr_hit[6]: begin 1375 reg_rdata_next[0] = transition_ctrl_ext_clock_en_qs; ==> 1376 reg_rdata_next[1] = transition_ctrl_volatile_raw_unlock_qs; 1377 end 1378 1379 addr_hit[7]: begin 1380 reg_rdata_next[31:0] = transition_token_0_qs; ==> 1381 end 1382 1383 addr_hit[8]: begin 1384 reg_rdata_next[31:0] = transition_token_1_qs; ==> 1385 end 1386 1387 addr_hit[9]: begin 1388 reg_rdata_next[31:0] = transition_token_2_qs; ==> 1389 end 1390 1391 addr_hit[10]: begin 1392 reg_rdata_next[31:0] = transition_token_3_qs; ==> 1393 end 1394 1395 addr_hit[11]: begin 1396 reg_rdata_next[29:0] = transition_target_qs; ==> 1397 end 1398 1399 addr_hit[12]: begin 1400 reg_rdata_next[31:0] = otp_vendor_test_ctrl_qs; ==> 1401 end 1402 1403 addr_hit[13]: begin 1404 reg_rdata_next[31:0] = otp_vendor_test_status_qs; ==> 1405 end 1406 1407 addr_hit[14]: begin 1408 reg_rdata_next[29:0] = lc_state_qs; ==> 1409 end 1410 1411 addr_hit[15]: begin 1412 reg_rdata_next[4:0] = lc_transition_cnt_qs; ==> 1413 end 1414 1415 addr_hit[16]: begin 1416 reg_rdata_next[31:0] = lc_id_state_qs; ==> 1417 end 1418 1419 addr_hit[17]: begin 1420 reg_rdata_next[15:0] = hw_revision0_product_id_qs; ==> 1421 reg_rdata_next[31:16] = hw_revision0_silicon_creator_id_qs; 1422 end 1423 1424 addr_hit[18]: begin 1425 reg_rdata_next[7:0] = hw_revision1_revision_id_qs; ==> 1426 reg_rdata_next[31:8] = hw_revision1_reserved_qs; 1427 end 1428 1429 addr_hit[19]: begin 1430 reg_rdata_next[31:0] = device_id_0_qs; ==> 1431 end 1432 1433 addr_hit[20]: begin 1434 reg_rdata_next[31:0] = device_id_1_qs; ==> 1435 end 1436 1437 addr_hit[21]: begin 1438 reg_rdata_next[31:0] = device_id_2_qs; ==> 1439 end 1440 1441 addr_hit[22]: begin 1442 reg_rdata_next[31:0] = device_id_3_qs; ==> 1443 end 1444 1445 addr_hit[23]: begin 1446 reg_rdata_next[31:0] = device_id_4_qs; ==> 1447 end 1448 1449 addr_hit[24]: begin 1450 reg_rdata_next[31:0] = device_id_5_qs; ==> 1451 end 1452 1453 addr_hit[25]: begin 1454 reg_rdata_next[31:0] = device_id_6_qs; ==> 1455 end 1456 1457 addr_hit[26]: begin 1458 reg_rdata_next[31:0] = device_id_7_qs; ==> 1459 end 1460 1461 addr_hit[27]: begin 1462 reg_rdata_next[31:0] = manuf_state_0_qs; ==> 1463 end 1464 1465 addr_hit[28]: begin 1466 reg_rdata_next[31:0] = manuf_state_1_qs; ==> 1467 end 1468 1469 addr_hit[29]: begin 1470 reg_rdata_next[31:0] = manuf_state_2_qs; ==> 1471 end 1472 1473 addr_hit[30]: begin 1474 reg_rdata_next[31:0] = manuf_state_3_qs; ==> 1475 end 1476 1477 addr_hit[31]: begin 1478 reg_rdata_next[31:0] = manuf_state_4_qs; ==> 1479 end 1480 1481 addr_hit[32]: begin 1482 reg_rdata_next[31:0] = manuf_state_5_qs; ==> 1483 end 1484 1485 addr_hit[33]: begin 1486 reg_rdata_next[31:0] = manuf_state_6_qs; ==> 1487 end 1488 1489 addr_hit[34]: begin 1490 reg_rdata_next[31:0] = manuf_state_7_qs; ==> 1491 end 1492 1493 default: begin 1494 reg_rdata_next = '1; ==>

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
addr_hit[21] Covered T1,T2,T3
addr_hit[22] Covered T1,T2,T3
addr_hit[23] Covered T1,T2,T3
addr_hit[24] Covered T1,T2,T3
addr_hit[25] Covered T1,T2,T3
addr_hit[26] Covered T1,T2,T3
addr_hit[27] Covered T1,T2,T3
addr_hit[28] Covered T1,T2,T3
addr_hit[29] Covered T1,T2,T3
addr_hit[30] Covered T1,T2,T3
addr_hit[31] Covered T1,T2,T3
addr_hit[32] Covered T1,T2,T3
addr_hit[33] Covered T1,T2,T3
addr_hit[34] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : lc_ctrl_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 120528550 1945518 0 0
reAfterRv 120528550 1945517 0 0
rePulse 120528550 1574803 0 0
wePulse 120528550 370714 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 120528550 1945518 0 0
T1 1059 59 0 0
T2 2661 418 0 0
T3 1066 3 0 0
T4 62242 251 0 0
T5 7142 154 0 0
T6 15718 136 0 0
T7 24720 218 0 0
T8 17991 232 0 0
T9 0 274 0 0
T11 59454 267 0 0
T12 1274 20 0 0
T13 1016 7 0 0
T14 16415 65 0 0
T15 5970 0 0 0
T16 6146 0 0 0
T19 0 136 0 0
T20 0 118 0 0
T21 0 876 0 0
T22 981 3 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 120528550 1945517 0 0
T1 1059 59 0 0
T2 2661 418 0 0
T3 1066 3 0 0
T4 62242 251 0 0
T5 7142 154 0 0
T6 15718 136 0 0
T7 24720 218 0 0
T8 17991 232 0 0
T9 0 274 0 0
T11 59454 267 0 0
T12 1274 20 0 0
T13 1016 7 0 0
T14 16415 65 0 0
T15 5970 0 0 0
T16 6146 0 0 0
T19 0 136 0 0
T20 0 118 0 0
T21 0 876 0 0
T22 981 3 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 120528550 1574803 0 0
T1 1059 43 0 0
T2 2661 298 0 0
T3 1066 2 0 0
T4 62242 131 0 0
T5 7142 98 0 0
T6 15718 70 0 0
T7 24720 119 0 0
T8 17991 118 0 0
T9 0 150 0 0
T11 59454 123 0 0
T12 1274 5 0 0
T13 1016 0 0 0
T14 16415 41 0 0
T15 5970 152 0 0
T16 6146 0 0 0
T19 0 60 0 0
T20 0 56 0 0
T21 0 444 0 0
T22 981 2 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 120528550 370714 0 0
T1 1059 16 0 0
T2 2661 120 0 0
T3 1066 1 0 0
T4 62242 120 0 0
T5 7142 56 0 0
T6 15718 66 0 0
T7 24720 99 0 0
T8 17991 114 0 0
T9 0 124 0 0
T11 59454 144 0 0
T12 1274 15 0 0
T13 1016 7 0 0
T14 16415 24 0 0
T15 5970 0 0 0
T16 6146 0 0 0
T19 0 76 0 0
T20 0 62 0 0
T21 0 432 0 0
T22 981 1 0 0

Line Coverage for Instance : tb.dut.u_reg
Line No.TotalCoveredPercent
TOTAL227227100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN23311100.00
CONT_ASSIGN24811100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49911100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN55211100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN56111100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN59211100.00
CONT_ASSIGN59911100.00
CONT_ASSIGN60211100.00
CONT_ASSIGN61611100.00
CONT_ASSIGN62311100.00
CONT_ASSIGN62611100.00
CONT_ASSIGN64011100.00
CONT_ASSIGN64711100.00
CONT_ASSIGN65011100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN67111100.00
CONT_ASSIGN67411100.00
CONT_ASSIGN68811100.00
CONT_ASSIGN69411100.00
CONT_ASSIGN69711100.00
CONT_ASSIGN71111100.00
CONT_ASSIGN71711100.00
CONT_ASSIGN72011100.00
CONT_ASSIGN73411100.00
ALWAYS11403636100.00
CONT_ASSIGN117811100.00
ALWAYS118211100.00
CONT_ASSIGN122111100.00
CONT_ASSIGN122311100.00
CONT_ASSIGN122511100.00
CONT_ASSIGN122711100.00
CONT_ASSIGN122811100.00
CONT_ASSIGN122911100.00
CONT_ASSIGN123111100.00
CONT_ASSIGN123211100.00
CONT_ASSIGN123311100.00
CONT_ASSIGN123511100.00
CONT_ASSIGN123611100.00
CONT_ASSIGN123711100.00
CONT_ASSIGN123911100.00
CONT_ASSIGN124011100.00
CONT_ASSIGN124111100.00
CONT_ASSIGN124311100.00
CONT_ASSIGN124511100.00
CONT_ASSIGN124611100.00
CONT_ASSIGN124711100.00
CONT_ASSIGN124911100.00
CONT_ASSIGN125011100.00
CONT_ASSIGN125111100.00
CONT_ASSIGN125311100.00
CONT_ASSIGN125411100.00
CONT_ASSIGN125511100.00
CONT_ASSIGN125711100.00
CONT_ASSIGN125811100.00
CONT_ASSIGN125911100.00
CONT_ASSIGN126111100.00
CONT_ASSIGN126211100.00
CONT_ASSIGN126311100.00
CONT_ASSIGN126511100.00
CONT_ASSIGN126611100.00
CONT_ASSIGN126711100.00
CONT_ASSIGN126911100.00
CONT_ASSIGN127011100.00
CONT_ASSIGN127111100.00
CONT_ASSIGN127211100.00
CONT_ASSIGN127311100.00
CONT_ASSIGN127411100.00
CONT_ASSIGN127511100.00
CONT_ASSIGN127611100.00
CONT_ASSIGN127711100.00
CONT_ASSIGN127811100.00
CONT_ASSIGN127911100.00
CONT_ASSIGN128011100.00
CONT_ASSIGN128111100.00
CONT_ASSIGN128211100.00
CONT_ASSIGN128311100.00
CONT_ASSIGN128411100.00
CONT_ASSIGN128511100.00
CONT_ASSIGN128611100.00
CONT_ASSIGN128711100.00
CONT_ASSIGN128811100.00
CONT_ASSIGN128911100.00
CONT_ASSIGN129011100.00
CONT_ASSIGN129111100.00
ALWAYS12953636100.00
ALWAYS13355353100.00
CONT_ASSIGN150400
CONT_ASSIGN151211100.00
CONT_ASSIGN151311100.00

Click here to see the source line report.

Cond Coverage for Instance : tb.dut.u_reg
TotalCoveredPercent
Conditions43242197.45
Logical43242197.45
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1232100.00
1233-129192.95

Branch Coverage for Instance : tb.dut.u_reg
Line No.TotalCoveredPercent
Branches 41 41 100.00
TERNARY 1178 2 2 100.00
IF 68 3 3 100.00
CASE 1336 36 36 100.00


1178 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


68 if (!rst_ni) begin -1- 69 err_q <= '0; ==> 70 end else if (intg_err || reg_we_err) begin -2- 71 err_q <= 1'b1; ==> 72 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T91,T87,T73
0 0 Covered T1,T2,T3


1336 unique case (1'b1) -1- 1337 addr_hit[0]: begin 1338 reg_rdata_next[0] = '0; ==> 1339 reg_rdata_next[1] = '0; 1340 reg_rdata_next[2] = '0; 1341 end 1342 1343 addr_hit[1]: begin 1344 reg_rdata_next[0] = status_initialized_qs; ==> 1345 reg_rdata_next[1] = status_ready_qs; 1346 reg_rdata_next[2] = status_ext_clock_switched_qs; 1347 reg_rdata_next[3] = status_transition_successful_qs; 1348 reg_rdata_next[4] = status_transition_count_error_qs; 1349 reg_rdata_next[5] = status_transition_error_qs; 1350 reg_rdata_next[6] = status_token_error_qs; 1351 reg_rdata_next[7] = status_flash_rma_error_qs; 1352 reg_rdata_next[8] = status_otp_error_qs; 1353 reg_rdata_next[9] = status_state_error_qs; 1354 reg_rdata_next[10] = status_bus_integ_error_qs; 1355 reg_rdata_next[11] = status_otp_partition_error_qs; 1356 end 1357 1358 addr_hit[2]: begin 1359 reg_rdata_next[0] = claim_transition_if_regwen_qs; ==> 1360 end 1361 1362 addr_hit[3]: begin 1363 reg_rdata_next[7:0] = claim_transition_if_qs; ==> 1364 end 1365 1366 addr_hit[4]: begin 1367 reg_rdata_next[0] = transition_regwen_qs; ==> 1368 end 1369 1370 addr_hit[5]: begin 1371 reg_rdata_next[0] = '0; ==> 1372 end 1373 1374 addr_hit[6]: begin 1375 reg_rdata_next[0] = transition_ctrl_ext_clock_en_qs; ==> 1376 reg_rdata_next[1] = transition_ctrl_volatile_raw_unlock_qs; 1377 end 1378 1379 addr_hit[7]: begin 1380 reg_rdata_next[31:0] = transition_token_0_qs; ==> 1381 end 1382 1383 addr_hit[8]: begin 1384 reg_rdata_next[31:0] = transition_token_1_qs; ==> 1385 end 1386 1387 addr_hit[9]: begin 1388 reg_rdata_next[31:0] = transition_token_2_qs; ==> 1389 end 1390 1391 addr_hit[10]: begin 1392 reg_rdata_next[31:0] = transition_token_3_qs; ==> 1393 end 1394 1395 addr_hit[11]: begin 1396 reg_rdata_next[29:0] = transition_target_qs; ==> 1397 end 1398 1399 addr_hit[12]: begin 1400 reg_rdata_next[31:0] = otp_vendor_test_ctrl_qs; ==> 1401 end 1402 1403 addr_hit[13]: begin 1404 reg_rdata_next[31:0] = otp_vendor_test_status_qs; ==> 1405 end 1406 1407 addr_hit[14]: begin 1408 reg_rdata_next[29:0] = lc_state_qs; ==> 1409 end 1410 1411 addr_hit[15]: begin 1412 reg_rdata_next[4:0] = lc_transition_cnt_qs; ==> 1413 end 1414 1415 addr_hit[16]: begin 1416 reg_rdata_next[31:0] = lc_id_state_qs; ==> 1417 end 1418 1419 addr_hit[17]: begin 1420 reg_rdata_next[15:0] = hw_revision0_product_id_qs; ==> 1421 reg_rdata_next[31:16] = hw_revision0_silicon_creator_id_qs; 1422 end 1423 1424 addr_hit[18]: begin 1425 reg_rdata_next[7:0] = hw_revision1_revision_id_qs; ==> 1426 reg_rdata_next[31:8] = hw_revision1_reserved_qs; 1427 end 1428 1429 addr_hit[19]: begin 1430 reg_rdata_next[31:0] = device_id_0_qs; ==> 1431 end 1432 1433 addr_hit[20]: begin 1434 reg_rdata_next[31:0] = device_id_1_qs; ==> 1435 end 1436 1437 addr_hit[21]: begin 1438 reg_rdata_next[31:0] = device_id_2_qs; ==> 1439 end 1440 1441 addr_hit[22]: begin 1442 reg_rdata_next[31:0] = device_id_3_qs; ==> 1443 end 1444 1445 addr_hit[23]: begin 1446 reg_rdata_next[31:0] = device_id_4_qs; ==> 1447 end 1448 1449 addr_hit[24]: begin 1450 reg_rdata_next[31:0] = device_id_5_qs; ==> 1451 end 1452 1453 addr_hit[25]: begin 1454 reg_rdata_next[31:0] = device_id_6_qs; ==> 1455 end 1456 1457 addr_hit[26]: begin 1458 reg_rdata_next[31:0] = device_id_7_qs; ==> 1459 end 1460 1461 addr_hit[27]: begin 1462 reg_rdata_next[31:0] = manuf_state_0_qs; ==> 1463 end 1464 1465 addr_hit[28]: begin 1466 reg_rdata_next[31:0] = manuf_state_1_qs; ==> 1467 end 1468 1469 addr_hit[29]: begin 1470 reg_rdata_next[31:0] = manuf_state_2_qs; ==> 1471 end 1472 1473 addr_hit[30]: begin 1474 reg_rdata_next[31:0] = manuf_state_3_qs; ==> 1475 end 1476 1477 addr_hit[31]: begin 1478 reg_rdata_next[31:0] = manuf_state_4_qs; ==> 1479 end 1480 1481 addr_hit[32]: begin 1482 reg_rdata_next[31:0] = manuf_state_5_qs; ==> 1483 end 1484 1485 addr_hit[33]: begin 1486 reg_rdata_next[31:0] = manuf_state_6_qs; ==> 1487 end 1488 1489 addr_hit[34]: begin 1490 reg_rdata_next[31:0] = manuf_state_7_qs; ==> 1491 end 1492 1493 default: begin 1494 reg_rdata_next = '1; ==>

Branches:
-1-StatusTests
addr_hit[0] Covered T2,T3,T12
addr_hit[1] Covered T1,T2,T12
addr_hit[2] Covered T2,T12,T13
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T12
addr_hit[6] Covered T1,T2,T12
addr_hit[7] Covered T1,T2,T12
addr_hit[8] Covered T1,T2,T12
addr_hit[9] Covered T1,T2,T12
addr_hit[10] Covered T1,T2,T12
addr_hit[11] Covered T1,T2,T12
addr_hit[12] Covered T2,T12,T13
addr_hit[13] Covered T2,T12,T13
addr_hit[14] Covered T1,T2,T12
addr_hit[15] Covered T1,T2,T12
addr_hit[16] Covered T2,T12,T13
addr_hit[17] Covered T1,T2,T12
addr_hit[18] Covered T1,T2,T12
addr_hit[19] Covered T2,T12,T13
addr_hit[20] Covered T1,T2,T12
addr_hit[21] Covered T2,T12,T13
addr_hit[22] Covered T2,T12,T13
addr_hit[23] Covered T2,T12,T13
addr_hit[24] Covered T1,T2,T12
addr_hit[25] Covered T1,T2,T12
addr_hit[26] Covered T2,T12,T13
addr_hit[27] Covered T2,T12,T13
addr_hit[28] Covered T1,T2,T12
addr_hit[29] Covered T2,T3,T12
addr_hit[30] Covered T1,T2,T12
addr_hit[31] Covered T1,T2,T12
addr_hit[32] Covered T1,T2,T12
addr_hit[33] Covered T1,T2,T12
addr_hit[34] Covered T1,T2,T12
default Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 60264275 1726767 0 0
reAfterRv 60264275 1726766 0 0
rePulse 60264275 1445153 0 0
wePulse 60264275 281613 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 60264275 1726767 0 0
T1 1059 59 0 0
T2 2661 418 0 0
T3 1066 3 0 0
T4 31121 0 0 0
T5 3571 154 0 0
T6 7859 68 0 0
T7 12360 112 0 0
T8 0 116 0 0
T11 29727 0 0 0
T12 1274 20 0 0
T13 1016 7 0 0
T22 0 3 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 60264275 1726766 0 0
T1 1059 59 0 0
T2 2661 418 0 0
T3 1066 3 0 0
T4 31121 0 0 0
T5 3571 154 0 0
T6 7859 68 0 0
T7 12360 112 0 0
T8 0 116 0 0
T11 29727 0 0 0
T12 1274 20 0 0
T13 1016 7 0 0
T22 0 3 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 60264275 1445153 0 0
T1 1059 43 0 0
T2 2661 298 0 0
T3 1066 2 0 0
T4 31121 0 0 0
T5 3571 98 0 0
T6 7859 35 0 0
T7 12360 61 0 0
T8 0 59 0 0
T11 29727 0 0 0
T12 1274 5 0 0
T13 1016 0 0 0
T15 0 152 0 0
T22 0 2 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 60264275 281613 0 0
T1 1059 16 0 0
T2 2661 120 0 0
T3 1066 1 0 0
T4 31121 0 0 0
T5 3571 56 0 0
T6 7859 33 0 0
T7 12360 51 0 0
T8 0 57 0 0
T11 29727 0 0 0
T12 1274 15 0 0
T13 1016 7 0 0
T22 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg_tap
Line No.TotalCoveredPercent
TOTAL227227100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN23311100.00
CONT_ASSIGN24811100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49911100.00
CONT_ASSIGN51311100.00
CONT_ASSIGN53511100.00
CONT_ASSIGN53811100.00
CONT_ASSIGN55211100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN56111100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN59211100.00
CONT_ASSIGN59911100.00
CONT_ASSIGN60211100.00
CONT_ASSIGN61611100.00
CONT_ASSIGN62311100.00
CONT_ASSIGN62611100.00
CONT_ASSIGN64011100.00
CONT_ASSIGN64711100.00
CONT_ASSIGN65011100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN67111100.00
CONT_ASSIGN67411100.00
CONT_ASSIGN68811100.00
CONT_ASSIGN69411100.00
CONT_ASSIGN69711100.00
CONT_ASSIGN71111100.00
CONT_ASSIGN71711100.00
CONT_ASSIGN72011100.00
CONT_ASSIGN73411100.00
ALWAYS11403636100.00
CONT_ASSIGN117811100.00
ALWAYS118211100.00
CONT_ASSIGN122111100.00
CONT_ASSIGN122311100.00
CONT_ASSIGN122511100.00
CONT_ASSIGN122711100.00
CONT_ASSIGN122811100.00
CONT_ASSIGN122911100.00
CONT_ASSIGN123111100.00
CONT_ASSIGN123211100.00
CONT_ASSIGN123311100.00
CONT_ASSIGN123511100.00
CONT_ASSIGN123611100.00
CONT_ASSIGN123711100.00
CONT_ASSIGN123911100.00
CONT_ASSIGN124011100.00
CONT_ASSIGN124111100.00
CONT_ASSIGN124311100.00
CONT_ASSIGN124511100.00
CONT_ASSIGN124611100.00
CONT_ASSIGN124711100.00
CONT_ASSIGN124911100.00
CONT_ASSIGN125011100.00
CONT_ASSIGN125111100.00
CONT_ASSIGN125311100.00
CONT_ASSIGN125411100.00
CONT_ASSIGN125511100.00
CONT_ASSIGN125711100.00
CONT_ASSIGN125811100.00
CONT_ASSIGN125911100.00
CONT_ASSIGN126111100.00
CONT_ASSIGN126211100.00
CONT_ASSIGN126311100.00
CONT_ASSIGN126511100.00
CONT_ASSIGN126611100.00
CONT_ASSIGN126711100.00
CONT_ASSIGN126911100.00
CONT_ASSIGN127011100.00
CONT_ASSIGN127111100.00
CONT_ASSIGN127211100.00
CONT_ASSIGN127311100.00
CONT_ASSIGN127411100.00
CONT_ASSIGN127511100.00
CONT_ASSIGN127611100.00
CONT_ASSIGN127711100.00
CONT_ASSIGN127811100.00
CONT_ASSIGN127911100.00
CONT_ASSIGN128011100.00
CONT_ASSIGN128111100.00
CONT_ASSIGN128211100.00
CONT_ASSIGN128311100.00
CONT_ASSIGN128411100.00
CONT_ASSIGN128511100.00
CONT_ASSIGN128611100.00
CONT_ASSIGN128711100.00
CONT_ASSIGN128811100.00
CONT_ASSIGN128911100.00
CONT_ASSIGN129011100.00
CONT_ASSIGN129111100.00
ALWAYS12953636100.00
ALWAYS13355353100.00
CONT_ASSIGN150400
CONT_ASSIGN151211100.00
CONT_ASSIGN151311100.00

Click here to see the source line report.

Cond Coverage for Instance : tb.dut.u_reg_tap
TotalCoveredPercent
Conditions27827598.92
Logical27827598.92
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-127698.71
1277-1291100.00

Branch Coverage for Instance : tb.dut.u_reg_tap
Line No.TotalCoveredPercent
Branches 41 41 100.00
TERNARY 1178 2 2 100.00
IF 68 3 3 100.00
CASE 1336 36 36 100.00


1178 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T4,T6,T7
0 Covered T1,T2,T3


68 if (!rst_ni) begin -1- 69 err_q <= '0; ==> 70 end else if (intg_err || reg_we_err) begin -2- 71 err_q <= 1'b1; ==> 72 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T91,T87,T73
0 0 Covered T1,T2,T3


1336 unique case (1'b1) -1- 1337 addr_hit[0]: begin 1338 reg_rdata_next[0] = '0; ==> 1339 reg_rdata_next[1] = '0; 1340 reg_rdata_next[2] = '0; 1341 end 1342 1343 addr_hit[1]: begin 1344 reg_rdata_next[0] = status_initialized_qs; ==> 1345 reg_rdata_next[1] = status_ready_qs; 1346 reg_rdata_next[2] = status_ext_clock_switched_qs; 1347 reg_rdata_next[3] = status_transition_successful_qs; 1348 reg_rdata_next[4] = status_transition_count_error_qs; 1349 reg_rdata_next[5] = status_transition_error_qs; 1350 reg_rdata_next[6] = status_token_error_qs; 1351 reg_rdata_next[7] = status_flash_rma_error_qs; 1352 reg_rdata_next[8] = status_otp_error_qs; 1353 reg_rdata_next[9] = status_state_error_qs; 1354 reg_rdata_next[10] = status_bus_integ_error_qs; 1355 reg_rdata_next[11] = status_otp_partition_error_qs; 1356 end 1357 1358 addr_hit[2]: begin 1359 reg_rdata_next[0] = claim_transition_if_regwen_qs; ==> 1360 end 1361 1362 addr_hit[3]: begin 1363 reg_rdata_next[7:0] = claim_transition_if_qs; ==> 1364 end 1365 1366 addr_hit[4]: begin 1367 reg_rdata_next[0] = transition_regwen_qs; ==> 1368 end 1369 1370 addr_hit[5]: begin 1371 reg_rdata_next[0] = '0; ==> 1372 end 1373 1374 addr_hit[6]: begin 1375 reg_rdata_next[0] = transition_ctrl_ext_clock_en_qs; ==> 1376 reg_rdata_next[1] = transition_ctrl_volatile_raw_unlock_qs; 1377 end 1378 1379 addr_hit[7]: begin 1380 reg_rdata_next[31:0] = transition_token_0_qs; ==> 1381 end 1382 1383 addr_hit[8]: begin 1384 reg_rdata_next[31:0] = transition_token_1_qs; ==> 1385 end 1386 1387 addr_hit[9]: begin 1388 reg_rdata_next[31:0] = transition_token_2_qs; ==> 1389 end 1390 1391 addr_hit[10]: begin 1392 reg_rdata_next[31:0] = transition_token_3_qs; ==> 1393 end 1394 1395 addr_hit[11]: begin 1396 reg_rdata_next[29:0] = transition_target_qs; ==> 1397 end 1398 1399 addr_hit[12]: begin 1400 reg_rdata_next[31:0] = otp_vendor_test_ctrl_qs; ==> 1401 end 1402 1403 addr_hit[13]: begin 1404 reg_rdata_next[31:0] = otp_vendor_test_status_qs; ==> 1405 end 1406 1407 addr_hit[14]: begin 1408 reg_rdata_next[29:0] = lc_state_qs; ==> 1409 end 1410 1411 addr_hit[15]: begin 1412 reg_rdata_next[4:0] = lc_transition_cnt_qs; ==> 1413 end 1414 1415 addr_hit[16]: begin 1416 reg_rdata_next[31:0] = lc_id_state_qs; ==> 1417 end 1418 1419 addr_hit[17]: begin 1420 reg_rdata_next[15:0] = hw_revision0_product_id_qs; ==> 1421 reg_rdata_next[31:16] = hw_revision0_silicon_creator_id_qs; 1422 end 1423 1424 addr_hit[18]: begin 1425 reg_rdata_next[7:0] = hw_revision1_revision_id_qs; ==> 1426 reg_rdata_next[31:8] = hw_revision1_reserved_qs; 1427 end 1428 1429 addr_hit[19]: begin 1430 reg_rdata_next[31:0] = device_id_0_qs; ==> 1431 end 1432 1433 addr_hit[20]: begin 1434 reg_rdata_next[31:0] = device_id_1_qs; ==> 1435 end 1436 1437 addr_hit[21]: begin 1438 reg_rdata_next[31:0] = device_id_2_qs; ==> 1439 end 1440 1441 addr_hit[22]: begin 1442 reg_rdata_next[31:0] = device_id_3_qs; ==> 1443 end 1444 1445 addr_hit[23]: begin 1446 reg_rdata_next[31:0] = device_id_4_qs; ==> 1447 end 1448 1449 addr_hit[24]: begin 1450 reg_rdata_next[31:0] = device_id_5_qs; ==> 1451 end 1452 1453 addr_hit[25]: begin 1454 reg_rdata_next[31:0] = device_id_6_qs; ==> 1455 end 1456 1457 addr_hit[26]: begin 1458 reg_rdata_next[31:0] = device_id_7_qs; ==> 1459 end 1460 1461 addr_hit[27]: begin 1462 reg_rdata_next[31:0] = manuf_state_0_qs; ==> 1463 end 1464 1465 addr_hit[28]: begin 1466 reg_rdata_next[31:0] = manuf_state_1_qs; ==> 1467 end 1468 1469 addr_hit[29]: begin 1470 reg_rdata_next[31:0] = manuf_state_2_qs; ==> 1471 end 1472 1473 addr_hit[30]: begin 1474 reg_rdata_next[31:0] = manuf_state_3_qs; ==> 1475 end 1476 1477 addr_hit[31]: begin 1478 reg_rdata_next[31:0] = manuf_state_4_qs; ==> 1479 end 1480 1481 addr_hit[32]: begin 1482 reg_rdata_next[31:0] = manuf_state_5_qs; ==> 1483 end 1484 1485 addr_hit[33]: begin 1486 reg_rdata_next[31:0] = manuf_state_6_qs; ==> 1487 end 1488 1489 addr_hit[34]: begin 1490 reg_rdata_next[31:0] = manuf_state_7_qs; ==> 1491 end 1492 1493 default: begin 1494 reg_rdata_next = '1; ==>

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
addr_hit[21] Covered T1,T2,T3
addr_hit[22] Covered T1,T2,T3
addr_hit[23] Covered T1,T2,T3
addr_hit[24] Covered T1,T2,T3
addr_hit[25] Covered T1,T2,T3
addr_hit[26] Covered T1,T2,T3
addr_hit[27] Covered T1,T2,T3
addr_hit[28] Covered T1,T2,T3
addr_hit[29] Covered T1,T2,T3
addr_hit[30] Covered T1,T2,T3
addr_hit[31] Covered T1,T2,T3
addr_hit[32] Covered T1,T2,T3
addr_hit[33] Covered T1,T2,T3
addr_hit[34] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg_tap
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 60264275 218751 0 0
reAfterRv 60264275 218751 0 0
rePulse 60264275 129650 0 0
wePulse 60264275 89101 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 60264275 218751 0 0
T4 31121 251 0 0
T5 3571 0 0 0
T6 7859 68 0 0
T7 12360 106 0 0
T8 17991 116 0 0
T9 0 274 0 0
T11 29727 267 0 0
T14 16415 65 0 0
T15 5970 0 0 0
T16 6146 0 0 0
T19 0 136 0 0
T20 0 118 0 0
T21 0 876 0 0
T22 981 0 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 60264275 218751 0 0
T4 31121 251 0 0
T5 3571 0 0 0
T6 7859 68 0 0
T7 12360 106 0 0
T8 17991 116 0 0
T9 0 274 0 0
T11 29727 267 0 0
T14 16415 65 0 0
T15 5970 0 0 0
T16 6146 0 0 0
T19 0 136 0 0
T20 0 118 0 0
T21 0 876 0 0
T22 981 0 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 60264275 129650 0 0
T4 31121 131 0 0
T5 3571 0 0 0
T6 7859 35 0 0
T7 12360 58 0 0
T8 17991 59 0 0
T9 0 150 0 0
T11 29727 123 0 0
T14 16415 41 0 0
T15 5970 0 0 0
T16 6146 0 0 0
T19 0 60 0 0
T20 0 56 0 0
T21 0 444 0 0
T22 981 0 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 60264275 89101 0 0
T4 31121 120 0 0
T5 3571 0 0 0
T6 7859 33 0 0
T7 12360 48 0 0
T8 17991 57 0 0
T9 0 124 0 0
T11 29727 144 0 0
T14 16415 24 0 0
T15 5970 0 0 0
T16 6146 0 0 0
T19 0 76 0 0
T20 0 62 0 0
T21 0 432 0 0
T22 981 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%