Unified Coverage Report :: Module :: lc_ctrl_signal_decode

Module : lc_ctrl_signal_decode

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.69	98.41				91.67	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode	96.69	98.41				91.67	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.69	98.41				91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.86	99.21				97.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.10	98.87	93.02		100.00	98.63	100.00	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_flop_keymgr_div	100.00	100.00				100.00
u_prim_lc_sender_cpu_en	100.00	100.00				100.00
u_prim_lc_sender_creator_seed_sw_rw_en	100.00	100.00				100.00
u_prim_lc_sender_dft_en	100.00	100.00				100.00
u_prim_lc_sender_escalate_en	100.00	100.00				100.00
u_prim_lc_sender_hw_debug_en	100.00	100.00				100.00
u_prim_lc_sender_iso_part_sw_rd_en	100.00	100.00				100.00
u_prim_lc_sender_iso_part_sw_wr_en	100.00	100.00				100.00
u_prim_lc_sender_keymgr_en	100.00	100.00				100.00
u_prim_lc_sender_nvm_debug_en	100.00	100.00				100.00
u_prim_lc_sender_owner_seed_sw_rw_en	100.00	100.00				100.00
u_prim_lc_sender_raw_test_rma	100.00	100.00				100.00
u_prim_lc_sender_seed_hw_rd_en	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : lc_ctrl_signal_decode

	Line No.	Total	Covered	Percent
TOTAL		63	62	98.41
ALWAYS	60	62	61	98.39
CONT_ASSIGN	296	1	1	100.00

59                          // Life cycle control signal defaults
60         1/1              lc_raw_test_rma          = Off;
           Tests:       T1 T2 T3 
61         1/1              lc_dft_en                = Off;
           Tests:       T1 T2 T3 
62         1/1              lc_nvm_debug_en          = Off;
           Tests:       T1 T2 T3 
63         1/1              lc_hw_debug_en           = Off;
           Tests:       T1 T2 T3 
64         1/1              lc_cpu_en                = Off;
           Tests:       T1 T2 T3 
65         1/1              lc_creator_seed_sw_rw_en = Off;
           Tests:       T1 T2 T3 
66         1/1              lc_owner_seed_sw_rw_en   = Off;
           Tests:       T1 T2 T3 
67         1/1              lc_iso_part_sw_rd_en     = Off;
           Tests:       T1 T2 T3 
68         1/1              lc_iso_part_sw_wr_en     = Off;
           Tests:       T1 T2 T3 
69         1/1              lc_seed_hw_rd_en         = Off;
           Tests:       T1 T2 T3 
70         1/1              lc_keymgr_en             = Off;
           Tests:       T1 T2 T3 
71                          // This ensures that once escalation has been triggered, it cannot go back to Off.
72         1/1              lc_escalate_en           = lc_tx_or_hi(Off, lc_escalate_en_o);
           Tests:       T1 T2 T3 
73                          // Set to invalid diversification value by default.
74         1/1              lc_keymgr_div_d          = RndCnstLcKeymgrDivInvalid;
           Tests:       T1 T2 T3 
75                      
76         1/1              unique case (fsm_state_i)
           Tests:       T1 T2 T3 
77                            ///////////////////////////////////////////////////////////////////
78                            // Don't broadcast anything in this state.
79         1/1                ResetSt: ;
           Tests:       T1 T2 T3 
80                            ///////////////////////////////////////////////////////////////////
81                            // Broadcasting of most signals is only enabled during the following life cycle states.
82                            IdleSt,
83                            ClkMuxSt,
84                            CntIncrSt,
85                            CntProgSt,
86                            TransCheckSt,
87                            FlashRmaSt,
88                            TokenHashSt,
89                            TokenCheck0St,
90                            TokenCheck1St,
91                            TransProgSt: begin
92         1/1                  if (lc_state_valid_i) begin
           Tests:       T1 T2 T3 
93         1/1                    unique case (lc_state_i)
           Tests:       T1 T2 T3 
94                                  ///////////////////////////////////////////////////////////////////
95                                  // Only enable life cycle TAP register for OTP test mechanisms.
96                                  LcStRaw,
97                                  LcStTestLocked0,
98                                  LcStTestLocked1,
99                                  LcStTestLocked2,
100                                 LcStTestLocked3,
101                                 LcStTestLocked4,
102                                 LcStTestLocked5,
103                                 LcStTestLocked6: begin
104        1/1                        lc_raw_test_rma = On;
           Tests:       T1 T2 T12 
105                                 end
106                                 ///////////////////////////////////////////////////////////////////
107                                 // Enable DFT and debug functionality, including the CPU in the
108                                 // test unlocked states.
109                                 LcStTestUnlocked0,
110                                 LcStTestUnlocked1,
111                                 LcStTestUnlocked2,
112                                 LcStTestUnlocked3,
113                                 LcStTestUnlocked4,
114                                 LcStTestUnlocked5,
115                                 LcStTestUnlocked6: begin
116        1/1                        lc_raw_test_rma      = On;
           Tests:       T1 T2 T3 
117        1/1                        lc_dft_en            = On;
           Tests:       T1 T2 T3 
118        1/1                        lc_nvm_debug_en      = On;
           Tests:       T1 T2 T3 
119        1/1                        lc_hw_debug_en       = On;
           Tests:       T1 T2 T3 
120        1/1                        lc_cpu_en            = On;
           Tests:       T1 T2 T3 
121        1/1                        lc_iso_part_sw_wr_en = On;
           Tests:       T1 T2 T3 
122        1/1                        lc_keymgr_div_d      = RndCnstLcKeymgrDivTestUnlocked;
           Tests:       T1 T2 T3 
123                                 end
124                                 ///////////////////////////////////////////////////////////////////
125                                 // This is the last TEST_UNLOCKED state. The same feature set is enabled
126                                 // as in the other TEST_UNLOCKED states above, except for NVM debug en,
127                                 // which is disabled in this state.
128                                 LcStTestUnlocked7: begin
129        1/1                        lc_raw_test_rma      = On;
           Tests:       T4 T14 T15 
130        1/1                        lc_dft_en            = On;
           Tests:       T4 T14 T15 
131        1/1                        lc_hw_debug_en       = On;
           Tests:       T4 T14 T15 
132        1/1                        lc_cpu_en            = On;
           Tests:       T4 T14 T15 
133        1/1                        lc_iso_part_sw_wr_en = On;
           Tests:       T4 T14 T15 
134        1/1                        lc_keymgr_div_d      = RndCnstLcKeymgrDivTestUnlocked;
           Tests:       T4 T14 T15 
135                                 end
136                                 ///////////////////////////////////////////////////////////////////
137                                 // Enable production functions
138                                 LcStProd,
139                                 LcStProdEnd: begin
140        1/1                        lc_cpu_en              = On;
           Tests:       T2 T4 T5 
141        1/1                        lc_keymgr_en           = On;
           Tests:       T2 T4 T5 
142        1/1                        lc_owner_seed_sw_rw_en = On;
           Tests:       T2 T4 T5 
143        1/1                        lc_iso_part_sw_wr_en   = On;
           Tests:       T2 T4 T5 
144        1/1                        lc_iso_part_sw_rd_en   = On;
           Tests:       T2 T4 T5 
145        1/1                        lc_keymgr_div_d        = RndCnstLcKeymgrDivProduction;
           Tests:       T2 T4 T5 
146                                   // Only allow provisioning if the device has not yet been personalized.
147                                   // If secrets_valid_i is set to ON, we output OFF.
148                                   // Note that we can convert ON to OFF with a bitwise inversion due to the encoding.
149        1/1                        lc_creator_seed_sw_rw_en = lc_tx_t'(~secrets_valid_i);
           Tests:       T2 T4 T5 
150                                   // Only allow hardware to consume the seeds once personalized.
151                                   // If secrets_valid_i is set to ON, we output ON.
152        1/1                        lc_seed_hw_rd_en = secrets_valid_i;
           Tests:       T2 T4 T5 
153                                 end
154                                 ///////////////////////////////////////////////////////////////////
155                                 // Similar functions as PROD, with the following differences:
156                                 // - hardware debug functionality (CPU TAP) is enabled,
157                                 // - access to the isolated flash partition is disabled.
158                                 LcStDev: begin
159        1/1                        lc_hw_debug_en         = On;
           Tests:       T2 T4 T18 
160        1/1                        lc_cpu_en              = On;
           Tests:       T2 T4 T18 
161        1/1                        lc_keymgr_en           = On;
           Tests:       T2 T4 T18 
162        1/1                        lc_owner_seed_sw_rw_en = On;
           Tests:       T2 T4 T18 
163        1/1                        lc_iso_part_sw_wr_en   = On;
           Tests:       T2 T4 T18 
164        1/1                        lc_keymgr_div_d        = RndCnstLcKeymgrDivDev;
           Tests:       T2 T4 T18 
165                                   // Only allow provisioning if the device has not yet been personalized.
166                                   // If secrets_valid_i is set to ON, we output OFF.
167                                   // Note that we can convert ON to OFF with a bitwise inversion due to the encoding.
168        1/1                        lc_creator_seed_sw_rw_en = lc_tx_t'(~secrets_valid_i);
           Tests:       T2 T4 T18 
169                                   // Only allow hardware to consume the seeds once personalized.
170                                   // If secrets_valid_i is set to ON, we output ON.
171        1/1                        lc_seed_hw_rd_en = secrets_valid_i;
           Tests:       T2 T4 T18 
172                                 end
173                                 ///////////////////////////////////////////////////////////////////
174                                 // Enable all test and production functions.
175                                 LcStRma: begin
176        1/1                        lc_raw_test_rma          = On;
           Tests:       T11 T18 T19 
177        1/1                        lc_dft_en                = On;
           Tests:       T11 T18 T19 
178        1/1                        lc_nvm_debug_en          = On;
           Tests:       T11 T18 T19 
179        1/1                        lc_hw_debug_en           = On;
           Tests:       T11 T18 T19 
180        1/1                        lc_cpu_en                = On;
           Tests:       T11 T18 T19 
181        1/1                        lc_keymgr_en             = On;
           Tests:       T11 T18 T19 
182        1/1                        lc_creator_seed_sw_rw_en = On;
           Tests:       T11 T18 T19 
183        1/1                        lc_owner_seed_sw_rw_en   = On;
           Tests:       T11 T18 T19 
184        1/1                        lc_iso_part_sw_wr_en     = On;
           Tests:       T11 T18 T19 
185        1/1                        lc_iso_part_sw_rd_en     = On;
           Tests:       T11 T18 T19 
186        1/1                        lc_seed_hw_rd_en         = On;
           Tests:       T11 T18 T19 
187        1/1                        lc_keymgr_div_d          = RndCnstLcKeymgrDivRma;
           Tests:       T11 T18 T19 
188                                 end
189                                 ///////////////////////////////////////////////////////////////////
190                                 // Invalid or scrapped life cycle state, make sure the escalation
191                                 // signal is also asserted in this case.
192                                 default: begin
193                                   lc_escalate_en = On;
194                                 end
195                               endcase // lc_state_i
196                             end else begin
197        0/1     ==>            lc_escalate_en = On;
198                             end
199                           end
200                           ///////////////////////////////////////////////////////////////////
201                           // Post-transition state. Behaves similarly to the virtual scrap
202                           // states below, with the exception that escalate_en is NOT asserted,
203                           // since that could trigger unwanted alerts / escalations and system resets.
204        1/1                PostTransSt: ;
           Tests:       T1 T2 T12 
205                           ///////////////////////////////////////////////////////////////////
206                           // Virtual scrap states, make sure the escalation signal is
207                           // also asserted in this case.
208                           ScrapSt,
209                           EscalateSt,
210                           InvalidSt: begin
211        1/1                  lc_escalate_en = On;
           Tests:       T4 T5 T11 
212                           end
213                           default: begin
214                             lc_escalate_en = On;
215                           end
216                         endcase // fsm_state_i
217                       end
218                     
219                       /////////////////////////////////
220                       // Control signal output flops //
221                       /////////////////////////////////
222                     
223                       prim_lc_sender u_prim_lc_sender_raw_test_rma (
224                         .clk_i,
225                         .rst_ni,
226                         .lc_en_i(lc_raw_test_rma),
227                         .lc_en_o(lc_raw_test_rma_o)
228                       );
229                       prim_lc_sender u_prim_lc_sender_dft_en (
230                         .clk_i,
231                         .rst_ni,
232                         .lc_en_i(lc_dft_en),
233                         .lc_en_o(lc_dft_en_o)
234                       );
235                       prim_lc_sender u_prim_lc_sender_nvm_debug_en (
236                         .clk_i,
237                         .rst_ni,
238                         .lc_en_i(lc_nvm_debug_en),
239                         .lc_en_o(lc_nvm_debug_en_o)
240                       );
241                       prim_lc_sender u_prim_lc_sender_hw_debug_en (
242                         .clk_i,
243                         .rst_ni,
244                         .lc_en_i(lc_hw_debug_en),
245                         .lc_en_o(lc_hw_debug_en_o)
246                       );
247                       prim_lc_sender u_prim_lc_sender_cpu_en (
248                         .clk_i,
249                         .rst_ni,
250                         .lc_en_i(lc_cpu_en),
251                         .lc_en_o(lc_cpu_en_o)
252                       );
253                       prim_lc_sender u_prim_lc_sender_creator_seed_sw_rw_en (
254                         .clk_i,
255                         .rst_ni,
256                         .lc_en_i(lc_creator_seed_sw_rw_en),
257                         .lc_en_o(lc_creator_seed_sw_rw_en_o)
258                       );
259                       prim_lc_sender u_prim_lc_sender_owner_seed_sw_rw_en (
260                         .clk_i,
261                         .rst_ni,
262                         .lc_en_i(lc_owner_seed_sw_rw_en),
263                         .lc_en_o(lc_owner_seed_sw_rw_en_o)
264                       );
265                       prim_lc_sender u_prim_lc_sender_iso_part_sw_rd_en (
266                         .clk_i,
267                         .rst_ni,
268                         .lc_en_i(lc_iso_part_sw_rd_en),
269                         .lc_en_o(lc_iso_part_sw_rd_en_o)
270                       );
271                       prim_lc_sender u_prim_lc_sender_iso_part_sw_wr_en (
272                         .clk_i,
273                         .rst_ni,
274                         .lc_en_i(lc_iso_part_sw_wr_en),
275                         .lc_en_o(lc_iso_part_sw_wr_en_o)
276                       );
277                       prim_lc_sender u_prim_lc_sender_seed_hw_rd_en (
278                         .clk_i,
279                         .rst_ni,
280                         .lc_en_i(lc_seed_hw_rd_en),
281                         .lc_en_o(lc_seed_hw_rd_en_o)
282                       );
283                       prim_lc_sender u_prim_lc_sender_keymgr_en (
284                         .clk_i,
285                         .rst_ni,
286                         .lc_en_i(lc_keymgr_en),
287                         .lc_en_o(lc_keymgr_en_o)
288                       );
289                       prim_lc_sender u_prim_lc_sender_escalate_en (
290                         .clk_i,
291                         .rst_ni,
292                         .lc_en_i(lc_escalate_en),
293                         .lc_en_o(lc_escalate_en_o)
294                       );
295                     
296        1/1            assign lc_keymgr_div_o = lc_keymgr_div_q;
           Tests:       T1 T2 T3 

---

Branch Coverage for Module : lc_ctrl_signal_decode

	Line No.	Total	Covered	Percent
Branches		12	11	91.67
CASE	76	12	11	91.67

76             unique case (fsm_state_i)
                      -1-  
77               ///////////////////////////////////////////////////////////////////
78               // Don't broadcast anything in this state.
79               ResetSt: ;
                 ==>
80               ///////////////////////////////////////////////////////////////////
81               // Broadcasting of most signals is only enabled during the following life cycle states.
82               IdleSt,
83               ClkMuxSt,
84               CntIncrSt,
85               CntProgSt,
86               TransCheckSt,
87               FlashRmaSt,
88               TokenHashSt,
89               TokenCheck0St,
90               TokenCheck1St,
91               TransProgSt: begin
92                 if (lc_state_valid_i) begin
                   -2-  
93                   unique case (lc_state_i)
                            -3-  
94                     ///////////////////////////////////////////////////////////////////
95                     // Only enable life cycle TAP register for OTP test mechanisms.
96                     LcStRaw,
97                     LcStTestLocked0,
98                     LcStTestLocked1,
99                     LcStTestLocked2,
100                    LcStTestLocked3,
101                    LcStTestLocked4,
102                    LcStTestLocked5,
103                    LcStTestLocked6: begin
104                      lc_raw_test_rma = On;
                         ==>
105                    end
106                    ///////////////////////////////////////////////////////////////////
107                    // Enable DFT and debug functionality, including the CPU in the
108                    // test unlocked states.
109                    LcStTestUnlocked0,
110                    LcStTestUnlocked1,
111                    LcStTestUnlocked2,
112                    LcStTestUnlocked3,
113                    LcStTestUnlocked4,
114                    LcStTestUnlocked5,
115                    LcStTestUnlocked6: begin
116                      lc_raw_test_rma      = On;
                         ==>
117                      lc_dft_en            = On;
118                      lc_nvm_debug_en      = On;
119                      lc_hw_debug_en       = On;
120                      lc_cpu_en            = On;
121                      lc_iso_part_sw_wr_en = On;
122                      lc_keymgr_div_d      = RndCnstLcKeymgrDivTestUnlocked;
123                    end
124                    ///////////////////////////////////////////////////////////////////
125                    // This is the last TEST_UNLOCKED state. The same feature set is enabled
126                    // as in the other TEST_UNLOCKED states above, except for NVM debug en,
127                    // which is disabled in this state.
128                    LcStTestUnlocked7: begin
129                      lc_raw_test_rma      = On;
                         ==>
130                      lc_dft_en            = On;
131                      lc_hw_debug_en       = On;
132                      lc_cpu_en            = On;
133                      lc_iso_part_sw_wr_en = On;
134                      lc_keymgr_div_d      = RndCnstLcKeymgrDivTestUnlocked;
135                    end
136                    ///////////////////////////////////////////////////////////////////
137                    // Enable production functions
138                    LcStProd,
139                    LcStProdEnd: begin
140                      lc_cpu_en              = On;
                         ==>
141                      lc_keymgr_en           = On;
142                      lc_owner_seed_sw_rw_en = On;
143                      lc_iso_part_sw_wr_en   = On;
144                      lc_iso_part_sw_rd_en   = On;
145                      lc_keymgr_div_d        = RndCnstLcKeymgrDivProduction;
146                      // Only allow provisioning if the device has not yet been personalized.
147                      // If secrets_valid_i is set to ON, we output OFF.
148                      // Note that we can convert ON to OFF with a bitwise inversion due to the encoding.
149                      lc_creator_seed_sw_rw_en = lc_tx_t'(~secrets_valid_i);
150                      // Only allow hardware to consume the seeds once personalized.
151                      // If secrets_valid_i is set to ON, we output ON.
152                      lc_seed_hw_rd_en = secrets_valid_i;
153                    end
154                    ///////////////////////////////////////////////////////////////////
155                    // Similar functions as PROD, with the following differences:
156                    // - hardware debug functionality (CPU TAP) is enabled,
157                    // - access to the isolated flash partition is disabled.
158                    LcStDev: begin
159                      lc_hw_debug_en         = On;
                         ==>
160                      lc_cpu_en              = On;
161                      lc_keymgr_en           = On;
162                      lc_owner_seed_sw_rw_en = On;
163                      lc_iso_part_sw_wr_en   = On;
164                      lc_keymgr_div_d        = RndCnstLcKeymgrDivDev;
165                      // Only allow provisioning if the device has not yet been personalized.
166                      // If secrets_valid_i is set to ON, we output OFF.
167                      // Note that we can convert ON to OFF with a bitwise inversion due to the encoding.
168                      lc_creator_seed_sw_rw_en = lc_tx_t'(~secrets_valid_i);
169                      // Only allow hardware to consume the seeds once personalized.
170                      // If secrets_valid_i is set to ON, we output ON.
171                      lc_seed_hw_rd_en = secrets_valid_i;
172                    end
173                    ///////////////////////////////////////////////////////////////////
174                    // Enable all test and production functions.
175                    LcStRma: begin
176                      lc_raw_test_rma          = On;
                         ==>
177                      lc_dft_en                = On;
178                      lc_nvm_debug_en          = On;
179                      lc_hw_debug_en           = On;
180                      lc_cpu_en                = On;
181                      lc_keymgr_en             = On;
182                      lc_creator_seed_sw_rw_en = On;
183                      lc_owner_seed_sw_rw_en   = On;
184                      lc_iso_part_sw_wr_en     = On;
185                      lc_iso_part_sw_rd_en     = On;
186                      lc_seed_hw_rd_en         = On;
187                      lc_keymgr_div_d          = RndCnstLcKeymgrDivRma;
188                    end
189                    ///////////////////////////////////////////////////////////////////
190                    // Invalid or scrapped life cycle state, make sure the escalation
191                    // signal is also asserted in this case.
192                    default: begin
193                      lc_escalate_en = On;
                         ==>
194                    end
195                  endcase // lc_state_i
196                end else begin
197                  lc_escalate_en = On;
                     ==>
198                end
199              end
200              ///////////////////////////////////////////////////////////////////
201              // Post-transition state. Behaves similarly to the virtual scrap
202              // states below, with the exception that escalate_en is NOT asserted,
203              // since that could trigger unwanted alerts / escalations and system resets.
204              PostTransSt: ;
                 ==>
205              ///////////////////////////////////////////////////////////////////
206              // Virtual scrap states, make sure the escalation signal is
207              // also asserted in this case.
208              ScrapSt,
209              EscalateSt,
210              InvalidSt: begin
211                lc_escalate_en = On;
                   ==>
212              end
213              default: begin
214                lc_escalate_en = On;
                   ==>

Branches:

-1-	-2-	-3-	Status	Tests
ResetSt	-	-	Covered	T1,T2,T3
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	CASEITEM-1: LcStRaw LcStTestLocked0 LcStTestLocked1 LcStTestLocked2 LcStTestLocked3 LcStTestLocked4 LcStTestLocked5 LcStTestLocked6	Covered	T1,T2,T12
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	CASEITEM-2: LcStTestUnlocked0 LcStTestUnlocked1 LcStTestUnlocked2 LcStTestUnlocked3 LcStTestUnlocked4 LcStTestUnlocked5 LcStTestUnlocked6	Covered	T1,T2,T3
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStTestUnlocked7	Covered	T4,T14,T15
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStProd LcStProdEnd	Covered	T2,T4,T5
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStDev	Covered	T2,T4,T18
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStRma	Covered	T11,T18,T19
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	default	Covered	T16,T36,T41
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	0	-	Not Covered
PostTransSt	-	-	Covered	T1,T2,T12
ScrapSt EscalateSt InvalidSt	-	-	Covered	T4,T5,T11
default	-	-	Covered	T11,T16,T36

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Assert Coverage for Module : lc_ctrl_signal_decode

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmInScrap_A	58101981	11672070	0	0
LcKeymgrDivUnique0_A	812	812	0	0
LcKeymgrDivUnique1_A	812	812	0	0
LcKeymgrDivUnique2_A	812	812	0	0
LcKeymgrDivUnique3_A	812	812	0	0
SignalsAreOffWhenNotEnabled_A	58101981	1143284	0	0
StateInScrap_A	58101981	4299	0	0

FsmInScrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	11672070	0	0
T4	31121	6056	0	0
T5	3571	861	0	0
T6	7859	0	0	0
T7	12360	0	0	0
T8	17991	0	0	0
T11	29727	12533	0	0
T14	16415	2077	0	0
T15	5970	1925	0	0
T16	6146	1028	0	0
T18	0	13854	0	0
T22	981	0	0	0
T33	0	4760	0	0
T36	0	1781	0	0
T41	0	15	0	0

LcKeymgrDivUnique0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

LcKeymgrDivUnique1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

LcKeymgrDivUnique2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

LcKeymgrDivUnique3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	812	812	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

SignalsAreOffWhenNotEnabled_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	1143284	0	0
T1	1059	1	0	0
T2	2661	14	0	0
T3	1066	1	0	0
T4	31121	16	0	0
T5	3571	8	0	0
T6	7859	1	0	0
T7	12360	1	0	0
T11	29727	1456	0	0
T12	1274	1	0	0
T13	1016	1	0	0

StateInScrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	4299	0	0
T16	6146	2	0	0
T17	33533	0	0	0
T18	31891	0	0	0
T19	25169	0	0	0
T30	1328	0	0	0
T33	22492	0	0	0
T36	5942	2	0	0
T41	17044	1	0	0
T42	3246	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T60	0	20	0	0
T62	0	1	0	0
T90	0	2	0	0
T91	0	13	0	0
T92	0	3	0	0
T93	1850	0	0	0