Unified Coverage Report :: Module :: lc_ctrl_fsm

Module : lc_ctrl_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.95	97.77	89.13		75.51	97.33	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm	98.10	98.87	93.02		100.00	98.63	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	98.87	93.02		100.00	98.63	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.38	99.39	89.84		100.00	97.67	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_syncs[0].u_prim_lc_sync_flash_rma_ack	100.00	100.00				100.00	100.00
gen_syncs[1].u_prim_lc_sync_flash_rma_ack	100.00	100.00				100.00	100.00
u_cnt_regs	100.00	100.00				100.00	100.00
u_fsm_state_regs	100.00	100.00				100.00	100.00
u_lc_ctrl_fsm_cov_if	96.97	100.00	90.91			100.00
u_lc_ctrl_signal_decode	98.86	99.21				97.37	100.00
u_lc_ctrl_state_decode	98.89	100.00	100.00			96.67
u_lc_ctrl_state_transition	89.97	98.48	75.00			96.43
u_prim_lc_sender_check_byp_en	100.00	100.00				100.00
u_prim_lc_sender_clk_byp_req	100.00	100.00				100.00
u_prim_lc_sender_flash_rma_req	100.00	100.00				100.00
u_prim_lc_sync_clk_byp_ack	100.00	100.00				100.00	100.00
u_prim_lc_sync_flash_rma_ack_buf	100.00	100.00					100.00
u_prim_lc_sync_rma_token_valid	100.00	100.00					100.00
u_prim_lc_sync_test_token_valid	100.00	100.00					100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : lc_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		179	175	97.77
CONT_ASSIGN	126	1	1	100.00
ALWAYS	146	3	3	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	204	114	110	96.49
ALWAYS	584	3	3	100.00
ALWAYS	585	3	3	100.00
ALWAYS	586	3	3	100.00
ALWAYS	589	3	3	100.00
ALWAYS	608	5	5	100.00
CONT_ASSIGN	619	1	1	100.00
CONT_ASSIGN	666	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
ALWAYS	677	15	15	100.00
ALWAYS	712	14	14	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	740	1	1	100.00
CONT_ASSIGN	742	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
ALWAYS	882	3	3	100.00

Click here to see the source line report.

---

Cond Coverage for Module : lc_ctrl_fsm

	Total	Covered	Percent
Conditions	92	82	89.13
Logical	92	82	89.13
Non-Logical	0	0
Event	0	0

 LINE       251
 EXPRESSION (init_req_i && lc_state_valid_q)
             -----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T16,T36
1	1	Covered	T1,T2,T3

 LINE       284
 EXPRESSION (lc_state_q == LcStScrap)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T45,T46

 LINE       293
 EXPRESSION (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i)
             -----------1----------    ----------2----------    -----3-----

-1-	-2-	-3-	Status	Tests
-	0	1	Covered	T1,T2,T4
-	1	0	Covered	T1,T12,T6
-	1	1	Covered	T1,T12,T30

 LINE       295
 EXPRESSION ((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}) && ((!trans_invalid_error_o)))
             -----------1-----------    ----------------------------------------2---------------------------------------    -------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T12,T30

 LINE       295
 SUB-EXPRESSION (lc_state_q == LcStRaw)
                -----------1-----------

-1-	Status	Tests
0	Covered	T12,T31,T32
1	Covered	T1,T12,T30

 LINE       295
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Covered	T12,T31,T32
1	Covered	T1,T12,T30

 LINE       299
 EXPRESSION (unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T12,T30

 LINE       305
 EXPRESSION ((lc_cnt_q == LcCnt0) ? LcCnt1 : lc_cnt_q)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T12,T30
1	Covered	T54

 LINE       305
 SUB-EXPRESSION (lc_cnt_q == LcCnt0)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T12,T30
1	Covered	T54

 LINE       411
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[1])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T33,T47,T21

 LINE       452
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T39,T40,T34
1	0	1	Covered	T21,T43,T44
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T11

 LINE       452
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T33,T39,T40
1	Covered	T1,T2,T11

 LINE       466
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T2,T16,T18

 LINE       493
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T11

 LINE       493
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T11

 LINE       496
 EXPRESSION (fsm_state_q == TokenCheck1St)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T1,T2,T11

 LINE       524
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[2])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T49,T50,T51

 LINE       529
 EXPRESSION 
 Number  Term
      1  ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))) || 
      2  ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T11
0	1	Covered	T47,T50,T55
1	0	Covered	T52,T56,T57

 LINE       529
 SUB-EXPRESSION ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off)))
                 -----------------------------------1----------------------------------    --------------------------------2--------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T18
1	0	Covered	T1,T2,T11
1	1	Covered	T52,T56,T57

 LINE       529
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T2,T16,T18
1	Covered	T1,T2,T11

 LINE       529
 SUB-EXPRESSION ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))
                 -------------1-------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T11
0	1	Covered	T52,T56,T57
1	0	Not Covered

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_req_o != Off)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T2,T16,T18

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_ack_buf[2] != Off)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T2,T16,T18

 LINE       529
 SUB-EXPRESSION ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On)))
                 -----------------------------------1----------------------------------    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T2,T16,T18
1	1	Covered	T47,T50,T55

 LINE       529
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T2,T16,T18

 LINE       529
 SUB-EXPRESSION ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On))
                 -------------1------------    ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T16,T18
0	1	Covered	T47,T50,T55
1	0	Covered	T58,T59

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_req_o != On)
                -------------1------------

-1-	Status	Tests
0	Covered	T2,T16,T18
1	Covered	T1,T2,T11

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_ack_buf[2] != On)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T16,T18
1	Covered	T1,T2,T11

 LINE       567
 EXPRESSION (esc_scrap_state0_i || esc_scrap_state1_i)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T11
1	0	Covered	T4,T5,T11

 LINE       574
 EXPRESSION ((((|state_invalid_error)) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt))
             -----------------------1-----------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T16,T60
1	1	Covered	T11,T16,T36

 LINE       574
 SUB-EXPRESSION (((|state_invalid_error)) | token_if_fsm_err_i)
                 ------------1-----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T16,T60
1	0	Covered	T11,T16,T36

 LINE       574
 SUB-EXPRESSION (fsm_state_q != EscalateSt)
                -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T11
1	Covered	T1,T2,T3

 LINE       612
 SUB-EXPRESSION (set_strap_en_override || gen_strap_delay_regs.strap_en_override_q[0])
                 ----------1----------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T30
1	0	Covered	T1,T12,T30

 LINE       732
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[0]][trans_target_i[0]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       732
 SUB-EXPRESSION ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       736
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[1]][trans_target_i[1]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       736
 SUB-EXPRESSION ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T7,T9,T61
1	1	Covered	T1,T2,T3

 LINE       749
 EXPRESSION (trans_invalid_error || (token_idx0 != token_idx1))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T39
1	0	Covered	T12,T21,T43

 LINE       749
 SUB-EXPRESSION (token_idx0 != token_idx1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T39

---

FSM Coverage for Module : lc_ctrl_fsm

Summary for FSM :: fsm_state_q

	Total	Covered	Percent
States	15	15	100.00	(Not included in score)
Transitions	47	35	74.47
Sequences	0	0

State, Transition and Sequence Details for FSM :: fsm_state_q

---

states	Line No.	Covered	Tests
ClkMuxSt	327	Covered	T1,T2,T4
CntIncrSt	385	Covered	T1,T2,T4
CntProgSt	401	Covered	T1,T2,T4
EscalateSt	568	Covered	T4,T5,T11
FlashRmaSt	455	Covered	T1,T2,T11
IdleSt	252	Covered	T1,T2,T3
InvalidSt	575	Covered	T11,T16,T36
PostTransSt	317	Covered	T1,T2,T12
ResetSt	246	Covered	T1,T2,T3
ScrapSt	285	Covered	T41,T45,T46
TokenCheck0St	469	Covered	T1,T2,T11
TokenCheck1St	501	Covered	T1,T2,T11
TokenHashSt	434	Covered	T1,T2,T11
TransCheckSt	423	Covered	T1,T2,T11
TransProgSt	499	Covered	T1,T2,T11

transitions	Line No.	Covered	Tests
ClkMuxSt->CntIncrSt	385	Covered	T1,T2,T4
ClkMuxSt->EscalateSt	568	Covered	T62,T63,T64
ClkMuxSt->InvalidSt	575	Not Covered
CntIncrSt->CntProgSt	401	Covered	T1,T2,T4
CntIncrSt->EscalateSt	568	Covered	T65,T62,T66
CntIncrSt->InvalidSt	575	Not Covered
CntIncrSt->PostTransSt	399	Covered	T21,T43,T44
CntProgSt->EscalateSt	568	Covered	T18,T65,T62
CntProgSt->InvalidSt	575	Not Covered
CntProgSt->PostTransSt	412	Covered	T4,T5,T14
CntProgSt->TransCheckSt	423	Covered	T1,T2,T11
EscalateSt->InvalidSt	575	Not Covered
FlashRmaSt->EscalateSt	568	Covered	T18,T65,T62
FlashRmaSt->InvalidSt	575	Not Covered
FlashRmaSt->TokenCheck0St	469	Covered	T1,T2,T11
IdleSt->ClkMuxSt	327	Covered	T1,T2,T4
IdleSt->EscalateSt	568	Covered	T18,T65,T62
IdleSt->InvalidSt	575	Covered	T11,T16,T36
IdleSt->PostTransSt	317	Covered	T12,T31,T32
IdleSt->ScrapSt	285	Covered	T41,T45,T46
InvalidSt->EscalateSt	568	Covered	T11,T16,T36
PostTransSt->EscalateSt	568	Covered	T4,T5,T14
PostTransSt->InvalidSt	575	Not Covered
ResetSt->EscalateSt	568	Covered	T18,T65,T62
ResetSt->IdleSt	252	Covered	T1,T2,T3
ResetSt->InvalidSt	575	Not Covered
ScrapSt->EscalateSt	568	Covered	T62,T66,T63
ScrapSt->InvalidSt	575	Covered	T67
TokenCheck0St->EscalateSt	568	Covered	T18,T65,T49
TokenCheck0St->InvalidSt	575	Not Covered
TokenCheck0St->PostTransSt	483	Covered	T33,T39,T34
TokenCheck0St->TokenCheck1St	501	Covered	T1,T2,T11
TokenCheck1St->EscalateSt	568	Covered	T18,T62,T66
TokenCheck1St->InvalidSt	575	Not Covered
TokenCheck1St->PostTransSt	483	Covered	T39,T34,T48
TokenCheck1St->TransProgSt	499	Covered	T1,T2,T11
TokenHashSt->EscalateSt	568	Covered	T18,T65,T62
TokenHashSt->FlashRmaSt	455	Covered	T1,T2,T11
TokenHashSt->InvalidSt	575	Not Covered
TokenHashSt->PostTransSt	457	Covered	T33,T39,T40
TransCheckSt->EscalateSt	568	Covered	T18,T62,T66
TransCheckSt->InvalidSt	575	Not Covered
TransCheckSt->PostTransSt	432	Covered	T39,T34,T21
TransCheckSt->TokenHashSt	434	Covered	T1,T2,T11
TransProgSt->EscalateSt	568	Covered	T18,T65,T62
TransProgSt->InvalidSt	575	Not Covered
TransProgSt->PostTransSt	525	Covered	T1,T2,T11

Summary for FSM :: lc_state_q

	Total	Covered	Percent
States	21	21	100.00	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_state_q

---

states	Line No.	Covered	Tests
LcStDev	92	Covered	T2,T4,T18
LcStProd	93	Covered	T2,T4,T5
LcStProdEnd	94	Covered	T2,T4,T5
LcStRaw	295	Covered	T1,T2,T12
LcStRma	333	Covered	T11,T18,T19
LcStScrap	284	Covered	T1,T2,T3
LcStTestLocked0	333	Covered	T5,T22,T17
LcStTestLocked1	333	Covered	T4,T11,T8
LcStTestLocked2	333	Covered	T4,T11,T14
LcStTestLocked3	333	Covered	T2,T11,T15
LcStTestLocked4	333	Covered	T2,T7,T15
LcStTestLocked5	333	Covered	T4,T17,T18
LcStTestLocked6	333	Covered	T2,T4,T5
LcStTestUnlocked0	301	Covered	T1,T2,T12
LcStTestUnlocked1	333	Covered	T4,T6,T11
LcStTestUnlocked2	333	Covered	T2,T5,T11
LcStTestUnlocked3	333	Covered	T2,T11,T15
LcStTestUnlocked4	333	Covered	T3,T4,T11
LcStTestUnlocked5	333	Covered	T4,T5,T15
LcStTestUnlocked6	333	Covered	T4,T16,T17
LcStTestUnlocked7	333	Covered	T4,T14,T15

transitions	Line No.	Covered	Tests
LcStRaw->LcStTestUnlocked0	301	Covered	T1,T12,T30

Summary for FSM :: lc_cnt_q

	Total	Covered	Percent
States	25	10	40.00	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_cnt_q

---

states	Line No.	Covered	Tests
LcCnt0	305	Covered	T33,T34,T35
LcCnt1	305	Covered	T2,T4,T17
LcCnt10	112	Not Covered
LcCnt11	113	Not Covered
LcCnt12	114	Not Covered
LcCnt13	115	Not Covered
LcCnt14	116	Not Covered
LcCnt15	117	Not Covered
LcCnt16	118	Not Covered
LcCnt17	119	Not Covered
LcCnt18	120	Not Covered
LcCnt19	121	Not Covered
LcCnt2	104	Covered	T4,T11,T17
LcCnt20	122	Not Covered
LcCnt21	123	Not Covered
LcCnt22	124	Not Covered
LcCnt23	125	Not Covered
LcCnt24	126	Not Covered
LcCnt3	105	Covered	T2,T16,T18
LcCnt4	106	Covered	T1,T2,T4
LcCnt5	107	Covered	T15,T17,T18
LcCnt6	108	Covered	T12,T4,T5
LcCnt7	109	Covered	T4,T15,T18
LcCnt8	110	Covered	T15,T16,T18
LcCnt9	111	Covered	T3,T13,T4

transitions	Line No.	Covered	Tests
LcCnt0->LcCnt1	305	Covered	T68,T54,T69

---

Branch Coverage for Module : lc_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		75	73	97.33
TERNARY	732	1	1	100.00
TERNARY	736	1	1	100.00
CASE	242	46	44	95.65
IF	567	3	3	100.00
IF	584	2	2	100.00
IF	585	2	2	100.00
IF	586	2	2	100.00
IF	589	2	2	100.00
IF	684	2	2	100.00
IF	687	2	2	100.00
IF	691	2	2	100.00
IF	694	2	2	100.00
IF	698	2	2	100.00
IF	701	2	2	100.00
IF	882	2	2	100.00
IF	608	2	2	100.00

732          assign token_idx0 = (int'(dec_lc_state_o[0]) < NumLcStates &&
                                                                          
733                               int'(trans_target_i[0]) < NumLcStates) ?
                                                                         -1-  
                                                                         ==>  
                                                                         ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

736          assign token_idx1 = (int'(dec_lc_state_o[1]) < NumLcStates &&
                                                                          
737                               int'(trans_target_i[1]) < NumLcStates) ?
                                                                         -1-  
                                                                         ==>  
                                                                         ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

242            unique case (fsm_state_q)
                      -1-  
243              ///////////////////////////////////////////////////////////////////
244              // Wait here until OTP has initialized and the
245              // power manager sends an initialization request.
246              ResetSt: begin
247                init_done_o = 1'b0;
248                lc_clk_byp_req   = Off;
249                lc_flash_rma_req = Off;
250                lc_check_byp_en  = Off;
251                if (init_req_i && lc_state_valid_q) begin
                   -2-  
252                  fsm_state_d = IdleSt;
                     ==>
253                  // Fetch LC state vector from OTP.
254                  lc_state_d  = lc_state_i;
255                  lc_cnt_d    = lc_cnt_i;
256                end
                   MISSING_ELSE
                   ==>
257              end
258              ///////////////////////////////////////////////////////////////////
259              // Idle state where life cycle control signals are broadcast.
260              // Note that the life cycle signals are decoded and broadcast
261              // in the lc_ctrl_signal_decode submodule.
262              IdleSt: begin
263                idle_o = 1'b1;
264        
265                // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
266                // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
267                // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
268                // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
269                // ---------------------------------------------------------------
270                // Note that if the volatile unlock mechanism is available,
271                // we have to stop fetching the OTP value after a volatile unlock has succeeded.
272                // Otherwise we unconditionally fetch from OTP in this state.
273                if (!(SecVolatileRawUnlockEn && lc_state_q == LcStTestUnlocked0 && lc_cnt_q != LcCnt0) ||
                   -3-  
274                    prim_mubi_pkg::mubi8_test_false_loose(volatile_raw_unlock_success_q)) begin
275                  // Continuously fetch LC state vector from OTP.
276                  // The state is locked in once a transition is started.
277                  lc_state_d    = lc_state_i;
                     ==>
278                  lc_cnt_d      = lc_cnt_i;
279                end
                   MISSING_ELSE
                   ==>
280                // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
281        
282                // If the life cycle state is SCRAP, we move the FSM into a terminal
283                // SCRAP state that does not allow any transitions to be initiated anymore.
284                if (lc_state_q == LcStScrap) begin
                   -4-  
285                  fsm_state_d = ScrapSt;
                     ==>
286        
287                // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
288                // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
289                // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
290                // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
291                // ---------------------------------------------------------------
292                // Only enter here if volatile RAW unlock is available and enabled.
293                end else if (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i) begin
                            -5-  
294                  // We only allow transitions from RAW -> TEST_UNLOCKED0
295                  if (lc_state_q == LcStRaw &&
                     -6-  
296                      trans_target_i == {DecLcStateNumRep{DecLcStTestUnlocked0}} &&
297                      !trans_invalid_error_o) begin
298                    // 128bit token check (without passing it through the KMAC)
299                    if (unhashed_token_i == RndCnstRawUnlockTokenHashed) begin
                       -7-  
300                      // We stay in Idle, but update the life cycle state register (volatile).
301                      lc_state_d = LcStTestUnlocked0;
302                      // If the count is 0, we set it to 1 - otherwise we just leave it as is so that the
303                      // register value is in sync with what has been programmed to OTP already (there may
304                      // have been unsuccessul raw unlock attempts before that already incremented it).
305                      lc_cnt_d = (lc_cnt_q == LcCnt0) ? LcCnt1 : lc_cnt_q;
                                                         -8-  
                                                         ==>  
                                                         ==>  
306                      // Re-sample the DFT straps in the pinmux.
307                      // This signal will be delayed by several cycles so that the LC_CTRL signals
308                      // have time to propagate.
309                      set_strap_en_override = 1'b1;
310                      // We have to remember that the transition was successful in order to correctly
311                      // disable the continuos sampling of the life cycle state vector coming from OTP.
312                      volatile_raw_unlock_success_d = prim_mubi_pkg::MuBi8True;
313                      // Indicate that the transition was successful.
314                      trans_success_o = 1'b1;
315                    end else begin
316                      token_invalid_error_o = 1'b1;
                         ==>
317                      fsm_state_d = PostTransSt;
318                    end
319                  end else begin
320                    // Transition invalid error is set by lc_ctrl_state_transition module.
321                    fsm_state_d = PostTransSt;
                       ==>
322                  end
323                // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
324                // Initiate a transition. This will first increment the
325                // life cycle counter before hashing and checking the token.
326                end else if (trans_cmd_i) begin
                            -9-  
327                  fsm_state_d = ClkMuxSt;
                     ==>
328                end
                   MISSING_ELSE
                   ==>
329                // If we are in a non-PROD life cycle state, steer the clock mux if requested. This
330                // action is available in IdleSt so that the mux can be steered without having to initiate
331                // a life cycle transition. If a transition is initiated however, the life cycle controller
332                // will wait for the clock mux acknowledgement in the ClkMuxSt state before proceeding.
333                if (lc_state_q inside {LcStRaw,
                   -10-  
334                                       LcStTestLocked0,
335                                       LcStTestLocked1,
336                                       LcStTestLocked2,
337                                       LcStTestLocked3,
338                                       LcStTestLocked4,
339                                       LcStTestLocked5,
340                                       LcStTestLocked6,
341                                       LcStTestUnlocked0,
342                                       LcStTestUnlocked1,
343                                       LcStTestUnlocked2,
344                                       LcStTestUnlocked3,
345                                       LcStTestUnlocked4,
346                                       LcStTestUnlocked5,
347                                       LcStTestUnlocked6,
348                                       LcStTestUnlocked7,
349                                       LcStRma}) begin
350                  if (use_ext_clock_i) begin
                     -11-  
351                    lc_clk_byp_req = On;
                       ==>
352                  end
                     MISSING_ELSE
                     ==>
353                end
                   MISSING_ELSE
                   ==>
354              end
355              ///////////////////////////////////////////////////////////////////
356              // Clock mux state. If we are in RAW, TEST* or RMA, it is permissible
357              // to switch to an external clock source. If the bypass request is
358              // asserted, we have to wait until the clock mux and clock manager
359              // have switched the mux and the clock divider. Also, we disable the
360              // life cycle partition checks at this point since we are going to
361              // alter the contents in the OTP memory array, which could lead to
362              // spurious escalations.
363              ClkMuxSt: begin
364                lc_check_byp_en = On;
365                if (lc_state_q inside {LcStRaw,
                   -12-  
366                                       LcStTestLocked0,
367                                       LcStTestLocked1,
368                                       LcStTestLocked2,
369                                       LcStTestLocked3,
370                                       LcStTestLocked4,
371                                       LcStTestLocked5,
372                                       LcStTestLocked6,
373                                       LcStTestUnlocked0,
374                                       LcStTestUnlocked1,
375                                       LcStTestUnlocked2,
376                                       LcStTestUnlocked3,
377                                       LcStTestUnlocked4,
378                                       LcStTestUnlocked5,
379                                       LcStTestUnlocked6,
380                                       LcStTestUnlocked7,
381                                       LcStRma}) begin
382                  if (use_ext_clock_i) begin
                     -13-  
383                    lc_clk_byp_req = On;
384                    if (lc_tx_test_true_strict(lc_clk_byp_ack[0])) begin
                       -14-  
385                      fsm_state_d = CntIncrSt;
                         ==>
386                    end
                       MISSING_ELSE
                       ==>
387                  end else begin
388                    fsm_state_d = CntIncrSt;
                       ==>
389                  end
390                end else begin
391                  fsm_state_d = CntIncrSt;
                     ==>
392                end
393              end
394              ///////////////////////////////////////////////////////////////////
395              // This increments the life cycle counter state.
396              CntIncrSt: begin
397                // If the counter has reached the maximum, bail out.
398                if (trans_cnt_oflw_error_o) begin
                   -15-  
399                  fsm_state_d = PostTransSt;
                     ==>
400                end else begin
401                  fsm_state_d = CntProgSt;
                     ==>
402                end
403              end
404              ///////////////////////////////////////////////////////////////////
405              // This programs the life cycle counter state.
406              CntProgSt: begin
407                otp_prog_req_o = 1'b1;
408        
409                // If the clock mux has been steered, double check that this is still the case.
410                // Otherwise abort the transition operation.
411                if (lc_clk_byp_req_o != lc_clk_byp_ack[1]) begin
                   -16-  
412                    fsm_state_d = PostTransSt;
                       ==>
413                    otp_prog_error_o = 1'b1;
414                end
                   MISSING_ELSE
                   ==>
415        
416                // Check return value and abort if there
417                // was an error.
418                if (otp_prog_ack_i) begin
                   -17-  
419                  if (otp_prog_err_i) begin
                     -18-  
420                    fsm_state_d = PostTransSt;
                       ==>
421                    otp_prog_error_o = 1'b1;
422                  end else begin
423                    fsm_state_d = TransCheckSt;
                       ==>
424                  end
425                end
                   MISSING_ELSE
                   ==>
426              end
427              ///////////////////////////////////////////////////////////////////
428              // First transition valid check. This will be repeated several
429              // times below.
430              TransCheckSt: begin
431                if (trans_invalid_error_o) begin
                   -19-  
432                  fsm_state_d = PostTransSt;
                     ==>
433                end else begin
434                  fsm_state_d = TokenHashSt;
                     ==>
435                end
436              end
437              ///////////////////////////////////////////////////////////////////
438              // Hash and compare the token, no matter whether this transition
439              // is conditional or not. Unconditional transitions just use a known
440              // all-zero token value. That way, we always compare a hashed token
441              // and guarantee that no other control flow path exists that could
442              // bypass the token check.
443              // SEC_CM: TOKEN.DIGEST
444              TokenHashSt: begin
445                token_hash_req_o = 1'b1;
446                if (token_hash_ack_i) begin
                   -20-  
447                  // This is the first comparison.
448                  // The token is compared two more times further below.
449                  // Also note that conditional transitions won't be possible if the
450                  // corresponding token is not valid. This only applies to tokens stored in
451                  // OTP. I.e., these tokens first have to be provisioned, before they can be used.
452                  if (hashed_token_i == hashed_token_mux &&
                     -21-  
453                      !token_hash_err_i &&
454                      &hashed_token_valid_mux) begin
455                    fsm_state_d = FlashRmaSt;
                       ==>
456                  end else begin
457                    fsm_state_d = PostTransSt;
                       ==>
458                    token_invalid_error_o = 1'b1;
459                  end
460                end
                   MISSING_ELSE
                   ==>
461              end
462              ///////////////////////////////////////////////////////////////////
463              // Flash RMA state. Note that we check the flash response again
464              // two times later below.
465              FlashRmaSt: begin
466                if (trans_target_i == {DecLcStateNumRep{DecLcStRma}}) begin
                   -22-  
467                  lc_flash_rma_req = On;
468                  if (lc_tx_test_true_strict(lc_flash_rma_ack_buf[0])) begin
                     -23-  
469                    fsm_state_d = TokenCheck0St;
                       ==>
470                  end
                     MISSING_ELSE
                     ==>
471                end else begin
472                  fsm_state_d = TokenCheck0St;
                     ==>
473                end
474              end
475              ///////////////////////////////////////////////////////////////////
476              // Check again two times whether this transition and the hashed
477              // token are valid. Also check again whether the flash RMA
478              // response is valid.
479              // SEC_CM: TOKEN.DIGEST
480              TokenCheck0St,
481              TokenCheck1St: begin
482                if (trans_invalid_error_o) begin
                   -24-  
483                  fsm_state_d = PostTransSt;
                     ==>
484                end else begin
485                  // If any of these RMA are conditions are true,
486                  // all of them must be true at the same time.
487                  if ((trans_target_i != {DecLcStateNumRep{DecLcStRma}} &&
                     -25-  
488                       lc_tx_test_false_strict(lc_flash_rma_req_o) &&
489                       lc_tx_test_false_strict(lc_flash_rma_ack_buf[1])) ||
490                      (trans_target_i == {DecLcStateNumRep{DecLcStRma}} &&
491                       lc_tx_test_true_strict(lc_flash_rma_req_o) &&
492                       lc_tx_test_true_strict(lc_flash_rma_ack_buf[1]))) begin
493                    if (hashed_token_i == hashed_token_mux &&
                       -26-  
494                        !token_hash_err_i &&
495                        &hashed_token_valid_mux) begin
496                      if (fsm_state_q == TokenCheck1St) begin
                         -27-  
497                        // This is the only way we can get into the
498                        // programming state.
499                        fsm_state_d = TransProgSt;
                           ==>
500                      end else begin
501                        fsm_state_d = TokenCheck1St;
                           ==>
502                      end
503                    end else begin
504                      fsm_state_d = PostTransSt;
                         ==>
505                      token_invalid_error_o = 1'b1;
506                    end
507                  // The flash RMA process failed.
508                  end else begin
509                      fsm_state_d = PostTransSt;
                         ==>
510                      flash_rma_error_o = 1'b1;
511                  end
512                end
513              end
514              ///////////////////////////////////////////////////////////////////
515              // Initiate OTP transaction. Note that the concurrent
516              // LC state check is continuously checking whether the
517              // new LC state remains valid. Once the ack returns we are
518              // done with the transition and can go into the terminal PosTransSt.
519              TransProgSt: begin
520                otp_prog_req_o = 1'b1;
521        
522                // If the clock mux has been steered, double check that this is still the case.
523                // Otherwise abort the transition operation.
524                if (lc_clk_byp_req_o != lc_clk_byp_ack[2]) begin
                   -28-  
525                  fsm_state_d = PostTransSt;
                     ==>
526                  otp_prog_error_o = 1'b1;
527                // Also double check that the RMA signals remain stable.
528                // Otherwise abort the transition operation.
529                end else if ((trans_target_i != {DecLcStateNumRep{DecLcStRma}} &&
                            -29-  
530                              (lc_flash_rma_req_o != Off || lc_flash_rma_ack_buf[2] != Off)) ||
531                             (trans_target_i == {DecLcStateNumRep{DecLcStRma}} &&
532                              (lc_flash_rma_req_o != On || lc_flash_rma_ack_buf[2] != On))) begin
533                  fsm_state_d = PostTransSt;
                     ==>
534                  flash_rma_error_o = 1'b1;
535                end else if (otp_prog_ack_i) begin
                            -30-  
536                  fsm_state_d = PostTransSt;
                     ==>
537                  otp_prog_error_o = otp_prog_err_i;
538                  trans_success_o  = ~otp_prog_err_i;
539                end
                   MISSING_ELSE
                   ==>
540              end
541              ///////////////////////////////////////////////////////////////////
542              // Terminal states.
543              ScrapSt,
544              PostTransSt: ;
                 ==>
545        
546        
547              EscalateSt: begin
548                // During an escalation it is okay to de-assert token_hash_req without receivng ACK.
549                token_hash_req_chk_o = 1'b0;
                   ==>
550              end
551        
552              InvalidSt: begin
553                // During an escalation it is okay to de-assert token_hash_req without receivng ACK.
554                token_hash_req_chk_o = 1'b0;
                   ==>
555                state_invalid_error_o = 1'b1;
556              end
557              ///////////////////////////////////////////////////////////////////
558              // Go to terminal error state if we get here.
559              default: begin
560                fsm_state_d = InvalidSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T30
IdleSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T41,T45,T46
IdleSt	-	-	0	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T54
IdleSt	-	-	0	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T30
IdleSt	-	-	0	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T31,T32
IdleSt	-	-	0	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	0	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T17
IdleSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T17,T30
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T17,T30
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T43,T44
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T33,T47,T21
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T14
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T39,T34,T21
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	Covered	T33,T39,T40
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	Covered	T2,T16,T18
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	Covered	T2,T16,T18
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T39,T34,T48
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T1,T2,T11
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T1,T2,T11
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T33,T47,T21
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T49,T50,T51
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T47,T50,T52
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	Covered	T1,T2,T11
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	Covered	T1,T2,T11
ScrapSt PostTransSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T12
EscalateSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T11
InvalidSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T16,T36
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T16,T36

567            if (esc_scrap_state0_i || esc_scrap_state1_i) begin
               -1-  
568              fsm_state_d = EscalateSt;
                 ==>
569            // SEC_CM: MAIN.FSM.LOCAL_ESC
570            // If at any time the life cycle state encoding or any other FSM state within this module
571            // is not valid, we jump into the terminal error state right away.
572            // Note that state_invalid_error is a multibit error signal
573            // with different error sources - need to reduce this to one bit here.
574            end else if ((|state_invalid_error | token_if_fsm_err_i) && (fsm_state_q != EscalateSt)) begin
                        -2-                                  
575              fsm_state_d = InvalidSt;
                 ==>
576              state_invalid_error_o = 1'b1;
577            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T11
0	1	Covered	T11,T16,T36
0	0	Covered	T1,T2,T3

584          `PRIM_FLOP_SPARSE_FSM(u_fsm_state_regs, fsm_state_d, fsm_state_q, fsm_state_e, ResetSt)
             -1-                                                                                       
             ==>                                                                                       
             ==>                                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

585          `PRIM_FLOP_SPARSE_FSM(u_state_regs, lc_state_d, lc_state_q, lc_state_e, LcStScrap)
             -1-                                                                                  
             ==>                                                                                  
             ==>                                                                                  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

586          `PRIM_FLOP_SPARSE_FSM(u_cnt_regs, lc_cnt_d, lc_cnt_q, lc_cnt_e, LcCnt24)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

589            if (!rst_ni) begin
               -1-  
590              lc_state_valid_q <= 1'b0;
                 ==>
591            end else begin
592              lc_state_valid_q <= lc_state_valid_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

684            if (lc_tx_test_true_strict(test_tokens_valid[0])) begin
               -1-  
685              hashed_tokens_lower[TestUnlockTokenIdx] = test_unlock_token_lower;
                 ==>
686            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T33,T47,T53

687            if (lc_tx_test_true_strict(test_tokens_valid[1])) begin
               -1-  
688              hashed_tokens_upper[TestUnlockTokenIdx] = test_unlock_token_upper;
                 ==>
689            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T33,T47,T53

691            if (lc_tx_test_true_strict(test_tokens_valid[2])) begin
               -1-  
692              hashed_tokens_lower[TestExitTokenIdx] = test_exit_token_lower;
                 ==>
693            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T33,T47,T53

694            if (lc_tx_test_true_strict(test_tokens_valid[3])) begin
               -1-  
695              hashed_tokens_upper[TestExitTokenIdx] = test_exit_token_upper;
                 ==>
696            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T33,T47,T53

698            if (lc_tx_test_true_strict(rma_token_valid[0])) begin
               -1-  
699              hashed_tokens_lower[RmaTokenIdx] = rma_token_lower;
                 ==>
700            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T33,T47,T53

701            if (lc_tx_test_true_strict(rma_token_valid[1])) begin
               -1-  
702              hashed_tokens_upper[RmaTokenIdx] = rma_token_upper;
                 ==>
703            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T33,T47,T53

882          `ASSERT_FPV_LINEAR_FSM(SecCmCFILinear_A, fsm_state_q, fsm_state_e)
             -1-                                                                  
             ==>                                                                  
             ==>                                                                  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

608              if(!rst_ni) begin
                 -1-  
609                strap_en_override_q <= '0;
                   ==>
610                volatile_raw_unlock_success_q <= prim_mubi_pkg::MuBi8False;
611              end else begin
612                strap_en_override_q <= {strap_en_override_q[NumStrapDelayRegs-2:0],
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : lc_ctrl_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ClkBypStaysOnOnceAsserted_A	58101981	3157166	0	83
EscStaysOnOnceAsserted_A	58101981	11657121	0	4
FlashRmaStaysOnOnceAsserted_A	58101981	477182	0	11
FsmStateKnown_A	58101981	54873882	0	0
LcCntKnown_A	58101981	54873882	0	0
LcStateKnown_A	58101981	54873882	0	0
NoClkBypInProdStates_A	58101981	7621748	0	0
SecCmCFILinear_A	58101981	254006	0	2037
SecCmCFITerminal0_A	58101981	8823641	0	0
SecCmCFITerminal1_A	58101981	47735	0	0
SecCmCFITerminal2_A	58101981	4641199	0	0
SecCmCFITerminal3_A	58101981	6981732	0	0
u_cnt_regs_A	53137619	50236936	0	0
u_fsm_state_regs_A	56479171	53373354	0	0
u_state_regs_A	54746572	51841424	0	0

ClkBypStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	3157166	0	83
T2	2661	717	0	1
T3	1066	0	0	0
T4	31121	0	0	0
T5	3571	0	0	0
T6	7859	0	0	0
T7	12360	11666	0	1
T8	17991	0	0	0
T9	0	59240	0	1
T10	0	0	0	1
T11	29727	0	0	0
T12	1274	0	0	0
T13	1016	0	0	0
T17	0	9234	0	0
T19	0	1490	0	0
T23	0	0	0	1
T24	0	0	0	1
T30	0	1172	0	1
T37	0	3033	0	0
T45	0	4050	0	0
T46	0	415	0	0
T70	0	2110	0	1
T71	0	0	0	1
T72	0	0	0	1

EscStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	11657121	0	4
T4	31121	6041	0	0
T5	3571	854	0	0
T6	7859	0	0	0
T7	12360	0	0	0
T8	17991	0	0	0
T11	29727	12528	0	0
T14	16415	2074	0	0
T15	5970	1909	0	0
T16	6146	1025	0	0
T18	0	13789	0	0
T22	981	0	0	0
T33	0	4736	0	0
T36	0	1779	0	0
T41	0	15	0	0
T73	0	0	0	1
T74	0	0	0	1
T75	0	0	0	1
T76	0	0	0	1

FlashRmaStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	477182	0	11
T2	2661	28	0	0
T3	1066	0	0	0
T4	31121	0	0	0
T5	3571	0	0	0
T6	7859	0	0	0
T7	12360	0	0	0
T8	17991	0	0	0
T11	29727	0	0	0
T12	1274	0	0	0
T13	1016	0	0	0
T16	0	210	0	0
T18	0	376	0	0
T21	0	1194	0	0
T33	0	701	0	0
T34	0	949	0	0
T37	0	1096	0	0
T38	0	43	0	0
T39	0	483	0	0
T46	0	0	0	1
T47	0	1137	0	0
T77	0	0	0	1
T78	0	0	0	1
T79	0	0	0	1
T80	0	0	0	1
T81	0	0	0	1
T82	0	0	0	1
T83	0	0	0	1
T84	0	0	0	1
T85	0	0	0	1

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcCntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

NoClkBypInProdStates_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	7621748	0	0
T2	2661	228	0	0
T3	1066	0	0	0
T4	31121	8836	0	0
T5	3571	990	0	0
T6	7859	0	0	0
T7	12360	0	0	0
T8	17991	0	0	0
T11	29727	0	0	0
T12	1274	0	0	0
T13	1016	0	0	0
T15	0	218	0	0
T16	0	309	0	0
T17	0	5392	0	0
T18	0	3058	0	0
T33	0	1398	0	0
T36	0	630	0	0
T42	0	304	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	254006	0	2037
T2	2661	143	0	11
T3	1066	0	0	1
T4	31121	90	0	1
T5	3571	42	0	1
T6	7859	0	0	1
T7	12360	0	0	1
T8	17991	0	0	1
T11	29727	60	0	1
T12	1274	0	0	2
T13	1016	0	0	1
T14	0	18	0	0
T15	0	96	0	0
T16	0	114	0	0
T17	0	66	0	0
T18	0	426	0	0
T19	0	88	0	0

SecCmCFITerminal0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	8823641	0	0
T1	1059	780	0	0
T2	2661	608	0	0
T3	1066	0	0	0
T4	31121	7279	0	0
T5	3571	446	0	0
T6	7859	0	0	0
T7	12360	0	0	0
T11	29727	7239	0	0
T12	1274	1033	0	0
T13	1016	0	0	0
T14	0	2779	0	0
T15	0	989	0	0
T16	0	1516	0	0
T17	0	763	0	0

SecCmCFITerminal1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	47735	0	0
T20	30347	0	0	0
T33	22492	0	0	0
T34	26285	0	0	0
T37	19042	0	0	0
T39	25934	0	0	0
T40	31998	0	0	0
T41	17044	15	0	0
T42	3246	0	0	0
T45	0	516	0	0
T46	0	41	0	0
T60	15072	0	0	0
T62	0	4	0	0
T63	0	4	0	0
T66	0	4	0	0
T72	0	14	0	0
T86	0	38	0	0
T87	0	4	0	0
T88	0	2463	0	0
T89	784	0	0	0

SecCmCFITerminal2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	4641199	0	0
T4	31121	6056	0	0
T5	3571	861	0	0
T6	7859	0	0	0
T7	12360	0	0	0
T8	17991	0	0	0
T11	29727	6588	0	0
T14	16415	2077	0	0
T15	5970	1925	0	0
T16	6146	743	0	0
T18	0	13854	0	0
T22	981	0	0	0
T33	0	3181	0	0
T36	0	937	0	0
T60	0	5293	0	0

SecCmCFITerminal3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	6981732	0	0
T8	17991	0	0	0
T11	29727	5944	0	0
T14	16415	0	0	0
T15	5970	0	0	0
T16	6146	284	0	0
T17	33533	0	0	0
T18	31891	0	0	0
T22	981	0	0	0
T30	1328	0	0	0
T33	0	1579	0	0
T36	0	843	0	0
T47	0	4057	0	0
T53	0	2333	0	0
T60	0	3238	0	0
T90	0	531	0	0
T91	0	3656	0	0
T92	0	9963	0	0
T93	1850	0	0	0

u_cnt_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53137619	50236936	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	19211	18568	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

u_fsm_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56479171	53373354	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	27245	26433	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54746572	51841424	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		177	175	98.87
CONT_ASSIGN	126	1	1	100.00
ALWAYS	146	3	3	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	204	112	110	98.21
ALWAYS	584	3	3	100.00
ALWAYS	585	3	3	100.00
ALWAYS	586	3	3	100.00
ALWAYS	589	3	3	100.00
ALWAYS	608	5	5	100.00
CONT_ASSIGN	619	1	1	100.00
CONT_ASSIGN	666	1	1	100.00
CONT_ASSIGN	667	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
ALWAYS	677	15	15	100.00
ALWAYS	712	14	14	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	740	1	1	100.00
CONT_ASSIGN	742	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
ALWAYS	882	3	3	100.00

Click here to see the source line report.

---

Cond Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Total	Covered	Percent
Conditions	86	80	93.02
Logical	86	80	93.02
Non-Logical	0	0
Event	0	0

 LINE       251
 EXPRESSION (init_req_i && lc_state_valid_q)
             -----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T16,T36
1	1	Covered	T1,T2,T3

 LINE       284
 EXPRESSION (lc_state_q == LcStScrap)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T45,T46

 LINE       293
 EXPRESSION (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i)
             -----------1----------    ----------2----------    -----3-----

-1-	-2-	-3-	Status	Tests
-	0	1	Covered	T1,T2,T4
-	1	0	Covered	T1,T12,T6
-	1	1	Covered	T1,T12,T30

 LINE       295
 EXPRESSION ((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}) && ((!trans_invalid_error_o)))
             -----------1-----------    ----------------------------------------2---------------------------------------    -------------3------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T12,T30

 LINE       295
 SUB-EXPRESSION (lc_state_q == LcStRaw)
                -----------1-----------

-1-	Status	Tests
0	Covered	T12,T31,T32
1	Covered	T1,T12,T30

 LINE       295
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Covered	T12,T31,T32
1	Covered	T1,T12,T30

 LINE       299
 EXPRESSION (unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed)
            ----------------------------------1---------------------------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T12,T30

 LINE       305
 EXPRESSION ((lc_cnt_q == LcCnt0) ? LcCnt1 : lc_cnt_q)
             ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T12,T30
1	Excluded	T54	VC_COV_UNR

 LINE       305
 SUB-EXPRESSION (lc_cnt_q == LcCnt0)
                ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T12,T30
1	Excluded	T54	VC_COV_UNR

 LINE       411
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[1])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T33,T47,T21

 LINE       452
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T39,T40,T34
1	0	1	Covered	T21,T43,T44
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T11

 LINE       452
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T33,T39,T40
1	Covered	T1,T2,T11

 LINE       466
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T2,T16,T18

 LINE       493
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T11

 LINE       493
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T11

 LINE       496
 EXPRESSION (fsm_state_q == TokenCheck1St)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T1,T2,T11

 LINE       524
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[2])
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T49,T50,T51

 LINE       529
 EXPRESSION 
 Number  Term
      1  ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))) || 
      2  ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T11
0	1	Covered	T47,T50,T55
1	0	Covered	T52,T56,T57

 LINE       529
 SUB-EXPRESSION ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off)))
                 -----------------------------------1----------------------------------    --------------------------------2--------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T18
1	0	Covered	T1,T2,T11
1	1	Covered	T52,T56,T57

 LINE       529
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T2,T16,T18
1	Covered	T1,T2,T11

 LINE       529
 SUB-EXPRESSION ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))
                 -------------1-------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T11
0	1	Covered	T52,T56,T57
1	0	Not Covered

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_req_o != Off)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T2,T16,T18

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_ack_buf[2] != Off)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T2,T16,T18

 LINE       529
 SUB-EXPRESSION ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On)))
                 -----------------------------------1----------------------------------    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T2,T16,T18
1	1	Covered	T47,T50,T55

 LINE       529
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T2,T16,T18

 LINE       529
 SUB-EXPRESSION ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On))
                 -------------1------------    ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T16,T18
0	1	Covered	T47,T50,T55
1	0	Covered	T58,T59

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_req_o != On)
                -------------1------------

-1-	Status	Tests
0	Covered	T2,T16,T18
1	Covered	T1,T2,T11

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_ack_buf[2] != On)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T16,T18
1	Covered	T1,T2,T11

 LINE       567
 EXPRESSION (esc_scrap_state0_i || esc_scrap_state1_i)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T11
1	0	Covered	T4,T5,T11

 LINE       574
 EXPRESSION ((((|state_invalid_error)) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt))
             -----------------------1-----------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T16,T60
1	1	Covered	T11,T16,T36

 LINE       574
 SUB-EXPRESSION (((|state_invalid_error)) | token_if_fsm_err_i)
                 ------------1-----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T16,T60
1	0	Covered	T11,T16,T36

 LINE       574
 SUB-EXPRESSION (fsm_state_q != EscalateSt)
                -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T11
1	Covered	T1,T2,T3

 LINE       612
 SUB-EXPRESSION (set_strap_en_override || gen_strap_delay_regs.strap_en_override_q[0])
                 ----------1----------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T30
1	0	Covered	T1,T12,T30

 LINE       732
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[0]][trans_target_i[0]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       732
 SUB-EXPRESSION ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       736
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[1]][trans_target_i[1]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       736
 SUB-EXPRESSION ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable	T1,T2,T3
1	0	Unreachable	T7,T9,T61
1	1	Covered	T1,T2,T3

 LINE       749
 EXPRESSION (trans_invalid_error || (token_idx0 != token_idx1))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T39
1	0	Covered	T12,T21,T43

 LINE       749
 SUB-EXPRESSION (token_idx0 != token_idx1)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T39

---

FSM Coverage for Instance : tb.dut.u_lc_ctrl_fsm

Summary for FSM :: fsm_state_q

	Total	Covered	Percent
States	15	15	100.00	(Not included in score)
Transitions	35	35	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fsm_state_q

---

states	Line No.	Covered	Tests
ClkMuxSt	327	Covered	T1,T2,T4
CntIncrSt	385	Covered	T1,T2,T4
CntProgSt	401	Covered	T1,T2,T4
EscalateSt	568	Covered	T4,T5,T11
FlashRmaSt	455	Covered	T1,T2,T11
IdleSt	252	Covered	T1,T2,T3
InvalidSt	575	Covered	T11,T16,T36
PostTransSt	317	Covered	T1,T2,T12
ResetSt	246	Covered	T1,T2,T3
ScrapSt	285	Covered	T41,T45,T46
TokenCheck0St	469	Covered	T1,T2,T11
TokenCheck1St	501	Covered	T1,T2,T11
TokenHashSt	434	Covered	T1,T2,T11
TransCheckSt	423	Covered	T1,T2,T11
TransProgSt	499	Covered	T1,T2,T11

transitions	Line No.	Covered	Tests	Exclude Annotation
ClkMuxSt->CntIncrSt	385	Covered	T1,T2,T4
ClkMuxSt->EscalateSt	568	Covered	T62,T63,T64
ClkMuxSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntIncrSt->CntProgSt	401	Covered	T1,T2,T4
CntIncrSt->EscalateSt	568	Covered	T65,T62,T66
CntIncrSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntIncrSt->PostTransSt	399	Covered	T21,T43,T44
CntProgSt->EscalateSt	568	Covered	T18,T65,T62
CntProgSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntProgSt->PostTransSt	412	Covered	T4,T5,T14
CntProgSt->TransCheckSt	423	Covered	T1,T2,T11
EscalateSt->InvalidSt	575	Excluded		VC_COV_UNR
FlashRmaSt->EscalateSt	568	Covered	T18,T65,T62
FlashRmaSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
FlashRmaSt->TokenCheck0St	469	Covered	T1,T2,T11
IdleSt->ClkMuxSt	327	Covered	T1,T2,T4
IdleSt->EscalateSt	568	Covered	T18,T65,T62
IdleSt->InvalidSt	575	Covered	T11,T16,T36
IdleSt->PostTransSt	317	Covered	T12,T31,T32
IdleSt->ScrapSt	285	Covered	T41,T45,T46
InvalidSt->EscalateSt	568	Covered	T11,T16,T36
PostTransSt->EscalateSt	568	Covered	T4,T5,T14
PostTransSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
ResetSt->EscalateSt	568	Covered	T18,T65,T62
ResetSt->IdleSt	252	Covered	T1,T2,T3
ResetSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
ScrapSt->EscalateSt	568	Covered	T62,T66,T63
ScrapSt->InvalidSt	575	Covered	T67
TokenCheck0St->EscalateSt	568	Covered	T18,T65,T49
TokenCheck0St->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenCheck0St->PostTransSt	483	Covered	T33,T39,T34
TokenCheck0St->TokenCheck1St	501	Covered	T1,T2,T11
TokenCheck1St->EscalateSt	568	Covered	T18,T62,T66
TokenCheck1St->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenCheck1St->PostTransSt	483	Covered	T39,T34,T48
TokenCheck1St->TransProgSt	499	Covered	T1,T2,T11
TokenHashSt->EscalateSt	568	Covered	T18,T65,T62
TokenHashSt->FlashRmaSt	455	Covered	T1,T2,T11
TokenHashSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenHashSt->PostTransSt	457	Covered	T33,T39,T40
TransCheckSt->EscalateSt	568	Covered	T18,T62,T66
TransCheckSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TransCheckSt->PostTransSt	432	Covered	T39,T34,T21
TransCheckSt->TokenHashSt	434	Covered	T1,T2,T11
TransProgSt->EscalateSt	568	Covered	T18,T65,T62
TransProgSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TransProgSt->PostTransSt	525	Covered	T1,T2,T11

Summary for FSM :: lc_state_q

	Total	Covered	Percent
States	21	21	100.00	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_state_q

---

states	Line No.	Covered	Tests
LcStDev	92	Covered	T2,T4,T18
LcStProd	93	Covered	T2,T4,T5
LcStProdEnd	94	Covered	T2,T4,T5
LcStRaw	295	Covered	T1,T2,T12
LcStRma	333	Covered	T11,T18,T19
LcStScrap	284	Covered	T1,T2,T3
LcStTestLocked0	333	Covered	T5,T22,T17
LcStTestLocked1	333	Covered	T4,T11,T8
LcStTestLocked2	333	Covered	T4,T11,T14
LcStTestLocked3	333	Covered	T2,T11,T15
LcStTestLocked4	333	Covered	T2,T7,T15
LcStTestLocked5	333	Covered	T4,T17,T18
LcStTestLocked6	333	Covered	T2,T4,T5
LcStTestUnlocked0	301	Covered	T1,T2,T12
LcStTestUnlocked1	333	Covered	T4,T6,T11
LcStTestUnlocked2	333	Covered	T2,T5,T11
LcStTestUnlocked3	333	Covered	T2,T11,T15
LcStTestUnlocked4	333	Covered	T3,T4,T11
LcStTestUnlocked5	333	Covered	T4,T5,T15
LcStTestUnlocked6	333	Covered	T4,T16,T17
LcStTestUnlocked7	333	Covered	T4,T14,T15

transitions	Line No.	Covered	Tests
LcStRaw->LcStTestUnlocked0	301	Covered	T1,T12,T30

Summary for FSM :: lc_cnt_q

	Total	Covered	Percent
States	25	10	40.00	(Not included in score)
Transitions	1	1	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_cnt_q

---

states	Line No.	Covered	Tests
LcCnt0	305	Covered	T33,T34,T35
LcCnt1	305	Covered	T2,T4,T17
LcCnt10	112	Not Covered
LcCnt11	113	Not Covered
LcCnt12	114	Not Covered
LcCnt13	115	Not Covered
LcCnt14	116	Not Covered
LcCnt15	117	Not Covered
LcCnt16	118	Not Covered
LcCnt17	119	Not Covered
LcCnt18	120	Not Covered
LcCnt19	121	Not Covered
LcCnt2	104	Covered	T4,T11,T17
LcCnt20	122	Not Covered
LcCnt21	123	Not Covered
LcCnt22	124	Not Covered
LcCnt23	125	Not Covered
LcCnt24	126	Not Covered
LcCnt3	105	Covered	T2,T16,T18
LcCnt4	106	Covered	T1,T2,T4
LcCnt5	107	Covered	T15,T17,T18
LcCnt6	108	Covered	T12,T4,T5
LcCnt7	109	Covered	T4,T15,T18
LcCnt8	110	Covered	T15,T16,T18
LcCnt9	111	Covered	T3,T13,T4

transitions	Line No.	Covered	Tests
LcCnt0->LcCnt1	305	Covered	T68,T54,T69

---

Branch Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		73	72	98.63
TERNARY	732	1	1	100.00
TERNARY	736	1	1	100.00
CASE	242	44	43	97.73
IF	567	3	3	100.00
IF	584	2	2	100.00
IF	585	2	2	100.00
IF	586	2	2	100.00
IF	589	2	2	100.00
IF	684	2	2	100.00
IF	687	2	2	100.00
IF	691	2	2	100.00
IF	694	2	2	100.00
IF	698	2	2	100.00
IF	701	2	2	100.00
IF	882	2	2	100.00
IF	608	2	2	100.00

732          assign token_idx0 = (int'(dec_lc_state_o[0]) < NumLcStates &&
                                                                          
733                               int'(trans_target_i[0]) < NumLcStates) ?
                                                                         -1-  
                                                                         ==>  
                                                                         ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

736          assign token_idx1 = (int'(dec_lc_state_o[1]) < NumLcStates &&
                                                                          
737                               int'(trans_target_i[1]) < NumLcStates) ?
                                                                         -1-  
                                                                         ==>  
                                                                         ==> (Unreachable)  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable	T1,T2,T3

242            unique case (fsm_state_q)
                      -1-  
243              ///////////////////////////////////////////////////////////////////
244              // Wait here until OTP has initialized and the
245              // power manager sends an initialization request.
246              ResetSt: begin
247                init_done_o = 1'b0;
248                lc_clk_byp_req   = Off;
249                lc_flash_rma_req = Off;
250                lc_check_byp_en  = Off;
251                if (init_req_i && lc_state_valid_q) begin
                   -2-  
252                  fsm_state_d = IdleSt;
                     ==>
253                  // Fetch LC state vector from OTP.
254                  lc_state_d  = lc_state_i;
255                  lc_cnt_d    = lc_cnt_i;
256                end
                   MISSING_ELSE
                   ==>
257              end
258              ///////////////////////////////////////////////////////////////////
259              // Idle state where life cycle control signals are broadcast.
260              // Note that the life cycle signals are decoded and broadcast
261              // in the lc_ctrl_signal_decode submodule.
262              IdleSt: begin
263                idle_o = 1'b1;
264        
265                // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
266                // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
267                // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
268                // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
269                // ---------------------------------------------------------------
270                // Note that if the volatile unlock mechanism is available,
271                // we have to stop fetching the OTP value after a volatile unlock has succeeded.
272                // Otherwise we unconditionally fetch from OTP in this state.
273                if (!(SecVolatileRawUnlockEn && lc_state_q == LcStTestUnlocked0 && lc_cnt_q != LcCnt0) ||
                   -3-  
274                    prim_mubi_pkg::mubi8_test_false_loose(volatile_raw_unlock_success_q)) begin
275                  // Continuously fetch LC state vector from OTP.
276                  // The state is locked in once a transition is started.
277                  lc_state_d    = lc_state_i;
                     ==>
278                  lc_cnt_d      = lc_cnt_i;
279                end
                   MISSING_ELSE
                   ==>
280                // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
281        
282                // If the life cycle state is SCRAP, we move the FSM into a terminal
283                // SCRAP state that does not allow any transitions to be initiated anymore.
284                if (lc_state_q == LcStScrap) begin
                   -4-  
285                  fsm_state_d = ScrapSt;
                     ==>
286        
287                // ---------- VOLATILE_TEST_UNLOCKED CODE SECTION START ----------
288                // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE
289                // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED VIA
290                // SecVolatileRawUnlockEn AT COMPILETIME FOR PRODUCTION DEVICES.
291                // ---------------------------------------------------------------
292                // Only enter here if volatile RAW unlock is available and enabled.
293                end else if (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i) begin
                            -5-  
294                  // We only allow transitions from RAW -> TEST_UNLOCKED0
295                  if (lc_state_q == LcStRaw &&
                     -6-  
296                      trans_target_i == {DecLcStateNumRep{DecLcStTestUnlocked0}} &&
297                      !trans_invalid_error_o) begin
298                    // 128bit token check (without passing it through the KMAC)
299                    if (unhashed_token_i == RndCnstRawUnlockTokenHashed) begin
                       -7-  
300                      // We stay in Idle, but update the life cycle state register (volatile).
301                      lc_state_d = LcStTestUnlocked0;
302                      // If the count is 0, we set it to 1 - otherwise we just leave it as is so that the
303                      // register value is in sync with what has been programmed to OTP already (there may
304                      // have been unsuccessul raw unlock attempts before that already incremented it).
305                      lc_cnt_d = (lc_cnt_q == LcCnt0) ? LcCnt1 : lc_cnt_q;
                                                         -8-  
                                                         ==> (Excluded)  
                                                         ==>  
306                      // Re-sample the DFT straps in the pinmux.
307                      // This signal will be delayed by several cycles so that the LC_CTRL signals
308                      // have time to propagate.
309                      set_strap_en_override = 1'b1;
310                      // We have to remember that the transition was successful in order to correctly
311                      // disable the continuos sampling of the life cycle state vector coming from OTP.
312                      volatile_raw_unlock_success_d = prim_mubi_pkg::MuBi8True;
313                      // Indicate that the transition was successful.
314                      trans_success_o = 1'b1;
315                    end else begin
316                      token_invalid_error_o = 1'b1;
                         ==> (Excluded)
Exclude Annotation: VC_COV_UNR
317                      fsm_state_d = PostTransSt;
318                    end
319                  end else begin
320                    // Transition invalid error is set by lc_ctrl_state_transition module.
321                    fsm_state_d = PostTransSt;
                       ==>
322                  end
323                // ----------- VOLATILE_TEST_UNLOCKED CODE SECTION END -----------
324                // Initiate a transition. This will first increment the
325                // life cycle counter before hashing and checking the token.
326                end else if (trans_cmd_i) begin
                            -9-  
327                  fsm_state_d = ClkMuxSt;
                     ==>
328                end
                   MISSING_ELSE
                   ==>
329                // If we are in a non-PROD life cycle state, steer the clock mux if requested. This
330                // action is available in IdleSt so that the mux can be steered without having to initiate
331                // a life cycle transition. If a transition is initiated however, the life cycle controller
332                // will wait for the clock mux acknowledgement in the ClkMuxSt state before proceeding.
333                if (lc_state_q inside {LcStRaw,
                   -10-  
334                                       LcStTestLocked0,
335                                       LcStTestLocked1,
336                                       LcStTestLocked2,
337                                       LcStTestLocked3,
338                                       LcStTestLocked4,
339                                       LcStTestLocked5,
340                                       LcStTestLocked6,
341                                       LcStTestUnlocked0,
342                                       LcStTestUnlocked1,
343                                       LcStTestUnlocked2,
344                                       LcStTestUnlocked3,
345                                       LcStTestUnlocked4,
346                                       LcStTestUnlocked5,
347                                       LcStTestUnlocked6,
348                                       LcStTestUnlocked7,
349                                       LcStRma}) begin
350                  if (use_ext_clock_i) begin
                     -11-  
351                    lc_clk_byp_req = On;
                       ==>
352                  end
                     MISSING_ELSE
                     ==>
353                end
                   MISSING_ELSE
                   ==>
354              end
355              ///////////////////////////////////////////////////////////////////
356              // Clock mux state. If we are in RAW, TEST* or RMA, it is permissible
357              // to switch to an external clock source. If the bypass request is
358              // asserted, we have to wait until the clock mux and clock manager
359              // have switched the mux and the clock divider. Also, we disable the
360              // life cycle partition checks at this point since we are going to
361              // alter the contents in the OTP memory array, which could lead to
362              // spurious escalations.
363              ClkMuxSt: begin
364                lc_check_byp_en = On;
365                if (lc_state_q inside {LcStRaw,
                   -12-  
366                                       LcStTestLocked0,
367                                       LcStTestLocked1,
368                                       LcStTestLocked2,
369                                       LcStTestLocked3,
370                                       LcStTestLocked4,
371                                       LcStTestLocked5,
372                                       LcStTestLocked6,
373                                       LcStTestUnlocked0,
374                                       LcStTestUnlocked1,
375                                       LcStTestUnlocked2,
376                                       LcStTestUnlocked3,
377                                       LcStTestUnlocked4,
378                                       LcStTestUnlocked5,
379                                       LcStTestUnlocked6,
380                                       LcStTestUnlocked7,
381                                       LcStRma}) begin
382                  if (use_ext_clock_i) begin
                     -13-  
383                    lc_clk_byp_req = On;
384                    if (lc_tx_test_true_strict(lc_clk_byp_ack[0])) begin
                       -14-  
385                      fsm_state_d = CntIncrSt;
                         ==>
386                    end
                       MISSING_ELSE
                       ==>
387                  end else begin
388                    fsm_state_d = CntIncrSt;
                       ==>
389                  end
390                end else begin
391                  fsm_state_d = CntIncrSt;
                     ==>
392                end
393              end
394              ///////////////////////////////////////////////////////////////////
395              // This increments the life cycle counter state.
396              CntIncrSt: begin
397                // If the counter has reached the maximum, bail out.
398                if (trans_cnt_oflw_error_o) begin
                   -15-  
399                  fsm_state_d = PostTransSt;
                     ==>
400                end else begin
401                  fsm_state_d = CntProgSt;
                     ==>
402                end
403              end
404              ///////////////////////////////////////////////////////////////////
405              // This programs the life cycle counter state.
406              CntProgSt: begin
407                otp_prog_req_o = 1'b1;
408        
409                // If the clock mux has been steered, double check that this is still the case.
410                // Otherwise abort the transition operation.
411                if (lc_clk_byp_req_o != lc_clk_byp_ack[1]) begin
                   -16-  
412                    fsm_state_d = PostTransSt;
                       ==>
413                    otp_prog_error_o = 1'b1;
414                end
                   MISSING_ELSE
                   ==>
415        
416                // Check return value and abort if there
417                // was an error.
418                if (otp_prog_ack_i) begin
                   -17-  
419                  if (otp_prog_err_i) begin
                     -18-  
420                    fsm_state_d = PostTransSt;
                       ==>
421                    otp_prog_error_o = 1'b1;
422                  end else begin
423                    fsm_state_d = TransCheckSt;
                       ==>
424                  end
425                end
                   MISSING_ELSE
                   ==>
426              end
427              ///////////////////////////////////////////////////////////////////
428              // First transition valid check. This will be repeated several
429              // times below.
430              TransCheckSt: begin
431                if (trans_invalid_error_o) begin
                   -19-  
432                  fsm_state_d = PostTransSt;
                     ==>
433                end else begin
434                  fsm_state_d = TokenHashSt;
                     ==>
435                end
436              end
437              ///////////////////////////////////////////////////////////////////
438              // Hash and compare the token, no matter whether this transition
439              // is conditional or not. Unconditional transitions just use a known
440              // all-zero token value. That way, we always compare a hashed token
441              // and guarantee that no other control flow path exists that could
442              // bypass the token check.
443              // SEC_CM: TOKEN.DIGEST
444              TokenHashSt: begin
445                token_hash_req_o = 1'b1;
446                if (token_hash_ack_i) begin
                   -20-  
447                  // This is the first comparison.
448                  // The token is compared two more times further below.
449                  // Also note that conditional transitions won't be possible if the
450                  // corresponding token is not valid. This only applies to tokens stored in
451                  // OTP. I.e., these tokens first have to be provisioned, before they can be used.
452                  if (hashed_token_i == hashed_token_mux &&
                     -21-  
453                      !token_hash_err_i &&
454                      &hashed_token_valid_mux) begin
455                    fsm_state_d = FlashRmaSt;
                       ==>
456                  end else begin
457                    fsm_state_d = PostTransSt;
                       ==>
458                    token_invalid_error_o = 1'b1;
459                  end
460                end
                   MISSING_ELSE
                   ==>
461              end
462              ///////////////////////////////////////////////////////////////////
463              // Flash RMA state. Note that we check the flash response again
464              // two times later below.
465              FlashRmaSt: begin
466                if (trans_target_i == {DecLcStateNumRep{DecLcStRma}}) begin
                   -22-  
467                  lc_flash_rma_req = On;
468                  if (lc_tx_test_true_strict(lc_flash_rma_ack_buf[0])) begin
                     -23-  
469                    fsm_state_d = TokenCheck0St;
                       ==>
470                  end
                     MISSING_ELSE
                     ==>
471                end else begin
472                  fsm_state_d = TokenCheck0St;
                     ==>
473                end
474              end
475              ///////////////////////////////////////////////////////////////////
476              // Check again two times whether this transition and the hashed
477              // token are valid. Also check again whether the flash RMA
478              // response is valid.
479              // SEC_CM: TOKEN.DIGEST
480              TokenCheck0St,
481              TokenCheck1St: begin
482                if (trans_invalid_error_o) begin
                   -24-  
483                  fsm_state_d = PostTransSt;
                     ==>
484                end else begin
485                  // If any of these RMA are conditions are true,
486                  // all of them must be true at the same time.
487                  if ((trans_target_i != {DecLcStateNumRep{DecLcStRma}} &&
                     -25-  
488                       lc_tx_test_false_strict(lc_flash_rma_req_o) &&
489                       lc_tx_test_false_strict(lc_flash_rma_ack_buf[1])) ||
490                      (trans_target_i == {DecLcStateNumRep{DecLcStRma}} &&
491                       lc_tx_test_true_strict(lc_flash_rma_req_o) &&
492                       lc_tx_test_true_strict(lc_flash_rma_ack_buf[1]))) begin
493                    if (hashed_token_i == hashed_token_mux &&
                       -26-  
494                        !token_hash_err_i &&
495                        &hashed_token_valid_mux) begin
496                      if (fsm_state_q == TokenCheck1St) begin
                         -27-  
497                        // This is the only way we can get into the
498                        // programming state.
499                        fsm_state_d = TransProgSt;
                           ==>
500                      end else begin
501                        fsm_state_d = TokenCheck1St;
                           ==>
502                      end
503                    end else begin
504                      fsm_state_d = PostTransSt;
                         ==>
505                      token_invalid_error_o = 1'b1;
506                    end
507                  // The flash RMA process failed.
508                  end else begin
509                      fsm_state_d = PostTransSt;
                         ==>
510                      flash_rma_error_o = 1'b1;
511                  end
512                end
513              end
514              ///////////////////////////////////////////////////////////////////
515              // Initiate OTP transaction. Note that the concurrent
516              // LC state check is continuously checking whether the
517              // new LC state remains valid. Once the ack returns we are
518              // done with the transition and can go into the terminal PosTransSt.
519              TransProgSt: begin
520                otp_prog_req_o = 1'b1;
521        
522                // If the clock mux has been steered, double check that this is still the case.
523                // Otherwise abort the transition operation.
524                if (lc_clk_byp_req_o != lc_clk_byp_ack[2]) begin
                   -28-  
525                  fsm_state_d = PostTransSt;
                     ==>
526                  otp_prog_error_o = 1'b1;
527                // Also double check that the RMA signals remain stable.
528                // Otherwise abort the transition operation.
529                end else if ((trans_target_i != {DecLcStateNumRep{DecLcStRma}} &&
                            -29-  
530                              (lc_flash_rma_req_o != Off || lc_flash_rma_ack_buf[2] != Off)) ||
531                             (trans_target_i == {DecLcStateNumRep{DecLcStRma}} &&
532                              (lc_flash_rma_req_o != On || lc_flash_rma_ack_buf[2] != On))) begin
533                  fsm_state_d = PostTransSt;
                     ==>
534                  flash_rma_error_o = 1'b1;
535                end else if (otp_prog_ack_i) begin
                            -30-  
536                  fsm_state_d = PostTransSt;
                     ==>
537                  otp_prog_error_o = otp_prog_err_i;
538                  trans_success_o  = ~otp_prog_err_i;
539                end
                   MISSING_ELSE
                   ==>
540              end
541              ///////////////////////////////////////////////////////////////////
542              // Terminal states.
543              ScrapSt,
544              PostTransSt: ;
                 ==>
545        
546        
547              EscalateSt: begin
548                // During an escalation it is okay to de-assert token_hash_req without receivng ACK.
549                token_hash_req_chk_o = 1'b0;
                   ==>
550              end
551        
552              InvalidSt: begin
553                // During an escalation it is okay to de-assert token_hash_req without receivng ACK.
554                token_hash_req_chk_o = 1'b0;
                   ==>
555                state_invalid_error_o = 1'b1;
556              end
557              ///////////////////////////////////////////////////////////////////
558              // Go to terminal error state if we get here.
559              default: begin
560                fsm_state_d = InvalidSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	Status	Tests	Exclude Annotation
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T30
IdleSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T41,T45,T46
IdleSt	-	-	0	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded	T54	VC_COV_UNR
IdleSt	-	-	0	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T30
IdleSt	-	-	0	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IdleSt	-	-	0	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T31,T32
IdleSt	-	-	0	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	0	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T17
IdleSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T17,T30
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T17,T30
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T43,T44
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T33,T47,T21
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T14
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T39,T34,T21
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	Covered	T33,T39,T40
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	Covered	T2,T16,T18
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	Covered	T2,T16,T18
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T39,T34,T48
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	1	-	-	-	Covered	T1,T2,T11
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	0	-	-	-	Covered	T1,T2,T11
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T33,T47,T21
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T49,T50,T51
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T47,T50,T52
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	Covered	T1,T2,T11
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	Covered	T1,T2,T11
ScrapSt PostTransSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T12
EscalateSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T11
InvalidSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T16,T36
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T16,T36

567            if (esc_scrap_state0_i || esc_scrap_state1_i) begin
               -1-  
568              fsm_state_d = EscalateSt;
                 ==>
569            // SEC_CM: MAIN.FSM.LOCAL_ESC
570            // If at any time the life cycle state encoding or any other FSM state within this module
571            // is not valid, we jump into the terminal error state right away.
572            // Note that state_invalid_error is a multibit error signal
573            // with different error sources - need to reduce this to one bit here.
574            end else if ((|state_invalid_error | token_if_fsm_err_i) && (fsm_state_q != EscalateSt)) begin
                        -2-                                  
575              fsm_state_d = InvalidSt;
                 ==>
576              state_invalid_error_o = 1'b1;
577            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T11
0	1	Covered	T11,T16,T36
0	0	Covered	T1,T2,T3

584          `PRIM_FLOP_SPARSE_FSM(u_fsm_state_regs, fsm_state_d, fsm_state_q, fsm_state_e, ResetSt)
             -1-                                                                                       
             ==>                                                                                       
             ==>                                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

585          `PRIM_FLOP_SPARSE_FSM(u_state_regs, lc_state_d, lc_state_q, lc_state_e, LcStScrap)
             -1-                                                                                  
             ==>                                                                                  
             ==>                                                                                  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

586          `PRIM_FLOP_SPARSE_FSM(u_cnt_regs, lc_cnt_d, lc_cnt_q, lc_cnt_e, LcCnt24)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

589            if (!rst_ni) begin
               -1-  
590              lc_state_valid_q <= 1'b0;
                 ==>
591            end else begin
592              lc_state_valid_q <= lc_state_valid_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

684            if (lc_tx_test_true_strict(test_tokens_valid[0])) begin
               -1-  
685              hashed_tokens_lower[TestUnlockTokenIdx] = test_unlock_token_lower;
                 ==>
686            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T33,T47,T53

687            if (lc_tx_test_true_strict(test_tokens_valid[1])) begin
               -1-  
688              hashed_tokens_upper[TestUnlockTokenIdx] = test_unlock_token_upper;
                 ==>
689            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T33,T47,T53

691            if (lc_tx_test_true_strict(test_tokens_valid[2])) begin
               -1-  
692              hashed_tokens_lower[TestExitTokenIdx] = test_exit_token_lower;
                 ==>
693            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T33,T47,T53

694            if (lc_tx_test_true_strict(test_tokens_valid[3])) begin
               -1-  
695              hashed_tokens_upper[TestExitTokenIdx] = test_exit_token_upper;
                 ==>
696            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T33,T47,T53

698            if (lc_tx_test_true_strict(rma_token_valid[0])) begin
               -1-  
699              hashed_tokens_lower[RmaTokenIdx] = rma_token_lower;
                 ==>
700            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T33,T47,T53

701            if (lc_tx_test_true_strict(rma_token_valid[1])) begin
               -1-  
702              hashed_tokens_upper[RmaTokenIdx] = rma_token_upper;
                 ==>
703            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T33,T47,T53

882          `ASSERT_FPV_LINEAR_FSM(SecCmCFILinear_A, fsm_state_q, fsm_state_e)
             -1-                                                                  
             ==>                                                                  
             ==>                                                                  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

608              if(!rst_ni) begin
                 -1-  
609                strap_en_override_q <= '0;
                   ==>
610                volatile_raw_unlock_success_q <= prim_mubi_pkg::MuBi8False;
611              end else begin
612                strap_en_override_q <= {strap_en_override_q[NumStrapDelayRegs-2:0],
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ClkBypStaysOnOnceAsserted_A	58101981	3157166	0	83
EscStaysOnOnceAsserted_A	58101981	11657121	0	4
FlashRmaStaysOnOnceAsserted_A	58101981	477182	0	11
FsmStateKnown_A	58101981	54873882	0	0
LcCntKnown_A	58101981	54873882	0	0
LcStateKnown_A	58101981	54873882	0	0
NoClkBypInProdStates_A	58101981	7621748	0	0
SecCmCFILinear_A	58101981	254006	0	2037
SecCmCFITerminal0_A	58101981	8823641	0	0
SecCmCFITerminal1_A	58101981	47735	0	0
SecCmCFITerminal2_A	58101981	4641199	0	0
SecCmCFITerminal3_A	58101981	6981732	0	0
u_cnt_regs_A	53137619	50236936	0	0
u_fsm_state_regs_A	56479171	53373354	0	0
u_state_regs_A	54746572	51841424	0	0

ClkBypStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	3157166	0	83
T2	2661	717	0	1
T3	1066	0	0	0
T4	31121	0	0	0
T5	3571	0	0	0
T6	7859	0	0	0
T7	12360	11666	0	1
T8	17991	0	0	0
T9	0	59240	0	1
T10	0	0	0	1
T11	29727	0	0	0
T12	1274	0	0	0
T13	1016	0	0	0
T17	0	9234	0	0
T19	0	1490	0	0
T23	0	0	0	1
T24	0	0	0	1
T30	0	1172	0	1
T37	0	3033	0	0
T45	0	4050	0	0
T46	0	415	0	0
T70	0	2110	0	1
T71	0	0	0	1
T72	0	0	0	1

EscStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	11657121	0	4
T4	31121	6041	0	0
T5	3571	854	0	0
T6	7859	0	0	0
T7	12360	0	0	0
T8	17991	0	0	0
T11	29727	12528	0	0
T14	16415	2074	0	0
T15	5970	1909	0	0
T16	6146	1025	0	0
T18	0	13789	0	0
T22	981	0	0	0
T33	0	4736	0	0
T36	0	1779	0	0
T41	0	15	0	0
T73	0	0	0	1
T74	0	0	0	1
T75	0	0	0	1
T76	0	0	0	1

FlashRmaStaysOnOnceAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	477182	0	11
T2	2661	28	0	0
T3	1066	0	0	0
T4	31121	0	0	0
T5	3571	0	0	0
T6	7859	0	0	0
T7	12360	0	0	0
T8	17991	0	0	0
T11	29727	0	0	0
T12	1274	0	0	0
T13	1016	0	0	0
T16	0	210	0	0
T18	0	376	0	0
T21	0	1194	0	0
T33	0	701	0	0
T34	0	949	0	0
T37	0	1096	0	0
T38	0	43	0	0
T39	0	483	0	0
T46	0	0	0	1
T47	0	1137	0	0
T77	0	0	0	1
T78	0	0	0	1
T79	0	0	0	1
T80	0	0	0	1
T81	0	0	0	1
T82	0	0	0	1
T83	0	0	0	1
T84	0	0	0	1
T85	0	0	0	1

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcCntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

LcStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	54873882	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

NoClkBypInProdStates_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	7621748	0	0
T2	2661	228	0	0
T3	1066	0	0	0
T4	31121	8836	0	0
T5	3571	990	0	0
T6	7859	0	0	0
T7	12360	0	0	0
T8	17991	0	0	0
T11	29727	0	0	0
T12	1274	0	0	0
T13	1016	0	0	0
T15	0	218	0	0
T16	0	309	0	0
T17	0	5392	0	0
T18	0	3058	0	0
T33	0	1398	0	0
T36	0	630	0	0
T42	0	304	0	0

SecCmCFILinear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	254006	0	2037
T2	2661	143	0	11
T3	1066	0	0	1
T4	31121	90	0	1
T5	3571	42	0	1
T6	7859	0	0	1
T7	12360	0	0	1
T8	17991	0	0	1
T11	29727	60	0	1
T12	1274	0	0	2
T13	1016	0	0	1
T14	0	18	0	0
T15	0	96	0	0
T16	0	114	0	0
T17	0	66	0	0
T18	0	426	0	0
T19	0	88	0	0

SecCmCFITerminal0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	8823641	0	0
T1	1059	780	0	0
T2	2661	608	0	0
T3	1066	0	0	0
T4	31121	7279	0	0
T5	3571	446	0	0
T6	7859	0	0	0
T7	12360	0	0	0
T11	29727	7239	0	0
T12	1274	1033	0	0
T13	1016	0	0	0
T14	0	2779	0	0
T15	0	989	0	0
T16	0	1516	0	0
T17	0	763	0	0

SecCmCFITerminal1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	47735	0	0
T20	30347	0	0	0
T33	22492	0	0	0
T34	26285	0	0	0
T37	19042	0	0	0
T39	25934	0	0	0
T40	31998	0	0	0
T41	17044	15	0	0
T42	3246	0	0	0
T45	0	516	0	0
T46	0	41	0	0
T60	15072	0	0	0
T62	0	4	0	0
T63	0	4	0	0
T66	0	4	0	0
T72	0	14	0	0
T86	0	38	0	0
T87	0	4	0	0
T88	0	2463	0	0
T89	784	0	0	0

SecCmCFITerminal2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	4641199	0	0
T4	31121	6056	0	0
T5	3571	861	0	0
T6	7859	0	0	0
T7	12360	0	0	0
T8	17991	0	0	0
T11	29727	6588	0	0
T14	16415	2077	0	0
T15	5970	1925	0	0
T16	6146	743	0	0
T18	0	13854	0	0
T22	981	0	0	0
T33	0	3181	0	0
T36	0	937	0	0
T60	0	5293	0	0

SecCmCFITerminal3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58101981	6981732	0	0
T8	17991	0	0	0
T11	29727	5944	0	0
T14	16415	0	0	0
T15	5970	0	0	0
T16	6146	284	0	0
T17	33533	0	0	0
T18	31891	0	0	0
T22	981	0	0	0
T30	1328	0	0	0
T33	0	1579	0	0
T36	0	843	0	0
T47	0	4057	0	0
T53	0	2333	0	0
T60	0	3238	0	0
T90	0	531	0	0
T91	0	3656	0	0
T92	0	9963	0	0
T93	1850	0	0	0

u_cnt_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53137619	50236936	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	19211	18568	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

u_fsm_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56479171	53373354	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	27245	26433	0	0
T12	1274	1183	0	0
T13	1016	924	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54746572	51841424	0	0
T1	1059	972	0	0
T2	2661	1683	0	0
T3	1066	972	0	0
T4	31121	29868	0	0
T5	3571	3008	0	0
T6	7859	7763	0	0
T7	12360	12291	0	0
T11	29727	28830	0	0
T12	1274	1183	0	0
T13	1016	924	0	0