| T362 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.530359162 |
|
|
Oct 15 11:32:11 AM UTC 24 |
Oct 15 11:32:20 AM UTC 24 |
1179242829 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.3296622844 |
|
|
Oct 15 11:30:46 AM UTC 24 |
Oct 15 11:32:21 AM UTC 24 |
10565464781 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.2923992005 |
|
|
Oct 15 11:32:11 AM UTC 24 |
Oct 15 11:32:21 AM UTC 24 |
280332290 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.2722556956 |
|
|
Oct 15 11:32:11 AM UTC 24 |
Oct 15 11:32:21 AM UTC 24 |
413161795 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.340871328 |
|
|
Oct 15 11:32:12 AM UTC 24 |
Oct 15 11:32:23 AM UTC 24 |
900768521 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.3953640230 |
|
|
Oct 15 11:32:46 AM UTC 24 |
Oct 15 11:32:59 AM UTC 24 |
633928193 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2687225106 |
|
|
Oct 15 11:32:21 AM UTC 24 |
Oct 15 11:32:24 AM UTC 24 |
15275062 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.2617003083 |
|
|
Oct 15 11:32:21 AM UTC 24 |
Oct 15 11:32:24 AM UTC 24 |
173566796 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.1712064796 |
|
|
Oct 15 11:32:03 AM UTC 24 |
Oct 15 11:32:25 AM UTC 24 |
3691228355 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.332119541 |
|
|
Oct 15 11:32:21 AM UTC 24 |
Oct 15 11:32:25 AM UTC 24 |
120944210 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.618039581 |
|
|
Oct 15 11:31:37 AM UTC 24 |
Oct 15 11:32:26 AM UTC 24 |
5260393484 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.3686074779 |
|
|
Oct 15 11:31:50 AM UTC 24 |
Oct 15 11:32:27 AM UTC 24 |
1933798248 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.841747799 |
|
|
Oct 15 11:32:23 AM UTC 24 |
Oct 15 11:32:27 AM UTC 24 |
46037864 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.1431269473 |
|
|
Oct 15 11:32:01 AM UTC 24 |
Oct 15 11:32:27 AM UTC 24 |
717492321 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.3908275856 |
|
|
Oct 15 11:32:23 AM UTC 24 |
Oct 15 11:32:27 AM UTC 24 |
99822424 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.2229024620 |
|
|
Oct 15 11:32:16 AM UTC 24 |
Oct 15 11:32:28 AM UTC 24 |
1223903937 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.2929559389 |
|
|
Oct 15 11:32:12 AM UTC 24 |
Oct 15 11:32:29 AM UTC 24 |
430687174 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.651533142 |
|
|
Oct 15 11:32:37 AM UTC 24 |
Oct 15 11:32:59 AM UTC 24 |
1339238436 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.3043951705 |
|
|
Oct 15 11:32:16 AM UTC 24 |
Oct 15 11:32:30 AM UTC 24 |
343796072 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3760004205 |
|
|
Oct 15 11:31:39 AM UTC 24 |
Oct 15 11:32:30 AM UTC 24 |
8199538356 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.2870765298 |
|
|
Oct 15 11:32:26 AM UTC 24 |
Oct 15 11:32:32 AM UTC 24 |
525185453 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.3567570813 |
|
|
Oct 15 11:31:57 AM UTC 24 |
Oct 15 11:32:32 AM UTC 24 |
1426117739 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.3230584289 |
|
|
Oct 15 11:32:30 AM UTC 24 |
Oct 15 11:32:33 AM UTC 24 |
338910551 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.4162983135 |
|
|
Oct 15 11:32:19 AM UTC 24 |
Oct 15 11:32:33 AM UTC 24 |
369062844 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.4094619246 |
|
|
Oct 15 11:32:25 AM UTC 24 |
Oct 15 11:32:33 AM UTC 24 |
2422046414 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.4047776879 |
|
|
Oct 15 11:32:31 AM UTC 24 |
Oct 15 11:32:34 AM UTC 24 |
32281898 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.741275325 |
|
|
Oct 15 11:31:45 AM UTC 24 |
Oct 15 11:32:34 AM UTC 24 |
1971928623 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.2138503478 |
|
|
Oct 15 11:30:20 AM UTC 24 |
Oct 15 11:32:35 AM UTC 24 |
6779767167 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.3999366813 |
|
|
Oct 15 11:32:25 AM UTC 24 |
Oct 15 11:32:35 AM UTC 24 |
743172984 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.2602775644 |
|
|
Oct 15 11:32:27 AM UTC 24 |
Oct 15 11:32:36 AM UTC 24 |
1996760225 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.370656613 |
|
|
Oct 15 11:32:31 AM UTC 24 |
Oct 15 11:32:36 AM UTC 24 |
127514068 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.2605161808 |
|
|
Oct 15 11:32:44 AM UTC 24 |
Oct 15 11:32:58 AM UTC 24 |
317489279 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.3326766435 |
|
|
Oct 15 11:32:37 AM UTC 24 |
Oct 15 11:33:01 AM UTC 24 |
764706576 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.842586078 |
|
|
Oct 15 11:32:25 AM UTC 24 |
Oct 15 11:32:36 AM UTC 24 |
1182329206 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.1325337650 |
|
|
Oct 15 11:31:54 AM UTC 24 |
Oct 15 11:33:04 AM UTC 24 |
4794117947 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.3609050583 |
|
|
Oct 15 11:32:27 AM UTC 24 |
Oct 15 11:32:38 AM UTC 24 |
195601486 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.1852299572 |
|
|
Oct 15 11:32:33 AM UTC 24 |
Oct 15 11:32:39 AM UTC 24 |
55189694 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.2669358103 |
|
|
Oct 15 11:32:55 AM UTC 24 |
Oct 15 11:32:59 AM UTC 24 |
228871282 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.4130031029 |
|
|
Oct 15 11:31:10 AM UTC 24 |
Oct 15 11:32:40 AM UTC 24 |
3496593118 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.2051568976 |
|
|
Oct 15 11:31:36 AM UTC 24 |
Oct 15 11:32:41 AM UTC 24 |
5315965432 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.3806396088 |
|
|
Oct 15 11:32:08 AM UTC 24 |
Oct 15 11:32:41 AM UTC 24 |
354143194 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.1268084746 |
|
|
Oct 15 11:32:29 AM UTC 24 |
Oct 15 11:32:41 AM UTC 24 |
857378421 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.1783894508 |
|
|
Oct 15 11:32:29 AM UTC 24 |
Oct 15 11:32:42 AM UTC 24 |
889879929 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.1794334030 |
|
|
Oct 15 11:32:40 AM UTC 24 |
Oct 15 11:32:43 AM UTC 24 |
43871813 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1572116668 |
|
|
Oct 15 11:32:42 AM UTC 24 |
Oct 15 11:32:44 AM UTC 24 |
58908187 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.2893871587 |
|
|
Oct 15 11:32:23 AM UTC 24 |
Oct 15 11:32:44 AM UTC 24 |
530903191 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.4066128616 |
|
|
Oct 15 11:32:43 AM UTC 24 |
Oct 15 11:32:59 AM UTC 24 |
3637918829 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.3438429019 |
|
|
Oct 15 11:32:34 AM UTC 24 |
Oct 15 11:32:45 AM UTC 24 |
317987308 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.657892711 |
|
|
Oct 15 11:32:36 AM UTC 24 |
Oct 15 11:32:45 AM UTC 24 |
394249959 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.489483168 |
|
|
Oct 15 11:32:33 AM UTC 24 |
Oct 15 11:32:46 AM UTC 24 |
213652863 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.732191988 |
|
|
Oct 15 11:32:34 AM UTC 24 |
Oct 15 11:32:47 AM UTC 24 |
1680773910 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.4116513111 |
|
|
Oct 15 11:32:42 AM UTC 24 |
Oct 15 11:32:47 AM UTC 24 |
68487637 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.2863656145 |
|
|
Oct 15 11:32:42 AM UTC 24 |
Oct 15 11:32:47 AM UTC 24 |
52185928 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.30883505 |
|
|
Oct 15 11:32:37 AM UTC 24 |
Oct 15 11:32:49 AM UTC 24 |
1063835079 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.3089541816 |
|
|
Oct 15 11:32:43 AM UTC 24 |
Oct 15 11:32:49 AM UTC 24 |
135966770 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_errors.761465942 |
|
|
Oct 15 11:32:34 AM UTC 24 |
Oct 15 11:32:50 AM UTC 24 |
1169061645 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.541173490 |
|
|
Oct 15 11:32:37 AM UTC 24 |
Oct 15 11:32:50 AM UTC 24 |
212175346 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.2878261517 |
|
|
Oct 15 11:32:11 AM UTC 24 |
Oct 15 11:32:52 AM UTC 24 |
1528160794 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.2789491215 |
|
|
Oct 15 11:32:26 AM UTC 24 |
Oct 15 11:32:53 AM UTC 24 |
1662742993 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.4124532935 |
|
|
Oct 15 11:32:44 AM UTC 24 |
Oct 15 11:32:54 AM UTC 24 |
451627795 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.1227135356 |
|
|
Oct 15 11:32:36 AM UTC 24 |
Oct 15 11:32:54 AM UTC 24 |
2218900890 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.3204190458 |
|
|
Oct 15 11:32:52 AM UTC 24 |
Oct 15 11:32:55 AM UTC 24 |
35787844 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3640352752 |
|
|
Oct 15 11:32:53 AM UTC 24 |
Oct 15 11:32:55 AM UTC 24 |
60771156 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.2468699378 |
|
|
Oct 15 11:32:31 AM UTC 24 |
Oct 15 11:32:58 AM UTC 24 |
1523314874 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.775067960 |
|
|
Oct 15 11:32:02 AM UTC 24 |
Oct 15 11:33:01 AM UTC 24 |
18976282617 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.1980940469 |
|
|
Oct 15 11:32:52 AM UTC 24 |
Oct 15 11:33:04 AM UTC 24 |
375576029 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.3010329524 |
|
|
Oct 15 11:32:55 AM UTC 24 |
Oct 15 11:33:05 AM UTC 24 |
82716830 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.3027117849 |
|
|
Oct 15 11:32:48 AM UTC 24 |
Oct 15 11:33:05 AM UTC 24 |
408399945 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.2448407579 |
|
|
Oct 15 11:32:25 AM UTC 24 |
Oct 15 11:33:06 AM UTC 24 |
7504798609 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.1890922906 |
|
|
Oct 15 11:32:15 AM UTC 24 |
Oct 15 11:33:06 AM UTC 24 |
9229101704 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.1887950413 |
|
|
Oct 15 11:32:42 AM UTC 24 |
Oct 15 11:33:07 AM UTC 24 |
1995934499 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.1943949246 |
|
|
Oct 15 11:32:48 AM UTC 24 |
Oct 15 11:33:07 AM UTC 24 |
5421343873 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.3391482071 |
|
|
Oct 15 11:32:48 AM UTC 24 |
Oct 15 11:33:08 AM UTC 24 |
526116192 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.591655958 |
|
|
Oct 15 11:32:36 AM UTC 24 |
Oct 15 11:33:08 AM UTC 24 |
7503600348 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.3323542232 |
|
|
Oct 15 11:33:01 AM UTC 24 |
Oct 15 11:33:08 AM UTC 24 |
697660364 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.739512854 |
|
|
Oct 15 11:32:55 AM UTC 24 |
Oct 15 11:33:09 AM UTC 24 |
3864215145 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.2779751779 |
|
|
Oct 15 11:33:00 AM UTC 24 |
Oct 15 11:33:09 AM UTC 24 |
462445186 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2431974573 |
|
|
Oct 15 11:33:07 AM UTC 24 |
Oct 15 11:33:09 AM UTC 24 |
13015109 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.3455922426 |
|
|
Oct 15 11:33:07 AM UTC 24 |
Oct 15 11:33:09 AM UTC 24 |
44302451 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.1683017354 |
|
|
Oct 15 11:33:07 AM UTC 24 |
Oct 15 11:33:10 AM UTC 24 |
142587171 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.2227163336 |
|
|
Oct 15 11:32:46 AM UTC 24 |
Oct 15 11:33:10 AM UTC 24 |
999974583 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.1840242711 |
|
|
Oct 15 11:31:44 AM UTC 24 |
Oct 15 11:33:11 AM UTC 24 |
2274232880 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.2945032857 |
|
|
Oct 15 11:31:00 AM UTC 24 |
Oct 15 11:33:11 AM UTC 24 |
8263717487 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.197332428 |
|
|
Oct 15 11:33:09 AM UTC 24 |
Oct 15 11:33:12 AM UTC 24 |
56992534 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.3136910588 |
|
|
Oct 15 11:32:56 AM UTC 24 |
Oct 15 11:33:12 AM UTC 24 |
990544702 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.1693367090 |
|
|
Oct 15 11:33:02 AM UTC 24 |
Oct 15 11:33:13 AM UTC 24 |
627744451 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.2761524697 |
|
|
Oct 15 11:33:11 AM UTC 24 |
Oct 15 11:33:15 AM UTC 24 |
66165416 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.3931668395 |
|
|
Oct 15 11:33:05 AM UTC 24 |
Oct 15 11:33:16 AM UTC 24 |
1742483584 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.108541827 |
|
|
Oct 15 11:33:00 AM UTC 24 |
Oct 15 11:33:17 AM UTC 24 |
501009773 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.440860826 |
|
|
Oct 15 11:33:02 AM UTC 24 |
Oct 15 11:33:17 AM UTC 24 |
884899266 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.3972604484 |
|
|
Oct 15 11:33:15 AM UTC 24 |
Oct 15 11:33:18 AM UTC 24 |
69344378 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.4141597720 |
|
|
Oct 15 11:33:09 AM UTC 24 |
Oct 15 11:33:18 AM UTC 24 |
787558398 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.2356548029 |
|
|
Oct 15 11:32:01 AM UTC 24 |
Oct 15 11:33:18 AM UTC 24 |
2100745276 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.3960768985 |
|
|
Oct 15 11:33:10 AM UTC 24 |
Oct 15 11:33:20 AM UTC 24 |
194430405 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1812672989 |
|
|
Oct 15 11:33:18 AM UTC 24 |
Oct 15 11:33:20 AM UTC 24 |
41540293 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.1796884718 |
|
|
Oct 15 11:33:18 AM UTC 24 |
Oct 15 11:33:21 AM UTC 24 |
248133865 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.3987915317 |
|
|
Oct 15 11:33:19 AM UTC 24 |
Oct 15 11:33:23 AM UTC 24 |
46581610 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.2412196934 |
|
|
Oct 15 11:33:10 AM UTC 24 |
Oct 15 11:33:23 AM UTC 24 |
239918982 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.3123855501 |
|
|
Oct 15 11:32:47 AM UTC 24 |
Oct 15 11:33:24 AM UTC 24 |
1585160616 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.867436810 |
|
|
Oct 15 11:33:10 AM UTC 24 |
Oct 15 11:33:24 AM UTC 24 |
2595211962 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.1740937737 |
|
|
Oct 15 11:32:54 AM UTC 24 |
Oct 15 11:33:24 AM UTC 24 |
320269179 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.1436133327 |
|
|
Oct 15 11:33:13 AM UTC 24 |
Oct 15 11:33:25 AM UTC 24 |
1107605715 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.2381458653 |
|
|
Oct 15 11:33:09 AM UTC 24 |
Oct 15 11:33:27 AM UTC 24 |
3640423263 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.2124251347 |
|
|
Oct 15 11:33:13 AM UTC 24 |
Oct 15 11:33:28 AM UTC 24 |
601873209 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.2788871736 |
|
|
Oct 15 11:33:13 AM UTC 24 |
Oct 15 11:33:28 AM UTC 24 |
371822584 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.1598584429 |
|
|
Oct 15 11:33:01 AM UTC 24 |
Oct 15 11:33:28 AM UTC 24 |
4358434276 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.3087087919 |
|
|
Oct 15 11:33:10 AM UTC 24 |
Oct 15 11:33:28 AM UTC 24 |
423453544 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.135223475 |
|
|
Oct 15 11:33:21 AM UTC 24 |
Oct 15 11:33:29 AM UTC 24 |
1880657537 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.3822862904 |
|
|
Oct 15 11:33:21 AM UTC 24 |
Oct 15 11:33:30 AM UTC 24 |
298419362 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.2639628417 |
|
|
Oct 15 11:33:25 AM UTC 24 |
Oct 15 11:33:32 AM UTC 24 |
715478479 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1364618056 |
|
|
Oct 15 11:33:30 AM UTC 24 |
Oct 15 11:33:32 AM UTC 24 |
14918329 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.2320372920 |
|
|
Oct 15 11:33:30 AM UTC 24 |
Oct 15 11:33:33 AM UTC 24 |
91189761 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.907721915 |
|
|
Oct 15 11:33:19 AM UTC 24 |
Oct 15 11:33:33 AM UTC 24 |
160415803 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.1166823186 |
|
|
Oct 15 11:33:26 AM UTC 24 |
Oct 15 11:33:34 AM UTC 24 |
476912604 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.155543775 |
|
|
Oct 15 11:33:30 AM UTC 24 |
Oct 15 11:33:34 AM UTC 24 |
155166034 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.2080189689 |
|
|
Oct 15 11:32:45 AM UTC 24 |
Oct 15 11:33:35 AM UTC 24 |
2035457596 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.1610535545 |
|
|
Oct 15 11:33:19 AM UTC 24 |
Oct 15 11:33:35 AM UTC 24 |
436568762 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.2373853149 |
|
|
Oct 15 11:33:23 AM UTC 24 |
Oct 15 11:33:35 AM UTC 24 |
1717003757 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.4191725198 |
|
|
Oct 15 11:33:33 AM UTC 24 |
Oct 15 11:33:37 AM UTC 24 |
69681222 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.1239135850 |
|
|
Oct 15 11:33:33 AM UTC 24 |
Oct 15 11:33:39 AM UTC 24 |
404270015 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.732883007 |
|
|
Oct 15 11:33:34 AM UTC 24 |
Oct 15 11:33:41 AM UTC 24 |
114312423 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.3885135077 |
|
|
Oct 15 11:33:25 AM UTC 24 |
Oct 15 11:33:41 AM UTC 24 |
317673921 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.3508736480 |
|
|
Oct 15 11:33:28 AM UTC 24 |
Oct 15 11:33:43 AM UTC 24 |
1484606409 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.3212221947 |
|
|
Oct 15 11:33:18 AM UTC 24 |
Oct 15 11:33:43 AM UTC 24 |
364659346 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.3142286272 |
|
|
Oct 15 11:33:11 AM UTC 24 |
Oct 15 11:33:43 AM UTC 24 |
2576065695 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.2713341398 |
|
|
Oct 15 11:33:36 AM UTC 24 |
Oct 15 11:33:43 AM UTC 24 |
706006315 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.3041970567 |
|
|
Oct 15 11:33:08 AM UTC 24 |
Oct 15 11:33:43 AM UTC 24 |
1764829772 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.2893633405 |
|
|
Oct 15 11:33:34 AM UTC 24 |
Oct 15 11:33:46 AM UTC 24 |
682638813 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.2419966798 |
|
|
Oct 15 11:33:34 AM UTC 24 |
Oct 15 11:33:46 AM UTC 24 |
235732522 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.4098214728 |
|
|
Oct 15 11:33:45 AM UTC 24 |
Oct 15 11:33:47 AM UTC 24 |
83612848 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.410825533 |
|
|
Oct 15 11:33:45 AM UTC 24 |
Oct 15 11:33:47 AM UTC 24 |
19003601 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.1436852083 |
|
|
Oct 15 11:30:00 AM UTC 24 |
Oct 15 11:33:58 AM UTC 24 |
5955832671 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.85590868 |
|
|
Oct 15 11:33:45 AM UTC 24 |
Oct 15 11:33:50 AM UTC 24 |
80193213 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.3669263461 |
|
|
Oct 15 11:33:47 AM UTC 24 |
Oct 15 11:33:59 AM UTC 24 |
265220701 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.223148400 |
|
|
Oct 15 11:33:25 AM UTC 24 |
Oct 15 11:33:51 AM UTC 24 |
3935646658 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.204666350 |
|
|
Oct 15 11:33:42 AM UTC 24 |
Oct 15 11:33:51 AM UTC 24 |
508978909 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.2732647317 |
|
|
Oct 15 11:33:48 AM UTC 24 |
Oct 15 11:33:54 AM UTC 24 |
90479895 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.3757796821 |
|
|
Oct 15 11:33:23 AM UTC 24 |
Oct 15 11:33:55 AM UTC 24 |
4494280951 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.1286497061 |
|
|
Oct 15 11:31:55 AM UTC 24 |
Oct 15 11:33:55 AM UTC 24 |
9895874794 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.3202100900 |
|
|
Oct 15 11:33:42 AM UTC 24 |
Oct 15 11:33:56 AM UTC 24 |
869204444 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.3124076774 |
|
|
Oct 15 11:33:38 AM UTC 24 |
Oct 15 11:33:57 AM UTC 24 |
682177410 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.1181899993 |
|
|
Oct 15 11:33:55 AM UTC 24 |
Oct 15 11:33:58 AM UTC 24 |
39617789 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.2649781523 |
|
|
Oct 15 11:33:36 AM UTC 24 |
Oct 15 11:33:58 AM UTC 24 |
663754799 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.3465304204 |
|
|
Oct 15 11:33:51 AM UTC 24 |
Oct 15 11:33:58 AM UTC 24 |
525739271 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.1199459726 |
|
|
Oct 15 11:33:51 AM UTC 24 |
Oct 15 11:33:59 AM UTC 24 |
712081400 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.2151169390 |
|
|
Oct 15 11:34:16 AM UTC 24 |
Oct 15 11:34:48 AM UTC 24 |
5158452125 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.1356777210 |
|
|
Oct 15 11:32:36 AM UTC 24 |
Oct 15 11:33:59 AM UTC 24 |
24396954730 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1039073599 |
|
|
Oct 15 11:33:57 AM UTC 24 |
Oct 15 11:33:59 AM UTC 24 |
14077734 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.4223325049 |
|
|
Oct 15 11:33:57 AM UTC 24 |
Oct 15 11:34:00 AM UTC 24 |
32877985 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.2903840854 |
|
|
Oct 15 11:33:10 AM UTC 24 |
Oct 15 11:34:00 AM UTC 24 |
2464479929 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.3401866093 |
|
|
Oct 15 11:33:48 AM UTC 24 |
Oct 15 11:34:01 AM UTC 24 |
485358918 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.4074348669 |
|
|
Oct 15 11:33:00 AM UTC 24 |
Oct 15 11:34:01 AM UTC 24 |
2720861883 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.1211737560 |
|
|
Oct 15 11:33:31 AM UTC 24 |
Oct 15 11:34:01 AM UTC 24 |
931712352 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.3768537686 |
|
|
Oct 15 11:33:40 AM UTC 24 |
Oct 15 11:34:02 AM UTC 24 |
760905551 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.2660858419 |
|
|
Oct 15 11:33:59 AM UTC 24 |
Oct 15 11:34:04 AM UTC 24 |
172177103 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.4052525802 |
|
|
Oct 15 11:34:03 AM UTC 24 |
Oct 15 11:34:05 AM UTC 24 |
43695779 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.1912300595 |
|
|
Oct 15 11:34:02 AM UTC 24 |
Oct 15 11:34:05 AM UTC 24 |
125255949 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.1923399765 |
|
|
Oct 15 11:34:02 AM UTC 24 |
Oct 15 11:34:05 AM UTC 24 |
134319164 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.42598687 |
|
|
Oct 15 11:33:48 AM UTC 24 |
Oct 15 11:34:06 AM UTC 24 |
1080484712 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.2890994911 |
|
|
Oct 15 11:33:59 AM UTC 24 |
Oct 15 11:34:06 AM UTC 24 |
269126919 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.100065249 |
|
|
Oct 15 11:32:06 AM UTC 24 |
Oct 15 11:34:07 AM UTC 24 |
15610355596 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.2347831433 |
|
|
Oct 15 11:34:00 AM UTC 24 |
Oct 15 11:34:07 AM UTC 24 |
204305517 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.3936451939 |
|
|
Oct 15 11:33:52 AM UTC 24 |
Oct 15 11:34:08 AM UTC 24 |
925608621 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.1565222838 |
|
|
Oct 15 11:34:06 AM UTC 24 |
Oct 15 11:34:09 AM UTC 24 |
37183043 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.2267473220 |
|
|
Oct 15 11:33:59 AM UTC 24 |
Oct 15 11:34:09 AM UTC 24 |
544458232 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.610942365 |
|
|
Oct 15 11:33:59 AM UTC 24 |
Oct 15 11:34:10 AM UTC 24 |
1226811266 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.3111453502 |
|
|
Oct 15 11:33:22 AM UTC 24 |
Oct 15 11:34:10 AM UTC 24 |
1282399176 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.1150529254 |
|
|
Oct 15 11:34:32 AM UTC 24 |
Oct 15 11:34:49 AM UTC 24 |
1179916145 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.2241882230 |
|
|
Oct 15 11:34:06 AM UTC 24 |
Oct 15 11:34:11 AM UTC 24 |
106906030 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.2364626043 |
|
|
Oct 15 11:33:47 AM UTC 24 |
Oct 15 11:34:11 AM UTC 24 |
250291818 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.2432627153 |
|
|
Oct 15 11:34:10 AM UTC 24 |
Oct 15 11:34:12 AM UTC 24 |
19786147 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.3084317990 |
|
|
Oct 15 11:33:52 AM UTC 24 |
Oct 15 11:34:13 AM UTC 24 |
400836641 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.509048791 |
|
|
Oct 15 11:34:11 AM UTC 24 |
Oct 15 11:34:13 AM UTC 24 |
38603929 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.983023470 |
|
|
Oct 15 11:34:03 AM UTC 24 |
Oct 15 11:34:14 AM UTC 24 |
107877839 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.3117911385 |
|
|
Oct 15 11:34:10 AM UTC 24 |
Oct 15 11:34:14 AM UTC 24 |
58639782 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.814450604 |
|
|
Oct 15 11:33:06 AM UTC 24 |
Oct 15 11:34:14 AM UTC 24 |
2825654530 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.444990359 |
|
|
Oct 15 11:34:36 AM UTC 24 |
Oct 15 11:34:49 AM UTC 24 |
1022932602 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.1231037316 |
|
|
Oct 15 11:33:59 AM UTC 24 |
Oct 15 11:34:15 AM UTC 24 |
264651689 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.2178572721 |
|
|
Oct 15 11:34:00 AM UTC 24 |
Oct 15 11:34:16 AM UTC 24 |
546247350 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.4159013764 |
|
|
Oct 15 11:34:12 AM UTC 24 |
Oct 15 11:34:18 AM UTC 24 |
254583425 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.3372745628 |
|
|
Oct 15 11:34:15 AM UTC 24 |
Oct 15 11:34:18 AM UTC 24 |
348666806 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.2691861822 |
|
|
Oct 15 11:33:59 AM UTC 24 |
Oct 15 11:34:20 AM UTC 24 |
1606630761 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.3521181866 |
|
|
Oct 15 11:34:06 AM UTC 24 |
Oct 15 11:34:20 AM UTC 24 |
597915529 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.1318628286 |
|
|
Oct 15 11:34:17 AM UTC 24 |
Oct 15 11:34:20 AM UTC 24 |
23758538 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.1874286204 |
|
|
Oct 15 11:34:07 AM UTC 24 |
Oct 15 11:34:21 AM UTC 24 |
444319766 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.316229129 |
|
|
Oct 15 11:34:12 AM UTC 24 |
Oct 15 11:34:21 AM UTC 24 |
247183914 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3928908571 |
|
|
Oct 15 11:34:20 AM UTC 24 |
Oct 15 11:34:22 AM UTC 24 |
18934256 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.1309081970 |
|
|
Oct 15 11:34:06 AM UTC 24 |
Oct 15 11:34:22 AM UTC 24 |
1892986511 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.4038077981 |
|
|
Oct 15 11:34:07 AM UTC 24 |
Oct 15 11:34:24 AM UTC 24 |
1276387890 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.455855203 |
|
|
Oct 15 11:34:21 AM UTC 24 |
Oct 15 11:34:25 AM UTC 24 |
26772176 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.3146247458 |
|
|
Oct 15 11:34:15 AM UTC 24 |
Oct 15 11:34:25 AM UTC 24 |
1385063525 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.2370539379 |
|
|
Oct 15 11:34:12 AM UTC 24 |
Oct 15 11:34:26 AM UTC 24 |
685764048 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.1160420089 |
|
|
Oct 15 11:34:07 AM UTC 24 |
Oct 15 11:34:27 AM UTC 24 |
543038437 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.406270965 |
|
|
Oct 15 11:34:48 AM UTC 24 |
Oct 15 11:34:50 AM UTC 24 |
69772737 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.2393798529 |
|
|
Oct 15 11:34:18 AM UTC 24 |
Oct 15 11:34:28 AM UTC 24 |
1009169383 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.1652009609 |
|
|
Oct 15 11:34:15 AM UTC 24 |
Oct 15 11:34:28 AM UTC 24 |
228547720 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.1989583019 |
|
|
Oct 15 11:34:15 AM UTC 24 |
Oct 15 11:34:29 AM UTC 24 |
879925675 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.2178168629 |
|
|
Oct 15 11:33:58 AM UTC 24 |
Oct 15 11:34:30 AM UTC 24 |
271570766 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.392015567 |
|
|
Oct 15 11:34:28 AM UTC 24 |
Oct 15 11:34:31 AM UTC 24 |
35859131 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.1986087897 |
|
|
Oct 15 11:34:21 AM UTC 24 |
Oct 15 11:34:31 AM UTC 24 |
983233846 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.224859810 |
|
|
Oct 15 11:34:03 AM UTC 24 |
Oct 15 11:34:32 AM UTC 24 |
492891227 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.461760607 |
|
|
Oct 15 11:34:30 AM UTC 24 |
Oct 15 11:34:32 AM UTC 24 |
14044239 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.2490001019 |
|
|
Oct 15 11:34:25 AM UTC 24 |
Oct 15 11:34:34 AM UTC 24 |
683893320 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.1216940189 |
|
|
Oct 15 11:34:22 AM UTC 24 |
Oct 15 11:34:35 AM UTC 24 |
196835573 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.3239860406 |
|
|
Oct 15 11:34:23 AM UTC 24 |
Oct 15 11:34:35 AM UTC 24 |
358493383 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.1978347658 |
|
|
Oct 15 11:34:30 AM UTC 24 |
Oct 15 11:34:36 AM UTC 24 |
61298643 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.3187213315 |
|
|
Oct 15 11:34:33 AM UTC 24 |
Oct 15 11:34:36 AM UTC 24 |
50704527 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.1045988115 |
|
|
Oct 15 11:34:31 AM UTC 24 |
Oct 15 11:34:36 AM UTC 24 |
277368905 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.987009658 |
|
|
Oct 15 11:34:11 AM UTC 24 |
Oct 15 11:34:37 AM UTC 24 |
379971686 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.3547972002 |
|
|
Oct 15 11:34:30 AM UTC 24 |
Oct 15 11:34:37 AM UTC 24 |
698151229 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.3791029345 |
|
|
Oct 15 11:34:22 AM UTC 24 |
Oct 15 11:34:37 AM UTC 24 |
360889178 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.3966273938 |
|
|
Oct 15 11:32:27 AM UTC 24 |
Oct 15 11:34:37 AM UTC 24 |
7904259150 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.2114337457 |
|
|
Oct 15 11:33:01 AM UTC 24 |
Oct 15 11:34:38 AM UTC 24 |
33156929248 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.1292401322 |
|
|
Oct 15 11:34:37 AM UTC 24 |
Oct 15 11:34:40 AM UTC 24 |
67903232 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1900967258 |
|
|
Oct 15 11:34:37 AM UTC 24 |
Oct 15 11:34:40 AM UTC 24 |
12721630 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.2376061579 |
|
|
Oct 15 11:33:35 AM UTC 24 |
Oct 15 11:34:40 AM UTC 24 |
1584833700 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.1631543450 |
|
|
Oct 15 11:34:37 AM UTC 24 |
Oct 15 11:34:40 AM UTC 24 |
33665987 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.1178567297 |
|
|
Oct 15 11:34:23 AM UTC 24 |
Oct 15 11:34:42 AM UTC 24 |
1458756712 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.1821726640 |
|
|
Oct 15 11:34:40 AM UTC 24 |
Oct 15 11:34:50 AM UTC 24 |
465320714 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.1241668379 |
|
|
Oct 15 11:34:39 AM UTC 24 |
Oct 15 11:34:42 AM UTC 24 |
92629661 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.2190344546 |
|
|
Oct 15 11:34:26 AM UTC 24 |
Oct 15 11:34:43 AM UTC 24 |
1449912014 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.3645809155 |
|
|
Oct 15 11:34:44 AM UTC 24 |
Oct 15 11:34:46 AM UTC 24 |
246319315 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.2113714059 |
|
|
Oct 15 11:34:32 AM UTC 24 |
Oct 15 11:34:46 AM UTC 24 |
389439188 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.129448228 |
|
|
Oct 15 11:34:34 AM UTC 24 |
Oct 15 11:34:47 AM UTC 24 |
274749635 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.2467684631 |
|
|
Oct 15 11:34:39 AM UTC 24 |
Oct 15 11:34:51 AM UTC 24 |
276432752 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.311090790 |
|
|
Oct 15 11:34:48 AM UTC 24 |
Oct 15 11:34:51 AM UTC 24 |
40478148 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.414448334 |
|
|
Oct 15 11:34:01 AM UTC 24 |
Oct 15 11:34:51 AM UTC 24 |
1897707938 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.915353471 |
|
|
Oct 15 11:34:39 AM UTC 24 |
Oct 15 11:34:52 AM UTC 24 |
480474344 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.313739257 |
|
|
Oct 15 11:34:41 AM UTC 24 |
Oct 15 11:34:54 AM UTC 24 |
1363962708 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.1565576087 |
|
|
Oct 15 11:34:35 AM UTC 24 |
Oct 15 11:34:54 AM UTC 24 |
555943010 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.1579600327 |
|
|
Oct 15 11:34:30 AM UTC 24 |
Oct 15 11:34:55 AM UTC 24 |
209475010 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.259002476 |
|
|
Oct 15 11:34:41 AM UTC 24 |
Oct 15 11:34:55 AM UTC 24 |
12231887561 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.851992220 |
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|
Oct 15 11:34:49 AM UTC 24 |
Oct 15 11:34:56 AM UTC 24 |
73906164 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.2916923203 |
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|
Oct 15 11:34:50 AM UTC 24 |
Oct 15 11:34:56 AM UTC 24 |
86864834 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.3252028779 |
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Oct 15 11:33:37 AM UTC 24 |
Oct 15 11:34:56 AM UTC 24 |
11827499364 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2868543035 |
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|
Oct 15 11:34:41 AM UTC 24 |
Oct 15 11:34:57 AM UTC 24 |
1711936872 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.1790479734 |
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|
Oct 15 11:34:55 AM UTC 24 |
Oct 15 11:34:57 AM UTC 24 |
16414044 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3317097173 |
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|
Oct 15 11:34:56 AM UTC 24 |
Oct 15 11:34:59 AM UTC 24 |
47254616 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.527741251 |
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|
Oct 15 11:34:21 AM UTC 24 |
Oct 15 11:34:59 AM UTC 24 |
1523959176 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.4196961009 |
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Oct 15 11:34:56 AM UTC 24 |
Oct 15 11:35:00 AM UTC 24 |
29229467 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.3194764682 |
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Oct 15 11:33:54 AM UTC 24 |
Oct 15 11:35:01 AM UTC 24 |
2219746407 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.1325495417 |
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Oct 15 11:35:25 AM UTC 24 |
Oct 15 11:35:43 AM UTC 24 |
3767036708 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.1551821889 |
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|
Oct 15 11:34:58 AM UTC 24 |
Oct 15 11:35:02 AM UTC 24 |
157227969 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.4241107791 |
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|
Oct 15 11:34:37 AM UTC 24 |
Oct 15 11:35:02 AM UTC 24 |
241732850 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.2605620657 |
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|
Oct 15 11:32:38 AM UTC 24 |
Oct 15 11:35:02 AM UTC 24 |
24644921802 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.14132875 |
|
|
Oct 15 11:34:53 AM UTC 24 |
Oct 15 11:35:02 AM UTC 24 |
449400451 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.2563736066 |
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Oct 15 11:34:43 AM UTC 24 |
Oct 15 11:35:03 AM UTC 24 |
1169804095 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.1000042898 |
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|
Oct 15 11:34:58 AM UTC 24 |
Oct 15 11:35:05 AM UTC 24 |
195870954 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.138388458 |
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|
Oct 15 11:34:51 AM UTC 24 |
Oct 15 11:35:06 AM UTC 24 |
492111345 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.831324324 |
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Oct 15 11:35:24 AM UTC 24 |
Oct 15 11:35:41 AM UTC 24 |
281182762 ps |