| T385 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.668765142 |
|
|
Feb 09 02:30:23 PM UTC 25 |
Feb 09 02:30:29 PM UTC 25 |
53233612 ps |
| T386 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.3934992935 |
|
|
Feb 09 02:30:23 PM UTC 25 |
Feb 09 02:30:31 PM UTC 25 |
535619354 ps |
| T387 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.1276606714 |
|
|
Feb 09 02:29:13 PM UTC 25 |
Feb 09 02:30:31 PM UTC 25 |
15557591988 ps |
| T388 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.3213501266 |
|
|
Feb 09 02:30:14 PM UTC 25 |
Feb 09 02:30:31 PM UTC 25 |
1869685008 ps |
| T57 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.2392819244 |
|
|
Feb 09 02:30:11 PM UTC 25 |
Feb 09 02:30:32 PM UTC 25 |
1376098907 ps |
| T389 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.2204138100 |
|
|
Feb 09 02:30:29 PM UTC 25 |
Feb 09 02:30:33 PM UTC 25 |
47299923 ps |
| T241 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.3815420372 |
|
|
Feb 09 02:30:23 PM UTC 25 |
Feb 09 02:30:34 PM UTC 25 |
416217115 ps |
| T390 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.1448547325 |
|
|
Feb 09 02:30:25 PM UTC 25 |
Feb 09 02:30:34 PM UTC 25 |
323047218 ps |
| T391 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.2431755461 |
|
|
Feb 09 02:30:32 PM UTC 25 |
Feb 09 02:30:35 PM UTC 25 |
11479130 ps |
| T392 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.635107464 |
|
|
Feb 09 02:30:33 PM UTC 25 |
Feb 09 02:30:36 PM UTC 25 |
41921401 ps |
| T393 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.2715752460 |
|
|
Feb 09 02:29:27 PM UTC 25 |
Feb 09 02:30:38 PM UTC 25 |
1921901012 ps |
| T394 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.1182117573 |
|
|
Feb 09 02:30:33 PM UTC 25 |
Feb 09 02:30:38 PM UTC 25 |
105375161 ps |
| T395 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.3368679794 |
|
|
Feb 09 02:30:23 PM UTC 25 |
Feb 09 02:30:38 PM UTC 25 |
258593846 ps |
| T396 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.1887951530 |
|
|
Feb 09 02:30:36 PM UTC 25 |
Feb 09 02:30:39 PM UTC 25 |
21931882 ps |
| T397 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.1594182556 |
|
|
Feb 09 02:30:29 PM UTC 25 |
Feb 09 02:30:40 PM UTC 25 |
522135418 ps |
| T398 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.3320590145 |
|
|
Feb 09 02:30:35 PM UTC 25 |
Feb 09 02:30:41 PM UTC 25 |
82268135 ps |
| T399 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.1107220440 |
|
|
Feb 09 02:30:03 PM UTC 25 |
Feb 09 02:30:44 PM UTC 25 |
1816799787 ps |
| T400 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.3980146374 |
|
|
Feb 09 02:30:29 PM UTC 25 |
Feb 09 02:30:44 PM UTC 25 |
3259199220 ps |
| T401 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.963317548 |
|
|
Feb 09 02:30:27 PM UTC 25 |
Feb 09 02:30:44 PM UTC 25 |
398736318 ps |
| T402 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.4027074808 |
|
|
Feb 09 02:30:30 PM UTC 25 |
Feb 09 02:30:47 PM UTC 25 |
2103284303 ps |
| T403 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.503713435 |
|
|
Feb 09 02:30:39 PM UTC 25 |
Feb 09 02:30:48 PM UTC 25 |
568336832 ps |
| T404 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.3336381263 |
|
|
Feb 09 02:30:45 PM UTC 25 |
Feb 09 02:30:48 PM UTC 25 |
116243060 ps |
| T405 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.827833790 |
|
|
Feb 09 02:27:51 PM UTC 25 |
Feb 09 02:30:51 PM UTC 25 |
26096938456 ps |
| T406 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.3573229689 |
|
|
Feb 09 02:30:51 PM UTC 25 |
Feb 09 02:30:54 PM UTC 25 |
95093962 ps |
| T407 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.4211385231 |
|
|
Feb 09 02:30:37 PM UTC 25 |
Feb 09 02:30:54 PM UTC 25 |
340613695 ps |
| T408 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.3338643062 |
|
|
Feb 09 02:29:49 PM UTC 25 |
Feb 09 02:30:54 PM UTC 25 |
8310038978 ps |
| T409 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.749626974 |
|
|
Feb 09 02:30:39 PM UTC 25 |
Feb 09 02:30:54 PM UTC 25 |
240659172 ps |
| T410 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.1598912586 |
|
|
Feb 09 02:30:41 PM UTC 25 |
Feb 09 02:30:55 PM UTC 25 |
1629501402 ps |
| T411 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.1828165620 |
|
|
Feb 09 02:30:09 PM UTC 25 |
Feb 09 02:30:56 PM UTC 25 |
5670090499 ps |
| T412 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.172346373 |
|
|
Feb 09 02:30:46 PM UTC 25 |
Feb 09 02:30:57 PM UTC 25 |
416684421 ps |
| T413 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.4021491178 |
|
|
Feb 09 02:30:54 PM UTC 25 |
Feb 09 02:30:58 PM UTC 25 |
95778628 ps |
| T414 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1810202308 |
|
|
Feb 09 02:30:56 PM UTC 25 |
Feb 09 02:30:59 PM UTC 25 |
38239469 ps |
| T415 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.599977100 |
|
|
Feb 09 02:29:45 PM UTC 25 |
Feb 09 02:30:59 PM UTC 25 |
2389192659 ps |
| T416 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.290850071 |
|
|
Feb 09 02:30:40 PM UTC 25 |
Feb 09 02:30:59 PM UTC 25 |
333962026 ps |
| T417 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.796221629 |
|
|
Feb 09 02:30:35 PM UTC 25 |
Feb 09 02:31:01 PM UTC 25 |
619986371 ps |
| T418 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.126984641 |
|
|
Feb 09 02:30:48 PM UTC 25 |
Feb 09 02:31:01 PM UTC 25 |
597164896 ps |
| T419 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.2584821914 |
|
|
Feb 09 02:30:19 PM UTC 25 |
Feb 09 02:31:03 PM UTC 25 |
311208296 ps |
| T420 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.3054084464 |
|
|
Feb 09 02:30:56 PM UTC 25 |
Feb 09 02:31:03 PM UTC 25 |
168761169 ps |
| T421 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.1220037055 |
|
|
Feb 09 02:30:45 PM UTC 25 |
Feb 09 02:31:03 PM UTC 25 |
297997929 ps |
| T80 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.48419768 |
|
|
Feb 09 02:29:56 PM UTC 25 |
Feb 09 02:31:04 PM UTC 25 |
1978597598 ps |
| T422 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.2948729292 |
|
|
Feb 09 02:31:01 PM UTC 25 |
Feb 09 02:31:06 PM UTC 25 |
200326682 ps |
| T423 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.1403236453 |
|
|
Feb 09 02:30:56 PM UTC 25 |
Feb 09 02:31:06 PM UTC 25 |
160517464 ps |
| T424 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.523854434 |
|
|
Feb 09 02:30:27 PM UTC 25 |
Feb 09 02:31:09 PM UTC 25 |
2582010961 ps |
| T425 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.1526082883 |
|
|
Feb 09 02:31:08 PM UTC 25 |
Feb 09 02:31:10 PM UTC 25 |
39373905 ps |
| T426 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_errors.1352520324 |
|
|
Feb 09 02:30:57 PM UTC 25 |
Feb 09 02:31:11 PM UTC 25 |
4354871857 ps |
| T427 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.1015951678 |
|
|
Feb 09 02:31:02 PM UTC 25 |
Feb 09 02:31:12 PM UTC 25 |
342656830 ps |
| T428 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2908813984 |
|
|
Feb 09 02:31:11 PM UTC 25 |
Feb 09 02:31:13 PM UTC 25 |
96966866 ps |
| T429 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.100565435 |
|
|
Feb 09 02:31:10 PM UTC 25 |
Feb 09 02:31:14 PM UTC 25 |
169112366 ps |
| T430 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.3640984241 |
|
|
Feb 09 02:30:58 PM UTC 25 |
Feb 09 02:31:15 PM UTC 25 |
353761997 ps |
| T431 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.3493797991 |
|
|
Feb 09 02:30:59 PM UTC 25 |
Feb 09 02:31:15 PM UTC 25 |
350308929 ps |
| T432 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.4112316265 |
|
|
Feb 09 02:31:03 PM UTC 25 |
Feb 09 02:31:16 PM UTC 25 |
305673099 ps |
| T433 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.437748963 |
|
|
Feb 09 02:31:14 PM UTC 25 |
Feb 09 02:31:18 PM UTC 25 |
74079552 ps |
| T434 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.483767831 |
|
|
Feb 09 02:31:04 PM UTC 25 |
Feb 09 02:31:19 PM UTC 25 |
421045598 ps |
| T435 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.2682488338 |
|
|
Feb 09 02:31:15 PM UTC 25 |
Feb 09 02:31:23 PM UTC 25 |
286268758 ps |
| T436 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.792811698 |
|
|
Feb 09 02:30:23 PM UTC 25 |
Feb 09 02:31:23 PM UTC 25 |
922408759 ps |
| T58 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.1937292576 |
|
|
Feb 09 02:31:03 PM UTC 25 |
Feb 09 02:31:26 PM UTC 25 |
5108526852 ps |
| T437 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.4184383774 |
|
|
Feb 09 02:31:13 PM UTC 25 |
Feb 09 02:31:26 PM UTC 25 |
443813101 ps |
| T438 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.4059873423 |
|
|
Feb 09 02:30:42 PM UTC 25 |
Feb 09 02:31:27 PM UTC 25 |
12758175917 ps |
| T88 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.216060097 |
|
|
Feb 09 02:28:50 PM UTC 25 |
Feb 09 02:31:27 PM UTC 25 |
4180746103 ps |
| T439 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.861786078 |
|
|
Feb 09 02:31:00 PM UTC 25 |
Feb 09 02:31:27 PM UTC 25 |
3732415780 ps |
| T440 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.2878218303 |
|
|
Feb 09 02:31:23 PM UTC 25 |
Feb 09 02:31:28 PM UTC 25 |
669874815 ps |
| T441 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.3212309690 |
|
|
Feb 09 02:31:19 PM UTC 25 |
Feb 09 02:31:29 PM UTC 25 |
478692595 ps |
| T442 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.1917530567 |
|
|
Feb 09 02:31:15 PM UTC 25 |
Feb 09 02:31:30 PM UTC 25 |
945429591 ps |
| T443 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.461450492 |
|
|
Feb 09 02:31:29 PM UTC 25 |
Feb 09 02:31:32 PM UTC 25 |
200806315 ps |
| T444 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.629996575 |
|
|
Feb 09 02:31:29 PM UTC 25 |
Feb 09 02:31:32 PM UTC 25 |
58006497 ps |
| T445 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.897889210 |
|
|
Feb 09 02:31:29 PM UTC 25 |
Feb 09 02:31:34 PM UTC 25 |
52886502 ps |
| T446 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.3690967243 |
|
|
Feb 09 02:30:56 PM UTC 25 |
Feb 09 02:31:35 PM UTC 25 |
846653646 ps |
| T447 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.2858203307 |
|
|
Feb 09 02:31:14 PM UTC 25 |
Feb 09 02:31:35 PM UTC 25 |
432118644 ps |
| T448 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.1630054569 |
|
|
Feb 09 02:31:31 PM UTC 25 |
Feb 09 02:31:36 PM UTC 25 |
284489641 ps |
| T449 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.364057852 |
|
|
Feb 09 02:31:02 PM UTC 25 |
Feb 09 02:31:37 PM UTC 25 |
2289955996 ps |
| T450 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.4164411232 |
|
|
Feb 09 02:31:33 PM UTC 25 |
Feb 09 02:31:38 PM UTC 25 |
1775172518 ps |
| T451 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.2050331158 |
|
|
Feb 09 02:31:26 PM UTC 25 |
Feb 09 02:31:40 PM UTC 25 |
830271458 ps |
| T452 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.675123965 |
|
|
Feb 09 02:31:26 PM UTC 25 |
Feb 09 02:31:41 PM UTC 25 |
290508584 ps |
| T453 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.2609184680 |
|
|
Feb 09 02:31:17 PM UTC 25 |
Feb 09 02:31:41 PM UTC 25 |
337570514 ps |
| T454 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.496753063 |
|
|
Feb 09 02:31:26 PM UTC 25 |
Feb 09 02:31:43 PM UTC 25 |
285337558 ps |
| T455 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.2987930572 |
|
|
Feb 09 02:31:31 PM UTC 25 |
Feb 09 02:31:45 PM UTC 25 |
173608335 ps |
| T456 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.1558212974 |
|
|
Feb 09 02:30:32 PM UTC 25 |
Feb 09 02:31:47 PM UTC 25 |
27745469868 ps |
| T457 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.3328422154 |
|
|
Feb 09 02:31:36 PM UTC 25 |
Feb 09 02:31:47 PM UTC 25 |
1214285506 ps |
| T458 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.333606094 |
|
|
Feb 09 02:30:39 PM UTC 25 |
Feb 09 02:31:47 PM UTC 25 |
1559661824 ps |
| T242 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.1715034235 |
|
|
Feb 09 02:31:32 PM UTC 25 |
Feb 09 02:31:47 PM UTC 25 |
1043904004 ps |
| T459 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.1261205741 |
|
|
Feb 09 02:31:46 PM UTC 25 |
Feb 09 02:31:49 PM UTC 25 |
58034897 ps |
| T460 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3057103919 |
|
|
Feb 09 02:31:48 PM UTC 25 |
Feb 09 02:31:50 PM UTC 25 |
117249842 ps |
| T461 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.1739496199 |
|
|
Feb 09 02:31:31 PM UTC 25 |
Feb 09 02:31:50 PM UTC 25 |
363569297 ps |
| T462 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.982255540 |
|
|
Feb 09 02:31:38 PM UTC 25 |
Feb 09 02:31:52 PM UTC 25 |
724301342 ps |
| T463 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.2765493169 |
|
|
Feb 09 02:31:41 PM UTC 25 |
Feb 09 02:31:52 PM UTC 25 |
552721868 ps |
| T464 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.1245693759 |
|
|
Feb 09 02:31:48 PM UTC 25 |
Feb 09 02:31:52 PM UTC 25 |
240581410 ps |
| T465 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.3659213790 |
|
|
Feb 09 02:31:41 PM UTC 25 |
Feb 09 02:31:53 PM UTC 25 |
249602838 ps |
| T466 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.296808241 |
|
|
Feb 09 02:31:39 PM UTC 25 |
Feb 09 02:31:56 PM UTC 25 |
216971138 ps |
| T467 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.1585471883 |
|
|
Feb 09 02:31:50 PM UTC 25 |
Feb 09 02:31:56 PM UTC 25 |
69847935 ps |
| T468 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.3429974921 |
|
|
Feb 09 02:31:35 PM UTC 25 |
Feb 09 02:31:58 PM UTC 25 |
1140950080 ps |
| T469 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.4217737207 |
|
|
Feb 09 02:31:48 PM UTC 25 |
Feb 09 02:32:02 PM UTC 25 |
63352384 ps |
| T470 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.2614496124 |
|
|
Feb 09 02:31:13 PM UTC 25 |
Feb 09 02:32:02 PM UTC 25 |
574178709 ps |
| T471 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.3080637965 |
|
|
Feb 09 02:31:57 PM UTC 25 |
Feb 09 02:32:04 PM UTC 25 |
332307496 ps |
| T472 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.3011932862 |
|
|
Feb 09 02:31:51 PM UTC 25 |
Feb 09 02:32:05 PM UTC 25 |
235799530 ps |
| T473 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.259950759 |
|
|
Feb 09 02:33:05 PM UTC 25 |
Feb 09 02:33:08 PM UTC 25 |
75164569 ps |
| T474 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.3497245333 |
|
|
Feb 09 02:31:29 PM UTC 25 |
Feb 09 02:32:07 PM UTC 25 |
242319824 ps |
| T475 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.1614604125 |
|
|
Feb 09 02:31:53 PM UTC 25 |
Feb 09 02:32:09 PM UTC 25 |
1910106244 ps |
| T476 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.3402987353 |
|
|
Feb 09 02:32:07 PM UTC 25 |
Feb 09 02:32:10 PM UTC 25 |
19137638 ps |
| T477 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.3432760787 |
|
|
Feb 09 02:30:06 PM UTC 25 |
Feb 09 02:32:10 PM UTC 25 |
14253926304 ps |
| T478 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.543865697 |
|
|
Feb 09 02:31:53 PM UTC 25 |
Feb 09 02:32:12 PM UTC 25 |
2384803212 ps |
| T479 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.3427800127 |
|
|
Feb 09 02:31:59 PM UTC 25 |
Feb 09 02:32:13 PM UTC 25 |
536016536 ps |
| T480 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.1572988504 |
|
|
Feb 09 02:32:09 PM UTC 25 |
Feb 09 02:32:13 PM UTC 25 |
32278862 ps |
| T481 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2406223157 |
|
|
Feb 09 02:32:10 PM UTC 25 |
Feb 09 02:32:13 PM UTC 25 |
52818184 ps |
| T482 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.792649466 |
|
|
Feb 09 02:28:22 PM UTC 25 |
Feb 09 02:32:14 PM UTC 25 |
11541872572 ps |
| T483 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.170885231 |
|
|
Feb 09 02:32:03 PM UTC 25 |
Feb 09 02:32:16 PM UTC 25 |
1763181976 ps |
| T484 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.773455278 |
|
|
Feb 09 02:31:27 PM UTC 25 |
Feb 09 02:32:17 PM UTC 25 |
11047319054 ps |
| T485 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.2077008216 |
|
|
Feb 09 02:31:51 PM UTC 25 |
Feb 09 02:32:18 PM UTC 25 |
914221717 ps |
| T486 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.1616838338 |
|
|
Feb 09 02:32:14 PM UTC 25 |
Feb 09 02:32:19 PM UTC 25 |
133822070 ps |
| T487 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.540236842 |
|
|
Feb 09 02:32:03 PM UTC 25 |
Feb 09 02:32:23 PM UTC 25 |
3621501412 ps |
| T488 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.1754423219 |
|
|
Feb 09 02:32:19 PM UTC 25 |
Feb 09 02:32:24 PM UTC 25 |
297563662 ps |
| T489 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.3712726713 |
|
|
Feb 09 02:32:15 PM UTC 25 |
Feb 09 02:32:25 PM UTC 25 |
883415889 ps |
| T490 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3674419885 |
|
|
Feb 09 02:32:14 PM UTC 25 |
Feb 09 02:32:26 PM UTC 25 |
269549116 ps |
| T491 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.2412637825 |
|
|
Feb 09 02:31:37 PM UTC 25 |
Feb 09 02:32:26 PM UTC 25 |
3090442751 ps |
| T492 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.374761561 |
|
|
Feb 09 02:32:13 PM UTC 25 |
Feb 09 02:32:28 PM UTC 25 |
267880301 ps |
| T493 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.3217515204 |
|
|
Feb 09 02:32:14 PM UTC 25 |
Feb 09 02:32:30 PM UTC 25 |
748919913 ps |
| T494 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.404360565 |
|
|
Feb 09 02:32:18 PM UTC 25 |
Feb 09 02:32:33 PM UTC 25 |
1241394621 ps |
| T495 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.4286688270 |
|
|
Feb 09 02:32:31 PM UTC 25 |
Feb 09 02:32:33 PM UTC 25 |
74496583 ps |
| T496 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.3829599938 |
|
|
Feb 09 02:31:00 PM UTC 25 |
Feb 09 02:32:35 PM UTC 25 |
9549721840 ps |
| T497 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.1007931731 |
|
|
Feb 09 02:31:35 PM UTC 25 |
Feb 09 02:32:35 PM UTC 25 |
1080047196 ps |
| T498 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2653874172 |
|
|
Feb 09 02:32:34 PM UTC 25 |
Feb 09 02:32:36 PM UTC 25 |
18582321 ps |
| T499 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.1451296602 |
|
|
Feb 09 02:32:34 PM UTC 25 |
Feb 09 02:32:38 PM UTC 25 |
133899557 ps |
| T500 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.556820646 |
|
|
Feb 09 02:31:20 PM UTC 25 |
Feb 09 02:32:38 PM UTC 25 |
2150071783 ps |
| T501 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.3334041063 |
|
|
Feb 09 02:31:48 PM UTC 25 |
Feb 09 02:32:39 PM UTC 25 |
717341739 ps |
| T502 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.2601741829 |
|
|
Feb 09 02:32:37 PM UTC 25 |
Feb 09 02:32:44 PM UTC 25 |
74088812 ps |
| T503 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.312413706 |
|
|
Feb 09 02:32:26 PM UTC 25 |
Feb 09 02:32:44 PM UTC 25 |
1422466854 ps |
| T504 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.4123839686 |
|
|
Feb 09 02:31:53 PM UTC 25 |
Feb 09 02:32:45 PM UTC 25 |
1390515399 ps |
| T505 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.341032000 |
|
|
Feb 09 02:32:26 PM UTC 25 |
Feb 09 02:32:45 PM UTC 25 |
363116322 ps |
| T506 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.3517589916 |
|
|
Feb 09 02:32:25 PM UTC 25 |
Feb 09 02:32:46 PM UTC 25 |
1194787379 ps |
| T507 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.2434485358 |
|
|
Feb 09 02:32:24 PM UTC 25 |
Feb 09 02:32:46 PM UTC 25 |
3648991204 ps |
| T508 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.2370895289 |
|
|
Feb 09 02:31:53 PM UTC 25 |
Feb 09 02:32:47 PM UTC 25 |
5382122454 ps |
| T509 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.582068806 |
|
|
Feb 09 02:32:36 PM UTC 25 |
Feb 09 02:32:50 PM UTC 25 |
112009178 ps |
| T510 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.1447678489 |
|
|
Feb 09 02:32:40 PM UTC 25 |
Feb 09 02:32:51 PM UTC 25 |
422981321 ps |
| T511 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.1472807554 |
|
|
Feb 09 02:32:40 PM UTC 25 |
Feb 09 02:32:51 PM UTC 25 |
4142218389 ps |
| T512 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.4004272458 |
|
|
Feb 09 02:32:05 PM UTC 25 |
Feb 09 02:32:53 PM UTC 25 |
9132296235 ps |
| T513 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.302893529 |
|
|
Feb 09 02:32:46 PM UTC 25 |
Feb 09 02:32:53 PM UTC 25 |
247983598 ps |
| T514 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.4205961267 |
|
|
Feb 09 02:31:57 PM UTC 25 |
Feb 09 02:32:54 PM UTC 25 |
2698301275 ps |
| T515 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.2373091711 |
|
|
Feb 09 02:32:20 PM UTC 25 |
Feb 09 02:32:55 PM UTC 25 |
5452358778 ps |
| T516 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.3314048827 |
|
|
Feb 09 02:32:54 PM UTC 25 |
Feb 09 02:32:57 PM UTC 25 |
23010653 ps |
| T517 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.702665571 |
|
|
Feb 09 02:32:47 PM UTC 25 |
Feb 09 02:32:57 PM UTC 25 |
450368099 ps |
| T518 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2227417873 |
|
|
Feb 09 02:32:56 PM UTC 25 |
Feb 09 02:32:58 PM UTC 25 |
46616642 ps |
| T519 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.587674576 |
|
|
Feb 09 02:30:14 PM UTC 25 |
Feb 09 02:32:58 PM UTC 25 |
24599516098 ps |
| T520 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.3240522591 |
|
|
Feb 09 02:32:49 PM UTC 25 |
Feb 09 02:32:59 PM UTC 25 |
661692594 ps |
| T521 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.3815895457 |
|
|
Feb 09 02:32:40 PM UTC 25 |
Feb 09 02:32:59 PM UTC 25 |
315708706 ps |
| T522 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.2390668089 |
|
|
Feb 09 02:32:54 PM UTC 25 |
Feb 09 02:33:00 PM UTC 25 |
52931833 ps |
| T523 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.2489401496 |
|
|
Feb 09 02:32:47 PM UTC 25 |
Feb 09 02:33:02 PM UTC 25 |
3465544255 ps |
| T524 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.997755053 |
|
|
Feb 09 02:32:12 PM UTC 25 |
Feb 09 02:33:02 PM UTC 25 |
1044525884 ps |
| T525 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.1036266407 |
|
|
Feb 09 02:31:05 PM UTC 25 |
Feb 09 02:33:04 PM UTC 25 |
68650093331 ps |
| T526 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.466602430 |
|
|
Feb 09 02:32:59 PM UTC 25 |
Feb 09 02:33:04 PM UTC 25 |
74229779 ps |
| T527 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.416478638 |
|
|
Feb 09 02:33:00 PM UTC 25 |
Feb 09 02:33:06 PM UTC 25 |
622039845 ps |
| T528 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.2667405705 |
|
|
Feb 09 02:32:45 PM UTC 25 |
Feb 09 02:33:08 PM UTC 25 |
599333997 ps |
| T529 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.802798926 |
|
|
Feb 09 02:32:51 PM UTC 25 |
Feb 09 02:33:10 PM UTC 25 |
1817154150 ps |
| T56 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1823730395 |
|
|
Feb 09 02:33:08 PM UTC 25 |
Feb 09 02:33:11 PM UTC 25 |
51084446 ps |
| T530 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1033207400 |
|
|
Feb 09 02:32:59 PM UTC 25 |
Feb 09 02:33:11 PM UTC 25 |
2881357381 ps |
| T531 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.2056131708 |
|
|
Feb 09 02:33:07 PM UTC 25 |
Feb 09 02:33:12 PM UTC 25 |
148583566 ps |
| T532 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.523540336 |
|
|
Feb 09 02:33:00 PM UTC 25 |
Feb 09 02:33:14 PM UTC 25 |
1197040285 ps |
| T533 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.831814009 |
|
|
Feb 09 02:33:00 PM UTC 25 |
Feb 09 02:33:15 PM UTC 25 |
865290060 ps |
| T534 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.1406799999 |
|
|
Feb 09 02:33:12 PM UTC 25 |
Feb 09 02:33:16 PM UTC 25 |
131674182 ps |
| T535 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.605638645 |
|
|
Feb 09 02:32:59 PM UTC 25 |
Feb 09 02:33:17 PM UTC 25 |
1261477134 ps |
| T536 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.2091264540 |
|
|
Feb 09 02:32:36 PM UTC 25 |
Feb 09 02:33:18 PM UTC 25 |
222194654 ps |
| T537 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.3123917861 |
|
|
Feb 09 02:32:17 PM UTC 25 |
Feb 09 02:33:18 PM UTC 25 |
3240554534 ps |
| T538 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.3203200625 |
|
|
Feb 09 02:32:58 PM UTC 25 |
Feb 09 02:33:22 PM UTC 25 |
251252930 ps |
| T539 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.732199283 |
|
|
Feb 09 02:33:03 PM UTC 25 |
Feb 09 02:33:23 PM UTC 25 |
383053883 ps |
| T540 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.4160985814 |
|
|
Feb 09 02:33:22 PM UTC 25 |
Feb 09 02:33:25 PM UTC 25 |
23197604 ps |
| T541 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3729431162 |
|
|
Feb 09 02:33:24 PM UTC 25 |
Feb 09 02:33:27 PM UTC 25 |
27909544 ps |
| T542 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.1492427849 |
|
|
Feb 09 02:33:12 PM UTC 25 |
Feb 09 02:33:27 PM UTC 25 |
452017998 ps |
| T543 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.3787733460 |
|
|
Feb 09 02:33:22 PM UTC 25 |
Feb 09 02:33:28 PM UTC 25 |
43055721 ps |
| T544 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.413696425 |
|
|
Feb 09 02:33:15 PM UTC 25 |
Feb 09 02:33:29 PM UTC 25 |
344650082 ps |
| T545 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.4053073110 |
|
|
Feb 09 02:33:13 PM UTC 25 |
Feb 09 02:33:30 PM UTC 25 |
1100047193 ps |
| T546 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.1213911852 |
|
|
Feb 09 02:33:17 PM UTC 25 |
Feb 09 02:33:30 PM UTC 25 |
1526314828 ps |
| T547 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.396912477 |
|
|
Feb 09 02:33:18 PM UTC 25 |
Feb 09 02:33:31 PM UTC 25 |
673042372 ps |
| T548 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.4062138653 |
|
|
Feb 09 02:33:29 PM UTC 25 |
Feb 09 02:33:33 PM UTC 25 |
86377886 ps |
| T549 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.3008015748 |
|
|
Feb 09 02:33:28 PM UTC 25 |
Feb 09 02:33:36 PM UTC 25 |
731636416 ps |
| T550 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.1161807318 |
|
|
Feb 09 02:33:13 PM UTC 25 |
Feb 09 02:33:37 PM UTC 25 |
335638865 ps |
| T551 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.2725365252 |
|
|
Feb 09 02:32:46 PM UTC 25 |
Feb 09 02:33:38 PM UTC 25 |
2644593821 ps |
| T552 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.1016081139 |
|
|
Feb 09 02:32:56 PM UTC 25 |
Feb 09 02:33:39 PM UTC 25 |
1249642594 ps |
| T553 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.2317822516 |
|
|
Feb 09 02:33:30 PM UTC 25 |
Feb 09 02:33:40 PM UTC 25 |
329912339 ps |
| T554 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.81288782 |
|
|
Feb 09 02:33:38 PM UTC 25 |
Feb 09 02:33:41 PM UTC 25 |
73581900 ps |
| T555 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.1723426726 |
|
|
Feb 09 02:33:31 PM UTC 25 |
Feb 09 02:33:41 PM UTC 25 |
584589667 ps |
| T556 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1106802157 |
|
|
Feb 09 02:33:40 PM UTC 25 |
Feb 09 02:33:43 PM UTC 25 |
18356012 ps |
| T557 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.202355019 |
|
|
Feb 09 02:33:16 PM UTC 25 |
Feb 09 02:33:43 PM UTC 25 |
467356552 ps |
| T558 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.937999684 |
|
|
Feb 09 02:33:29 PM UTC 25 |
Feb 09 02:33:43 PM UTC 25 |
196960323 ps |
| T559 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.1507716036 |
|
|
Feb 09 02:31:17 PM UTC 25 |
Feb 09 02:33:43 PM UTC 25 |
8253801240 ps |
| T560 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.101566621 |
|
|
Feb 09 02:33:39 PM UTC 25 |
Feb 09 02:33:45 PM UTC 25 |
272697330 ps |
| T561 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.1883715639 |
|
|
Feb 09 02:33:31 PM UTC 25 |
Feb 09 02:33:45 PM UTC 25 |
928261259 ps |
| T562 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.3475335247 |
|
|
Feb 09 02:33:31 PM UTC 25 |
Feb 09 02:33:47 PM UTC 25 |
306337234 ps |
| T563 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.82805291 |
|
|
Feb 09 02:33:08 PM UTC 25 |
Feb 09 02:33:48 PM UTC 25 |
1958224745 ps |
| T564 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.1831178293 |
|
|
Feb 09 02:33:41 PM UTC 25 |
Feb 09 02:33:48 PM UTC 25 |
96150663 ps |
| T565 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.2623718728 |
|
|
Feb 09 02:33:41 PM UTC 25 |
Feb 09 02:33:48 PM UTC 25 |
93028676 ps |
| T566 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.1769447147 |
|
|
Feb 09 02:33:49 PM UTC 25 |
Feb 09 02:33:51 PM UTC 25 |
18595817 ps |
| T567 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.870631888 |
|
|
Feb 09 02:34:32 PM UTC 25 |
Feb 09 02:34:35 PM UTC 25 |
16551872 ps |
| T568 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1181157618 |
|
|
Feb 09 02:33:49 PM UTC 25 |
Feb 09 02:33:52 PM UTC 25 |
23540674 ps |
| T569 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.2818207360 |
|
|
Feb 09 02:33:49 PM UTC 25 |
Feb 09 02:33:53 PM UTC 25 |
88997926 ps |
| T570 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.195279420 |
|
|
Feb 09 02:33:34 PM UTC 25 |
Feb 09 02:33:54 PM UTC 25 |
3632161731 ps |
| T571 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.1831405682 |
|
|
Feb 09 02:33:44 PM UTC 25 |
Feb 09 02:33:56 PM UTC 25 |
277489219 ps |
| T572 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.3451259457 |
|
|
Feb 09 02:33:44 PM UTC 25 |
Feb 09 02:33:56 PM UTC 25 |
751521496 ps |
| T573 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.1547335090 |
|
|
Feb 09 02:33:44 PM UTC 25 |
Feb 09 02:33:57 PM UTC 25 |
1089074712 ps |
| T574 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.2250837328 |
|
|
Feb 09 02:33:52 PM UTC 25 |
Feb 09 02:33:57 PM UTC 25 |
40582009 ps |
| T575 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.2369028618 |
|
|
Feb 09 02:33:57 PM UTC 25 |
Feb 09 02:34:00 PM UTC 25 |
221021573 ps |
| T576 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.1523688192 |
|
|
Feb 09 02:32:45 PM UTC 25 |
Feb 09 02:34:01 PM UTC 25 |
3741578587 ps |
| T577 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.2126874238 |
|
|
Feb 09 02:33:44 PM UTC 25 |
Feb 09 02:34:01 PM UTC 25 |
324451817 ps |
| T578 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.2823612821 |
|
|
Feb 09 02:33:43 PM UTC 25 |
Feb 09 02:34:02 PM UTC 25 |
424955702 ps |
| T579 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.503394393 |
|
|
Feb 09 02:33:54 PM UTC 25 |
Feb 09 02:34:05 PM UTC 25 |
1005582773 ps |
| T580 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.33146372 |
|
|
Feb 09 02:34:03 PM UTC 25 |
Feb 09 02:34:05 PM UTC 25 |
47010332 ps |
| T581 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1967824879 |
|
|
Feb 09 02:34:03 PM UTC 25 |
Feb 09 02:34:05 PM UTC 25 |
48896728 ps |
| T582 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.1443867734 |
|
|
Feb 09 02:33:52 PM UTC 25 |
Feb 09 02:34:06 PM UTC 25 |
142502622 ps |
| T583 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.2625499638 |
|
|
Feb 09 02:33:45 PM UTC 25 |
Feb 09 02:34:06 PM UTC 25 |
5950278073 ps |
| T584 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.2639668003 |
|
|
Feb 09 02:34:03 PM UTC 25 |
Feb 09 02:34:08 PM UTC 25 |
277795671 ps |
| T585 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.2334167627 |
|
|
Feb 09 02:33:58 PM UTC 25 |
Feb 09 02:34:09 PM UTC 25 |
1398332874 ps |
| T586 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.187988730 |
|
|
Feb 09 02:33:26 PM UTC 25 |
Feb 09 02:34:11 PM UTC 25 |
335314641 ps |
| T587 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.52401501 |
|
|
Feb 09 02:33:55 PM UTC 25 |
Feb 09 02:34:11 PM UTC 25 |
1389867023 ps |
| T588 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.2411440427 |
|
|
Feb 09 02:34:06 PM UTC 25 |
Feb 09 02:34:14 PM UTC 25 |
408927185 ps |
| T589 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.3291789571 |
|
|
Feb 09 02:33:41 PM UTC 25 |
Feb 09 02:34:15 PM UTC 25 |
258384397 ps |
| T590 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.3663749887 |
|
|
Feb 09 02:34:07 PM UTC 25 |
Feb 09 02:34:17 PM UTC 25 |
410668480 ps |
| T591 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.1351166342 |
|
|
Feb 09 02:33:58 PM UTC 25 |
Feb 09 02:34:18 PM UTC 25 |
9359664824 ps |
| T592 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.400653889 |
|
|
Feb 09 02:33:57 PM UTC 25 |
Feb 09 02:34:18 PM UTC 25 |
702449596 ps |
| T593 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.466029129 |
|
|
Feb 09 02:34:16 PM UTC 25 |
Feb 09 02:34:19 PM UTC 25 |
12869443 ps |
| T594 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.1366822025 |
|
|
Feb 09 02:34:09 PM UTC 25 |
Feb 09 02:34:19 PM UTC 25 |
316630552 ps |
| T595 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.2341035247 |
|
|
Feb 09 02:34:06 PM UTC 25 |
Feb 09 02:34:20 PM UTC 25 |
90090126 ps |
| T596 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2850329974 |
|
|
Feb 09 02:34:19 PM UTC 25 |
Feb 09 02:34:22 PM UTC 25 |
18945216 ps |
| T597 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.1225529393 |
|
|
Feb 09 02:34:18 PM UTC 25 |
Feb 09 02:34:22 PM UTC 25 |
73129744 ps |
| T598 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.1841226353 |
|
|
Feb 09 02:34:19 PM UTC 25 |
Feb 09 02:34:25 PM UTC 25 |
202569863 ps |
| T599 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.268873239 |
|
|
Feb 09 02:34:23 PM UTC 25 |
Feb 09 02:34:26 PM UTC 25 |
33829466 ps |
| T600 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.310988096 |
|
|
Feb 09 02:34:21 PM UTC 25 |
Feb 09 02:34:27 PM UTC 25 |
84696370 ps |
| T601 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.4073182624 |
|
|
Feb 09 02:34:07 PM UTC 25 |
Feb 09 02:34:27 PM UTC 25 |
394349475 ps |
| T602 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.3277634455 |
|
|
Feb 09 02:34:07 PM UTC 25 |
Feb 09 02:34:28 PM UTC 25 |
495139321 ps |
| T603 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.1934027049 |
|
|
Feb 09 02:34:12 PM UTC 25 |
Feb 09 02:34:29 PM UTC 25 |
371642050 ps |
| T172 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.3928749195 |
|
|
Feb 09 02:33:03 PM UTC 25 |
Feb 09 02:34:31 PM UTC 25 |
4243153375 ps |
| T604 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.714321780 |
|
|
Feb 09 02:34:08 PM UTC 25 |
Feb 09 02:34:33 PM UTC 25 |
369679352 ps |
| T605 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.3692011873 |
|
|
Feb 09 02:34:30 PM UTC 25 |
Feb 09 02:34:33 PM UTC 25 |
19165420 ps |
| T606 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.546584271 |
|
|
Feb 09 02:34:32 PM UTC 25 |
Feb 09 02:34:35 PM UTC 25 |
36294868 ps |
| T99 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.745070296 |
|
|
Feb 09 02:26:54 PM UTC 25 |
Feb 09 02:34:37 PM UTC 25 |
22258398853 ps |
| T607 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.3532781131 |
|
|
Feb 09 02:34:34 PM UTC 25 |
Feb 09 02:34:39 PM UTC 25 |
718684757 ps |
| T608 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.2179862997 |
|
|
Feb 09 02:34:23 PM UTC 25 |
Feb 09 02:34:40 PM UTC 25 |
339224433 ps |
| T609 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.3613123416 |
|
|
Feb 09 02:34:36 PM UTC 25 |
Feb 09 02:34:41 PM UTC 25 |
268630540 ps |
| T610 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.2859786327 |
|
|
Feb 09 02:34:06 PM UTC 25 |
Feb 09 02:34:42 PM UTC 25 |
231707386 ps |
| T611 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.2407461295 |
|
|
Feb 09 02:34:27 PM UTC 25 |
Feb 09 02:34:43 PM UTC 25 |
660976021 ps |
| T612 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.3086829128 |
|
|
Feb 09 02:34:28 PM UTC 25 |
Feb 09 02:34:45 PM UTC 25 |
2724233452 ps |
| T613 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.153643170 |
|
|
Feb 09 02:34:21 PM UTC 25 |
Feb 09 02:34:46 PM UTC 25 |
430940195 ps |
| T614 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.4127805884 |
|
|
Feb 09 02:34:26 PM UTC 25 |
Feb 09 02:34:48 PM UTC 25 |
1388498696 ps |
| T615 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.716226362 |
|
|
Feb 09 02:34:41 PM UTC 25 |
Feb 09 02:34:48 PM UTC 25 |
233767698 ps |
| T616 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.1212809990 |
|
|
Feb 09 02:34:47 PM UTC 25 |
Feb 09 02:34:50 PM UTC 25 |
62251168 ps |
| T617 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.525471735 |
|
|
Feb 09 02:33:52 PM UTC 25 |
Feb 09 02:34:51 PM UTC 25 |
346446020 ps |
| T618 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2124613399 |
|
|
Feb 09 02:34:49 PM UTC 25 |
Feb 09 02:34:51 PM UTC 25 |
25086357 ps |
| T619 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.2573261017 |
|
|
Feb 09 02:34:42 PM UTC 25 |
Feb 09 02:34:52 PM UTC 25 |
1402485697 ps |
| T620 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.834811461 |
|
|
Feb 09 02:34:41 PM UTC 25 |
Feb 09 02:34:53 PM UTC 25 |
250315073 ps |
| T621 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.4153057758 |
|
|
Feb 09 02:34:38 PM UTC 25 |
Feb 09 02:34:53 PM UTC 25 |
1092762533 ps |
| T81 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.3570061744 |
|
|
Feb 09 02:34:48 PM UTC 25 |
Feb 09 02:34:54 PM UTC 25 |
279185809 ps |
| T622 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.2375466538 |
|
|
Feb 09 02:34:43 PM UTC 25 |
Feb 09 02:34:56 PM UTC 25 |
587481840 ps |
| T623 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.3980221652 |
|
|
Feb 09 02:34:52 PM UTC 25 |
Feb 09 02:34:56 PM UTC 25 |
233987822 ps |
| T624 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_errors.3761675955 |
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Feb 09 02:34:37 PM UTC 25 |
Feb 09 02:34:57 PM UTC 25 |
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