| T600 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.4114459659 |
|
|
Oct 15 11:33:43 AM UTC 24 |
Oct 15 11:35:06 AM UTC 24 |
5472725867 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.330127404 |
|
|
Oct 15 11:34:51 AM UTC 24 |
Oct 15 11:35:06 AM UTC 24 |
1469337678 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.300516119 |
|
|
Oct 15 11:34:53 AM UTC 24 |
Oct 15 11:35:06 AM UTC 24 |
1529492331 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.4036130711 |
|
|
Oct 15 11:35:00 AM UTC 24 |
Oct 15 11:35:06 AM UTC 24 |
1897192863 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1562544709 |
|
|
Oct 15 11:35:04 AM UTC 24 |
Oct 15 11:35:07 AM UTC 24 |
39903525 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.983024098 |
|
|
Oct 15 11:35:04 AM UTC 24 |
Oct 15 11:35:07 AM UTC 24 |
24810490 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_errors.3878423785 |
|
|
Oct 15 11:34:50 AM UTC 24 |
Oct 15 11:35:09 AM UTC 24 |
2031777460 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.3448373329 |
|
|
Oct 15 11:35:00 AM UTC 24 |
Oct 15 11:35:09 AM UTC 24 |
2243889384 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.1906666172 |
|
|
Oct 15 11:35:07 AM UTC 24 |
Oct 15 11:35:10 AM UTC 24 |
32564954 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.3124109885 |
|
|
Oct 15 11:32:47 AM UTC 24 |
Oct 15 11:35:11 AM UTC 24 |
12900970498 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.3004243116 |
|
|
Oct 15 11:35:04 AM UTC 24 |
Oct 15 11:35:12 AM UTC 24 |
776883552 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.2903186458 |
|
|
Oct 15 11:35:05 AM UTC 24 |
Oct 15 11:35:42 AM UTC 24 |
1159771897 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.2605361943 |
|
|
Oct 15 11:34:58 AM UTC 24 |
Oct 15 11:35:12 AM UTC 24 |
5698502916 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.523036855 |
|
|
Oct 15 11:34:59 AM UTC 24 |
Oct 15 11:35:13 AM UTC 24 |
808585100 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.3038284881 |
|
|
Oct 15 11:34:53 AM UTC 24 |
Oct 15 11:35:13 AM UTC 24 |
1429443977 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.3224534952 |
|
|
Oct 15 11:35:02 AM UTC 24 |
Oct 15 11:35:13 AM UTC 24 |
442832709 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.733222457 |
|
|
Oct 15 11:35:12 AM UTC 24 |
Oct 15 11:35:14 AM UTC 24 |
100858187 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.163874521 |
|
|
Oct 15 11:35:13 AM UTC 24 |
Oct 15 11:35:16 AM UTC 24 |
20743263 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.443828671 |
|
|
Oct 15 11:35:13 AM UTC 24 |
Oct 15 11:35:16 AM UTC 24 |
57057129 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.619267361 |
|
|
Oct 15 11:35:07 AM UTC 24 |
Oct 15 11:35:16 AM UTC 24 |
104509549 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.650612256 |
|
|
Oct 15 11:35:00 AM UTC 24 |
Oct 15 11:35:16 AM UTC 24 |
1054657336 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.3049267735 |
|
|
Oct 15 11:34:58 AM UTC 24 |
Oct 15 11:35:17 AM UTC 24 |
238388601 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.690132721 |
|
|
Oct 15 11:34:07 AM UTC 24 |
Oct 15 11:35:17 AM UTC 24 |
3147961138 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.96792091 |
|
|
Oct 15 11:34:48 AM UTC 24 |
Oct 15 11:35:18 AM UTC 24 |
265421299 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.3960628646 |
|
|
Oct 15 11:35:07 AM UTC 24 |
Oct 15 11:35:18 AM UTC 24 |
176827669 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.3066149368 |
|
|
Oct 15 11:35:15 AM UTC 24 |
Oct 15 11:35:18 AM UTC 24 |
51343207 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.3385686610 |
|
|
Oct 15 11:35:07 AM UTC 24 |
Oct 15 11:35:19 AM UTC 24 |
402501178 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.3029681788 |
|
|
Oct 15 11:35:14 AM UTC 24 |
Oct 15 11:35:20 AM UTC 24 |
626168925 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.2191967701 |
|
|
Oct 15 11:35:07 AM UTC 24 |
Oct 15 11:35:20 AM UTC 24 |
451137232 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.3534359294 |
|
|
Oct 15 11:38:01 AM UTC 24 |
Oct 15 11:38:53 AM UTC 24 |
1489676236 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.3175012169 |
|
|
Oct 15 11:35:08 AM UTC 24 |
Oct 15 11:35:20 AM UTC 24 |
497490909 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.1254417179 |
|
|
Oct 15 11:35:19 AM UTC 24 |
Oct 15 11:35:21 AM UTC 24 |
60355951 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.2730776840 |
|
|
Oct 15 11:35:40 AM UTC 24 |
Oct 15 11:35:43 AM UTC 24 |
22019984 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3142970925 |
|
|
Oct 15 11:35:20 AM UTC 24 |
Oct 15 11:35:22 AM UTC 24 |
41668470 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.3088671172 |
|
|
Oct 15 11:35:07 AM UTC 24 |
Oct 15 11:35:23 AM UTC 24 |
299366468 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.3743898553 |
|
|
Oct 15 11:35:10 AM UTC 24 |
Oct 15 11:35:24 AM UTC 24 |
733352066 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.2742593827 |
|
|
Oct 15 11:35:20 AM UTC 24 |
Oct 15 11:35:25 AM UTC 24 |
49478621 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.1413741619 |
|
|
Oct 15 11:35:21 AM UTC 24 |
Oct 15 11:35:26 AM UTC 24 |
105195787 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.4016898774 |
|
|
Oct 15 11:35:21 AM UTC 24 |
Oct 15 11:35:26 AM UTC 24 |
131189750 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.560430 |
|
|
Oct 15 11:35:17 AM UTC 24 |
Oct 15 11:35:28 AM UTC 24 |
2141209821 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.3362097717 |
|
|
Oct 15 11:35:23 AM UTC 24 |
Oct 15 11:35:30 AM UTC 24 |
244929194 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.1349181681 |
|
|
Oct 15 11:35:18 AM UTC 24 |
Oct 15 11:35:30 AM UTC 24 |
872538876 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.3663551951 |
|
|
Oct 15 11:35:28 AM UTC 24 |
Oct 15 11:35:31 AM UTC 24 |
68878220 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_errors.4284811961 |
|
|
Oct 15 11:35:15 AM UTC 24 |
Oct 15 11:35:32 AM UTC 24 |
1680034120 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2621934554 |
|
|
Oct 15 11:35:31 AM UTC 24 |
Oct 15 11:35:33 AM UTC 24 |
36063347 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.3137302831 |
|
|
Oct 15 11:35:18 AM UTC 24 |
Oct 15 11:35:33 AM UTC 24 |
1338116455 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.1494998005 |
|
|
Oct 15 11:35:17 AM UTC 24 |
Oct 15 11:35:33 AM UTC 24 |
387821400 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.1564089633 |
|
|
Oct 15 11:35:31 AM UTC 24 |
Oct 15 11:35:35 AM UTC 24 |
67957810 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.3918268362 |
|
|
Oct 15 11:32:29 AM UTC 24 |
Oct 15 11:35:35 AM UTC 24 |
17632835201 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.3912060486 |
|
|
Oct 15 11:35:23 AM UTC 24 |
Oct 15 11:35:37 AM UTC 24 |
264302587 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.1107938087 |
|
|
Oct 15 11:35:34 AM UTC 24 |
Oct 15 11:35:37 AM UTC 24 |
203589567 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.595442133 |
|
|
Oct 15 11:35:14 AM UTC 24 |
Oct 15 11:35:38 AM UTC 24 |
1258915013 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.3977113294 |
|
|
Oct 15 11:34:36 AM UTC 24 |
Oct 15 11:35:39 AM UTC 24 |
1388663234 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.330992044 |
|
|
Oct 15 11:35:23 AM UTC 24 |
Oct 15 11:35:39 AM UTC 24 |
364666119 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.3225547589 |
|
|
Oct 15 11:35:17 AM UTC 24 |
Oct 15 11:35:40 AM UTC 24 |
546904616 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.3916186083 |
|
|
Oct 15 11:38:24 AM UTC 24 |
Oct 15 11:38:57 AM UTC 24 |
623574641 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1062457689 |
|
|
Oct 15 11:34:27 AM UTC 24 |
Oct 15 11:35:43 AM UTC 24 |
9892725326 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2472262218 |
|
|
Oct 15 11:35:42 AM UTC 24 |
Oct 15 11:35:44 AM UTC 24 |
13912585 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.405834252 |
|
|
Oct 15 11:35:36 AM UTC 24 |
Oct 15 11:35:45 AM UTC 24 |
1933467951 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.3148817692 |
|
|
Oct 15 11:35:34 AM UTC 24 |
Oct 15 11:35:47 AM UTC 24 |
2013579973 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.3633138469 |
|
|
Oct 15 11:35:33 AM UTC 24 |
Oct 15 11:35:47 AM UTC 24 |
301976015 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.1533108890 |
|
|
Oct 15 11:35:44 AM UTC 24 |
Oct 15 11:35:48 AM UTC 24 |
29209918 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.3186165565 |
|
|
Oct 15 11:35:38 AM UTC 24 |
Oct 15 11:35:48 AM UTC 24 |
257616579 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.952225043 |
|
|
Oct 15 11:35:25 AM UTC 24 |
Oct 15 11:35:49 AM UTC 24 |
1982197839 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.913806686 |
|
|
Oct 15 11:35:42 AM UTC 24 |
Oct 15 11:35:49 AM UTC 24 |
89764780 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.3005068539 |
|
|
Oct 15 11:35:21 AM UTC 24 |
Oct 15 11:35:50 AM UTC 24 |
346688566 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.1079124998 |
|
|
Oct 15 11:35:32 AM UTC 24 |
Oct 15 11:35:52 AM UTC 24 |
962701365 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.2649522609 |
|
|
Oct 15 11:35:36 AM UTC 24 |
Oct 15 11:35:52 AM UTC 24 |
1270181921 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.3758524787 |
|
|
Oct 15 11:35:50 AM UTC 24 |
Oct 15 11:35:53 AM UTC 24 |
20822850 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.149217176 |
|
|
Oct 15 11:35:51 AM UTC 24 |
Oct 15 11:35:55 AM UTC 24 |
26786704 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.1859997528 |
|
|
Oct 15 11:35:44 AM UTC 24 |
Oct 15 11:35:55 AM UTC 24 |
95399867 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2209462035 |
|
|
Oct 15 11:35:53 AM UTC 24 |
Oct 15 11:35:55 AM UTC 24 |
58373181 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.3402657554 |
|
|
Oct 15 11:35:38 AM UTC 24 |
Oct 15 11:35:55 AM UTC 24 |
669444498 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.1555418550 |
|
|
Oct 15 11:35:44 AM UTC 24 |
Oct 15 11:35:56 AM UTC 24 |
1066733790 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.1064265494 |
|
|
Oct 15 11:35:54 AM UTC 24 |
Oct 15 11:35:59 AM UTC 24 |
350758631 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.1318928416 |
|
|
Oct 15 11:37:30 AM UTC 24 |
Oct 15 11:37:45 AM UTC 24 |
3751491053 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.3684799747 |
|
|
Oct 15 11:35:48 AM UTC 24 |
Oct 15 11:35:59 AM UTC 24 |
206907634 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.4043952110 |
|
|
Oct 15 11:35:56 AM UTC 24 |
Oct 15 11:36:00 AM UTC 24 |
188188890 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.1006110576 |
|
|
Oct 15 11:35:45 AM UTC 24 |
Oct 15 11:36:01 AM UTC 24 |
1945927547 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.3958821458 |
|
|
Oct 15 11:35:49 AM UTC 24 |
Oct 15 11:36:02 AM UTC 24 |
662899889 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1089400998 |
|
|
Oct 15 11:35:40 AM UTC 24 |
Oct 15 11:36:02 AM UTC 24 |
1194561085 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.3071807346 |
|
|
Oct 15 11:35:43 AM UTC 24 |
Oct 15 11:36:02 AM UTC 24 |
249878844 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_errors.3808039612 |
|
|
Oct 15 11:35:34 AM UTC 24 |
Oct 15 11:36:03 AM UTC 24 |
2815496638 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.2633311530 |
|
|
Oct 15 11:36:02 AM UTC 24 |
Oct 15 11:36:04 AM UTC 24 |
39363154 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.154731035 |
|
|
Oct 15 11:35:48 AM UTC 24 |
Oct 15 11:36:04 AM UTC 24 |
1298330791 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.1656111612 |
|
|
Oct 15 11:35:54 AM UTC 24 |
Oct 15 11:36:05 AM UTC 24 |
215649253 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.451671904 |
|
|
Oct 15 11:36:03 AM UTC 24 |
Oct 15 11:36:06 AM UTC 24 |
16401159 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.3608336525 |
|
|
Oct 15 11:36:03 AM UTC 24 |
Oct 15 11:36:07 AM UTC 24 |
36648377 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.618409667 |
|
|
Oct 15 11:36:05 AM UTC 24 |
Oct 15 11:36:07 AM UTC 24 |
19353459 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.700080009 |
|
|
Oct 15 11:34:53 AM UTC 24 |
Oct 15 11:36:08 AM UTC 24 |
2989718840 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.3115737343 |
|
|
Oct 15 11:33:13 AM UTC 24 |
Oct 15 11:36:09 AM UTC 24 |
10186716638 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.4199666578 |
|
|
Oct 15 11:35:57 AM UTC 24 |
Oct 15 11:36:09 AM UTC 24 |
265981081 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.462273995 |
|
|
Oct 15 11:36:07 AM UTC 24 |
Oct 15 11:36:11 AM UTC 24 |
296926565 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.3740311091 |
|
|
Oct 15 11:35:56 AM UTC 24 |
Oct 15 11:36:12 AM UTC 24 |
743034588 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2580663651 |
|
|
Oct 15 11:34:16 AM UTC 24 |
Oct 15 11:36:14 AM UTC 24 |
14075822540 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.2243234264 |
|
|
Oct 15 11:34:36 AM UTC 24 |
Oct 15 11:36:14 AM UTC 24 |
10804839230 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.942813874 |
|
|
Oct 15 11:36:12 AM UTC 24 |
Oct 15 11:36:14 AM UTC 24 |
16149074 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.298059745 |
|
|
Oct 15 11:35:56 AM UTC 24 |
Oct 15 11:36:15 AM UTC 24 |
2183051622 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.1707915981 |
|
|
Oct 15 11:35:56 AM UTC 24 |
Oct 15 11:36:15 AM UTC 24 |
1159189662 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.3285401552 |
|
|
Oct 15 11:36:04 AM UTC 24 |
Oct 15 11:36:16 AM UTC 24 |
59896329 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.4238185896 |
|
|
Oct 15 11:36:14 AM UTC 24 |
Oct 15 11:36:16 AM UTC 24 |
37504705 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.2120749664 |
|
|
Oct 15 11:36:06 AM UTC 24 |
Oct 15 11:36:17 AM UTC 24 |
240479302 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.3892042464 |
|
|
Oct 15 11:36:28 AM UTC 24 |
Oct 15 11:36:41 AM UTC 24 |
1038423547 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.855715315 |
|
|
Oct 15 11:36:13 AM UTC 24 |
Oct 15 11:36:19 AM UTC 24 |
40375924 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.1246820502 |
|
|
Oct 15 11:36:08 AM UTC 24 |
Oct 15 11:36:19 AM UTC 24 |
1108178043 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.679394531 |
|
|
Oct 15 11:36:17 AM UTC 24 |
Oct 15 11:36:20 AM UTC 24 |
54266401 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.4121348858 |
|
|
Oct 15 11:36:16 AM UTC 24 |
Oct 15 11:36:20 AM UTC 24 |
61722191 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.3911738186 |
|
|
Oct 15 11:36:06 AM UTC 24 |
Oct 15 11:36:21 AM UTC 24 |
1430990762 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.3171828293 |
|
|
Oct 15 11:35:53 AM UTC 24 |
Oct 15 11:36:22 AM UTC 24 |
350330572 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.2558396393 |
|
|
Oct 15 11:36:01 AM UTC 24 |
Oct 15 11:36:22 AM UTC 24 |
3087542409 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.3975894767 |
|
|
Oct 15 11:35:47 AM UTC 24 |
Oct 15 11:36:23 AM UTC 24 |
1158487638 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.1809280749 |
|
|
Oct 15 11:36:23 AM UTC 24 |
Oct 15 11:36:25 AM UTC 24 |
51467946 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.4084162942 |
|
|
Oct 15 11:36:24 AM UTC 24 |
Oct 15 11:36:26 AM UTC 24 |
47516690 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1390258263 |
|
|
Oct 15 11:35:04 AM UTC 24 |
Oct 15 11:36:28 AM UTC 24 |
7309979698 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.689711080 |
|
|
Oct 15 11:36:07 AM UTC 24 |
Oct 15 11:36:29 AM UTC 24 |
3429196400 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.370473649 |
|
|
Oct 15 11:36:03 AM UTC 24 |
Oct 15 11:36:29 AM UTC 24 |
256454094 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.4088275266 |
|
|
Oct 15 11:36:16 AM UTC 24 |
Oct 15 11:36:29 AM UTC 24 |
149642781 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.1054345097 |
|
|
Oct 15 11:36:17 AM UTC 24 |
Oct 15 11:36:29 AM UTC 24 |
189158762 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.4200275886 |
|
|
Oct 15 11:36:24 AM UTC 24 |
Oct 15 11:36:29 AM UTC 24 |
90647775 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.230799518 |
|
|
Oct 15 11:36:19 AM UTC 24 |
Oct 15 11:36:30 AM UTC 24 |
276627120 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2474701799 |
|
|
Oct 15 11:34:43 AM UTC 24 |
Oct 15 11:36:30 AM UTC 24 |
9277693230 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.2143492141 |
|
|
Oct 15 11:36:27 AM UTC 24 |
Oct 15 11:36:31 AM UTC 24 |
30337511 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.1275994911 |
|
|
Oct 15 11:36:20 AM UTC 24 |
Oct 15 11:36:32 AM UTC 24 |
626298583 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.2603569975 |
|
|
Oct 15 11:36:17 AM UTC 24 |
Oct 15 11:36:33 AM UTC 24 |
1230922184 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.1197666884 |
|
|
Oct 15 11:36:18 AM UTC 24 |
Oct 15 11:36:34 AM UTC 24 |
1772783944 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.810164600 |
|
|
Oct 15 11:36:32 AM UTC 24 |
Oct 15 11:36:35 AM UTC 24 |
31165594 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.1372878614 |
|
|
Oct 15 11:36:26 AM UTC 24 |
Oct 15 11:36:35 AM UTC 24 |
112859486 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.1306222684 |
|
|
Oct 15 11:36:34 AM UTC 24 |
Oct 15 11:36:36 AM UTC 24 |
76933849 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3588569009 |
|
|
Oct 15 11:36:35 AM UTC 24 |
Oct 15 11:36:37 AM UTC 24 |
13069386 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.3066089884 |
|
|
Oct 15 11:36:10 AM UTC 24 |
Oct 15 11:36:38 AM UTC 24 |
700138349 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.1244827455 |
|
|
Oct 15 11:36:30 AM UTC 24 |
Oct 15 11:36:39 AM UTC 24 |
255326056 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.3560390872 |
|
|
Oct 15 11:36:36 AM UTC 24 |
Oct 15 11:36:39 AM UTC 24 |
18394708 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.3673375342 |
|
|
Oct 15 11:31:26 AM UTC 24 |
Oct 15 11:36:40 AM UTC 24 |
12273305921 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.4073938193 |
|
|
Oct 15 11:36:30 AM UTC 24 |
Oct 15 11:36:41 AM UTC 24 |
4900309567 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.303302691 |
|
|
Oct 15 11:37:40 AM UTC 24 |
Oct 15 11:37:46 AM UTC 24 |
108090548 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.3355408145 |
|
|
Oct 15 11:36:30 AM UTC 24 |
Oct 15 11:36:41 AM UTC 24 |
1113585433 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.2561375768 |
|
|
Oct 15 11:36:30 AM UTC 24 |
Oct 15 11:36:41 AM UTC 24 |
1610404485 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.756398228 |
|
|
Oct 15 11:34:55 AM UTC 24 |
Oct 15 11:36:42 AM UTC 24 |
5254062834 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.1226557004 |
|
|
Oct 15 11:36:30 AM UTC 24 |
Oct 15 11:36:43 AM UTC 24 |
708949909 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.2008025374 |
|
|
Oct 15 11:35:27 AM UTC 24 |
Oct 15 11:36:43 AM UTC 24 |
4716903994 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2150587271 |
|
|
Oct 15 11:36:40 AM UTC 24 |
Oct 15 11:36:43 AM UTC 24 |
134722290 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.2270967958 |
|
|
Oct 15 11:36:43 AM UTC 24 |
Oct 15 11:36:44 AM UTC 24 |
60367663 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.2269912245 |
|
|
Oct 15 11:36:43 AM UTC 24 |
Oct 15 11:36:45 AM UTC 24 |
62777036 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3471461074 |
|
|
Oct 15 11:36:44 AM UTC 24 |
Oct 15 11:36:47 AM UTC 24 |
13267463 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.3145726126 |
|
|
Oct 15 11:36:36 AM UTC 24 |
Oct 15 11:36:47 AM UTC 24 |
195874613 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.3852404030 |
|
|
Oct 15 11:36:38 AM UTC 24 |
Oct 15 11:36:48 AM UTC 24 |
231818562 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.2716338962 |
|
|
Oct 15 11:36:44 AM UTC 24 |
Oct 15 11:36:50 AM UTC 24 |
317916042 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.1599161884 |
|
|
Oct 15 11:36:31 AM UTC 24 |
Oct 15 11:36:50 AM UTC 24 |
1177970543 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.2199905436 |
|
|
Oct 15 11:36:15 AM UTC 24 |
Oct 15 11:36:50 AM UTC 24 |
252160717 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.436491030 |
|
|
Oct 15 11:36:37 AM UTC 24 |
Oct 15 11:36:51 AM UTC 24 |
1185763357 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.3493512048 |
|
|
Oct 15 11:36:41 AM UTC 24 |
Oct 15 11:36:51 AM UTC 24 |
3094635251 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.208676744 |
|
|
Oct 15 11:32:20 AM UTC 24 |
Oct 15 11:36:51 AM UTC 24 |
7874823826 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.154050740 |
|
|
Oct 15 11:36:25 AM UTC 24 |
Oct 15 11:36:53 AM UTC 24 |
181505089 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2928949383 |
|
|
Oct 15 11:35:50 AM UTC 24 |
Oct 15 11:36:54 AM UTC 24 |
5423711974 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.2671664915 |
|
|
Oct 15 11:36:51 AM UTC 24 |
Oct 15 11:36:54 AM UTC 24 |
16415677 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.11830882 |
|
|
Oct 15 11:36:44 AM UTC 24 |
Oct 15 11:36:54 AM UTC 24 |
75007517 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.2272885688 |
|
|
Oct 15 11:36:48 AM UTC 24 |
Oct 15 11:36:55 AM UTC 24 |
303720721 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.4042459703 |
|
|
Oct 15 11:35:39 AM UTC 24 |
Oct 15 11:36:55 AM UTC 24 |
1377088834 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.862396525 |
|
|
Oct 15 11:36:53 AM UTC 24 |
Oct 15 11:36:55 AM UTC 24 |
22225517 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.1443823668 |
|
|
Oct 15 11:36:40 AM UTC 24 |
Oct 15 11:36:56 AM UTC 24 |
255158707 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1624841599 |
|
|
Oct 15 11:36:53 AM UTC 24 |
Oct 15 11:36:57 AM UTC 24 |
41980844 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.267183757 |
|
|
Oct 15 11:36:50 AM UTC 24 |
Oct 15 11:36:59 AM UTC 24 |
766713339 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.1091445652 |
|
|
Oct 15 11:36:45 AM UTC 24 |
Oct 15 11:37:00 AM UTC 24 |
368273108 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.4060767581 |
|
|
Oct 15 11:36:46 AM UTC 24 |
Oct 15 11:37:00 AM UTC 24 |
1150332250 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.600760063 |
|
|
Oct 15 11:36:48 AM UTC 24 |
Oct 15 11:37:00 AM UTC 24 |
226069218 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.1632440226 |
|
|
Oct 15 11:36:55 AM UTC 24 |
Oct 15 11:37:00 AM UTC 24 |
254436193 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.2762844706 |
|
|
Oct 15 11:36:55 AM UTC 24 |
Oct 15 11:37:00 AM UTC 24 |
97631317 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.2241030351 |
|
|
Oct 15 11:36:51 AM UTC 24 |
Oct 15 11:37:02 AM UTC 24 |
439904670 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.2126333259 |
|
|
Oct 15 11:36:56 AM UTC 24 |
Oct 15 11:37:03 AM UTC 24 |
791039118 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.4225442445 |
|
|
Oct 15 11:36:55 AM UTC 24 |
Oct 15 11:37:04 AM UTC 24 |
619607486 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3282873265 |
|
|
Oct 15 11:37:01 AM UTC 24 |
Oct 15 11:37:04 AM UTC 24 |
57816851 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.1313738055 |
|
|
Oct 15 11:37:01 AM UTC 24 |
Oct 15 11:37:04 AM UTC 24 |
102668794 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.1919920784 |
|
|
Oct 15 11:37:01 AM UTC 24 |
Oct 15 11:37:05 AM UTC 24 |
247739005 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.2870023096 |
|
|
Oct 15 11:36:56 AM UTC 24 |
Oct 15 11:37:06 AM UTC 24 |
751945190 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.1522575498 |
|
|
Oct 15 11:37:03 AM UTC 24 |
Oct 15 11:37:07 AM UTC 24 |
26575049 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.3751940044 |
|
|
Oct 15 11:36:41 AM UTC 24 |
Oct 15 11:37:09 AM UTC 24 |
3895616057 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.458157355 |
|
|
Oct 15 11:36:56 AM UTC 24 |
Oct 15 11:37:11 AM UTC 24 |
679568320 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.3265545251 |
|
|
Oct 15 11:37:01 AM UTC 24 |
Oct 15 11:37:11 AM UTC 24 |
170991121 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.3375707755 |
|
|
Oct 15 11:36:35 AM UTC 24 |
Oct 15 11:37:12 AM UTC 24 |
326949442 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.243617601 |
|
|
Oct 15 11:36:44 AM UTC 24 |
Oct 15 11:37:13 AM UTC 24 |
150263827 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.3782172744 |
|
|
Oct 15 11:37:11 AM UTC 24 |
Oct 15 11:37:14 AM UTC 24 |
14634689 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.964880816 |
|
|
Oct 15 11:36:55 AM UTC 24 |
Oct 15 11:37:14 AM UTC 24 |
3466336806 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2509955345 |
|
|
Oct 15 11:37:13 AM UTC 24 |
Oct 15 11:37:15 AM UTC 24 |
12808032 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.136072882 |
|
|
Oct 15 11:37:13 AM UTC 24 |
Oct 15 11:37:17 AM UTC 24 |
32165305 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.4005599202 |
|
|
Oct 15 11:36:57 AM UTC 24 |
Oct 15 11:37:18 AM UTC 24 |
3153197257 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.2388375718 |
|
|
Oct 15 11:37:03 AM UTC 24 |
Oct 15 11:37:18 AM UTC 24 |
1166642382 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.1805655632 |
|
|
Oct 15 11:37:07 AM UTC 24 |
Oct 15 11:37:19 AM UTC 24 |
1237692686 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.216074378 |
|
|
Oct 15 11:37:05 AM UTC 24 |
Oct 15 11:37:19 AM UTC 24 |
691074823 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.3003259624 |
|
|
Oct 15 11:37:06 AM UTC 24 |
Oct 15 11:37:19 AM UTC 24 |
379277196 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.109434722 |
|
|
Oct 15 11:37:20 AM UTC 24 |
Oct 15 11:37:45 AM UTC 24 |
554436204 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.3128198990 |
|
|
Oct 15 11:37:05 AM UTC 24 |
Oct 15 11:37:20 AM UTC 24 |
757770162 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.172163094 |
|
|
Oct 15 11:37:15 AM UTC 24 |
Oct 15 11:37:20 AM UTC 24 |
48178063 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.572254485 |
|
|
Oct 15 11:37:15 AM UTC 24 |
Oct 15 11:37:21 AM UTC 24 |
257983953 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3665859970 |
|
|
Oct 15 11:37:21 AM UTC 24 |
Oct 15 11:37:24 AM UTC 24 |
35741054 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.3218029676 |
|
|
Oct 15 11:37:21 AM UTC 24 |
Oct 15 11:37:24 AM UTC 24 |
54420424 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.4079749240 |
|
|
Oct 15 11:37:21 AM UTC 24 |
Oct 15 11:37:26 AM UTC 24 |
226575016 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.3436381746 |
|
|
Oct 15 11:36:53 AM UTC 24 |
Oct 15 11:37:26 AM UTC 24 |
458900915 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1149403908 |
|
|
Oct 15 11:37:16 AM UTC 24 |
Oct 15 11:37:28 AM UTC 24 |
1035393291 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.2997608829 |
|
|
Oct 15 11:37:05 AM UTC 24 |
Oct 15 11:37:28 AM UTC 24 |
3451908648 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.3906226209 |
|
|
Oct 15 11:37:18 AM UTC 24 |
Oct 15 11:37:30 AM UTC 24 |
10642805662 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.2414783574 |
|
|
Oct 15 11:37:27 AM UTC 24 |
Oct 15 11:37:30 AM UTC 24 |
17809096 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.1647255193 |
|
|
Oct 15 11:35:18 AM UTC 24 |
Oct 15 11:37:31 AM UTC 24 |
3794361782 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.2846451698 |
|
|
Oct 15 11:34:16 AM UTC 24 |
Oct 15 11:37:32 AM UTC 24 |
7270203913 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.2884856069 |
|
|
Oct 15 11:37:18 AM UTC 24 |
Oct 15 11:37:32 AM UTC 24 |
288308684 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.2348767964 |
|
|
Oct 15 11:37:20 AM UTC 24 |
Oct 15 11:37:32 AM UTC 24 |
1133751886 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.3759010902 |
|
|
Oct 15 11:37:26 AM UTC 24 |
Oct 15 11:37:32 AM UTC 24 |
103432192 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.2543415961 |
|
|
Oct 15 11:37:29 AM UTC 24 |
Oct 15 11:37:33 AM UTC 24 |
93665819 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.4011603302 |
|
|
Oct 15 11:37:20 AM UTC 24 |
Oct 15 11:37:34 AM UTC 24 |
2310297863 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.2955060647 |
|
|
Oct 15 11:37:34 AM UTC 24 |
Oct 15 11:37:36 AM UTC 24 |
19830533 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3091343719 |
|
|
Oct 15 11:37:35 AM UTC 24 |
Oct 15 11:37:37 AM UTC 24 |
14070129 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.2711871064 |
|
|
Oct 15 11:37:34 AM UTC 24 |
Oct 15 11:37:38 AM UTC 24 |
115091648 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.3705471527 |
|
|
Oct 15 11:37:29 AM UTC 24 |
Oct 15 11:37:40 AM UTC 24 |
1570466506 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.3595694998 |
|
|
Oct 15 11:37:01 AM UTC 24 |
Oct 15 11:37:40 AM UTC 24 |
337703292 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1665839777 |
|
|
Oct 15 11:36:11 AM UTC 24 |
Oct 15 11:37:40 AM UTC 24 |
15620154936 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.3402121703 |
|
|
Oct 15 11:37:38 AM UTC 24 |
Oct 15 11:37:42 AM UTC 24 |
146108274 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.2348783113 |
|
|
Oct 15 11:37:33 AM UTC 24 |
Oct 15 11:37:46 AM UTC 24 |
753901649 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.1884028883 |
|
|
Oct 15 11:37:31 AM UTC 24 |
Oct 15 11:37:46 AM UTC 24 |
357108969 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.3097270530 |
|
|
Oct 15 11:37:27 AM UTC 24 |
Oct 15 11:37:47 AM UTC 24 |
643255212 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.3882528582 |
|
|
Oct 15 11:37:37 AM UTC 24 |
Oct 15 11:37:48 AM UTC 24 |
768522225 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.2467892317 |
|
|
Oct 15 11:34:43 AM UTC 24 |
Oct 15 11:37:48 AM UTC 24 |
11794356866 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.1371825114 |
|
|
Oct 15 11:37:15 AM UTC 24 |
Oct 15 11:37:49 AM UTC 24 |
307052205 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.592533904 |
|
|
Oct 15 11:37:47 AM UTC 24 |
Oct 15 11:37:49 AM UTC 24 |
46752134 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1520416187 |
|
|
Oct 15 11:37:48 AM UTC 24 |
Oct 15 11:37:51 AM UTC 24 |
14695808 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.3553542463 |
|
|
Oct 15 11:37:47 AM UTC 24 |
Oct 15 11:37:51 AM UTC 24 |
33033192 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.3717364473 |
|
|
Oct 15 11:37:48 AM UTC 24 |
Oct 15 11:37:52 AM UTC 24 |
34120124 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.650774124 |
|
|
Oct 15 11:37:48 AM UTC 24 |
Oct 15 11:37:53 AM UTC 24 |
257063607 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.1977410444 |
|
|
Oct 15 11:37:50 AM UTC 24 |
Oct 15 11:37:53 AM UTC 24 |
118930891 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.2192206885 |
|
|
Oct 15 11:37:24 AM UTC 24 |
Oct 15 11:37:53 AM UTC 24 |
252334269 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.4245259061 |
|
|
Oct 15 11:37:35 AM UTC 24 |
Oct 15 11:37:54 AM UTC 24 |
304723434 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.3187419162 |
|
|
Oct 15 11:37:40 AM UTC 24 |
Oct 15 11:37:56 AM UTC 24 |
731141607 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.1730295662 |
|
|
Oct 15 11:37:43 AM UTC 24 |
Oct 15 11:37:57 AM UTC 24 |
348098429 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.725964038 |
|
|
Oct 15 11:37:42 AM UTC 24 |
Oct 15 11:37:57 AM UTC 24 |
346343782 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.885904780 |
|
|
Oct 15 11:37:55 AM UTC 24 |
Oct 15 11:37:57 AM UTC 24 |
24867396 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2720825778 |
|
|
Oct 15 11:37:55 AM UTC 24 |
Oct 15 11:37:57 AM UTC 24 |
21705105 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.303951889 |
|
|
Oct 15 11:37:49 AM UTC 24 |
Oct 15 11:37:57 AM UTC 24 |
670841752 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.2390754024 |
|
|
Oct 15 11:37:55 AM UTC 24 |
Oct 15 11:37:58 AM UTC 24 |
37844566 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.294117693 |
|
|
Oct 15 11:35:19 AM UTC 24 |
Oct 15 11:37:59 AM UTC 24 |
4308054847 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.2456025036 |
|
|
Oct 15 11:37:50 AM UTC 24 |
Oct 15 11:38:00 AM UTC 24 |
204021676 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.3769233581 |
|
|
Oct 15 11:37:42 AM UTC 24 |
Oct 15 11:38:00 AM UTC 24 |
321053480 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.2069866353 |
|
|
Oct 15 11:37:38 AM UTC 24 |
Oct 15 11:38:00 AM UTC 24 |
709181193 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.377502814 |
|
|
Oct 15 11:37:57 AM UTC 24 |
Oct 15 11:38:02 AM UTC 24 |
718706628 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.787864767 |
|
|
Oct 15 11:38:01 AM UTC 24 |
Oct 15 11:38:04 AM UTC 24 |
37663021 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.243672040 |
|
|
Oct 15 11:34:26 AM UTC 24 |
Oct 15 11:38:04 AM UTC 24 |
28354657162 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.3180154201 |
|
|
Oct 15 11:37:50 AM UTC 24 |
Oct 15 11:38:05 AM UTC 24 |
500323913 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.3316078203 |
|
|
Oct 15 11:37:59 AM UTC 24 |
Oct 15 11:38:06 AM UTC 24 |
2366848055 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3182280449 |
|
|
Oct 15 11:38:05 AM UTC 24 |
Oct 15 11:38:07 AM UTC 24 |
22064887 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.900845805 |
|
|
Oct 15 11:38:18 AM UTC 24 |
Oct 15 11:38:42 AM UTC 24 |
571924797 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.2879239264 |
|
|
Oct 15 11:37:52 AM UTC 24 |
Oct 15 11:38:07 AM UTC 24 |
1134978286 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.3015482719 |
|
|
Oct 15 11:38:03 AM UTC 24 |
Oct 15 11:38:08 AM UTC 24 |
122953268 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.2434826680 |
|
|
Oct 15 11:37:51 AM UTC 24 |
Oct 15 11:38:08 AM UTC 24 |
2511385290 ps |