| T625 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.95079726 |
|
|
Feb 09 02:34:19 PM UTC 25 |
Feb 09 02:34:57 PM UTC 25 |
267509561 ps |
| T626 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.806925919 |
|
|
Feb 09 02:34:54 PM UTC 25 |
Feb 09 02:34:59 PM UTC 25 |
311010713 ps |
| T627 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.1984399448 |
|
|
Feb 09 02:34:58 PM UTC 25 |
Feb 09 02:35:00 PM UTC 25 |
14828044 ps |
| T628 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.2238624144 |
|
|
Feb 09 02:33:34 PM UTC 25 |
Feb 09 02:35:02 PM UTC 25 |
7976222689 ps |
| T629 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.701318135 |
|
|
Feb 09 02:35:01 PM UTC 25 |
Feb 09 02:35:03 PM UTC 25 |
48421434 ps |
| T630 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.3291388514 |
|
|
Feb 09 02:35:00 PM UTC 25 |
Feb 09 02:35:05 PM UTC 25 |
810307242 ps |
| T631 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.941875662 |
|
|
Feb 09 02:34:52 PM UTC 25 |
Feb 09 02:35:05 PM UTC 25 |
52451738 ps |
| T632 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.122916879 |
|
|
Feb 09 02:34:55 PM UTC 25 |
Feb 09 02:35:07 PM UTC 25 |
374823443 ps |
| T633 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.1758354576 |
|
|
Feb 09 02:34:54 PM UTC 25 |
Feb 09 02:35:08 PM UTC 25 |
684614341 ps |
| T634 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.233369749 |
|
|
Feb 09 02:34:54 PM UTC 25 |
Feb 09 02:35:08 PM UTC 25 |
1262772161 ps |
| T635 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.2094497103 |
|
|
Feb 09 02:35:04 PM UTC 25 |
Feb 09 02:35:09 PM UTC 25 |
118026994 ps |
| T636 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.1138636967 |
|
|
Feb 09 02:35:05 PM UTC 25 |
Feb 09 02:35:12 PM UTC 25 |
367627702 ps |
| T637 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.1498763251 |
|
|
Feb 09 02:34:55 PM UTC 25 |
Feb 09 02:35:13 PM UTC 25 |
367158194 ps |
| T638 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.2396806572 |
|
|
Feb 09 02:35:09 PM UTC 25 |
Feb 09 02:35:16 PM UTC 25 |
1125962681 ps |
| T639 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.3872358516 |
|
|
Feb 09 02:35:10 PM UTC 25 |
Feb 09 02:35:21 PM UTC 25 |
177990519 ps |
| T640 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.2368680199 |
|
|
Feb 09 02:35:08 PM UTC 25 |
Feb 09 02:35:22 PM UTC 25 |
461732888 ps |
| T641 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.1155606922 |
|
|
Feb 09 02:35:09 PM UTC 25 |
Feb 09 02:35:24 PM UTC 25 |
1323989678 ps |
| T642 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.2441666817 |
|
|
Feb 09 02:35:22 PM UTC 25 |
Feb 09 02:35:25 PM UTC 25 |
61070687 ps |
| T643 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.3915543243 |
|
|
Feb 09 02:34:58 PM UTC 25 |
Feb 09 02:35:26 PM UTC 25 |
1735487444 ps |
| T644 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.3526739572 |
|
|
Feb 09 02:35:06 PM UTC 25 |
Feb 09 02:35:27 PM UTC 25 |
349633924 ps |
| T645 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2288583676 |
|
|
Feb 09 02:35:25 PM UTC 25 |
Feb 09 02:35:27 PM UTC 25 |
66721969 ps |
| T646 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.3649210372 |
|
|
Feb 09 02:35:24 PM UTC 25 |
Feb 09 02:35:28 PM UTC 25 |
276053566 ps |
| T647 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.3728810566 |
|
|
Feb 09 02:34:12 PM UTC 25 |
Feb 09 02:35:30 PM UTC 25 |
6642695800 ps |
| T648 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.1559374789 |
|
|
Feb 09 02:36:10 PM UTC 25 |
Feb 09 02:36:21 PM UTC 25 |
266915152 ps |
| T649 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.2704256339 |
|
|
Feb 09 02:34:33 PM UTC 25 |
Feb 09 02:35:31 PM UTC 25 |
264818588 ps |
| T650 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.3796068273 |
|
|
Feb 09 02:35:28 PM UTC 25 |
Feb 09 02:35:33 PM UTC 25 |
153172597 ps |
| T651 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.1828221116 |
|
|
Feb 09 02:35:03 PM UTC 25 |
Feb 09 02:35:33 PM UTC 25 |
617126765 ps |
| T652 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.2946703678 |
|
|
Feb 09 02:35:27 PM UTC 25 |
Feb 09 02:35:35 PM UTC 25 |
382930442 ps |
| T653 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.3063195119 |
|
|
Feb 09 02:35:30 PM UTC 25 |
Feb 09 02:35:39 PM UTC 25 |
346037272 ps |
| T654 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.717288931 |
|
|
Feb 09 02:35:39 PM UTC 25 |
Feb 09 02:35:42 PM UTC 25 |
30493882 ps |
| T655 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.1816086511 |
|
|
Feb 09 02:35:32 PM UTC 25 |
Feb 09 02:35:46 PM UTC 25 |
1167539054 ps |
| T656 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.664543958 |
|
|
Feb 09 02:35:29 PM UTC 25 |
Feb 09 02:35:46 PM UTC 25 |
2817601242 ps |
| T657 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_errors.3912020204 |
|
|
Feb 09 02:35:28 PM UTC 25 |
Feb 09 02:35:46 PM UTC 25 |
3903795825 ps |
| T658 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.1277502696 |
|
|
Feb 09 02:35:13 PM UTC 25 |
Feb 09 02:35:46 PM UTC 25 |
1862695538 ps |
| T89 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.3082118669 |
|
|
Feb 09 02:35:42 PM UTC 25 |
Feb 09 02:35:48 PM UTC 25 |
348514256 ps |
| T659 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2461571796 |
|
|
Feb 09 02:35:46 PM UTC 25 |
Feb 09 02:35:49 PM UTC 25 |
13309904 ps |
| T660 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.565532184 |
|
|
Feb 09 02:35:34 PM UTC 25 |
Feb 09 02:35:49 PM UTC 25 |
401148121 ps |
| T661 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.1010788709 |
|
|
Feb 09 02:35:48 PM UTC 25 |
Feb 09 02:35:55 PM UTC 25 |
376068587 ps |
| T662 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.3761415337 |
|
|
Feb 09 02:34:51 PM UTC 25 |
Feb 09 02:35:58 PM UTC 25 |
3347355015 ps |
| T663 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.1000319105 |
|
|
Feb 09 02:35:50 PM UTC 25 |
Feb 09 02:36:02 PM UTC 25 |
1007544865 ps |
| T664 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.1699301059 |
|
|
Feb 09 02:35:32 PM UTC 25 |
Feb 09 02:36:02 PM UTC 25 |
2127775297 ps |
| T665 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.2231995962 |
|
|
Feb 09 02:35:48 PM UTC 25 |
Feb 09 02:36:02 PM UTC 25 |
85293130 ps |
| T666 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.2055862462 |
|
|
Feb 09 02:35:50 PM UTC 25 |
Feb 09 02:36:03 PM UTC 25 |
1993614745 ps |
| T667 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.1831693060 |
|
|
Feb 09 02:35:26 PM UTC 25 |
Feb 09 02:36:05 PM UTC 25 |
3962952272 ps |
| T668 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.2356528212 |
|
|
Feb 09 02:35:49 PM UTC 25 |
Feb 09 02:36:06 PM UTC 25 |
632421192 ps |
| T669 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.3743834368 |
|
|
Feb 09 02:36:03 PM UTC 25 |
Feb 09 02:36:06 PM UTC 25 |
23385044 ps |
| T670 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.4197797152 |
|
|
Feb 09 02:36:03 PM UTC 25 |
Feb 09 02:36:06 PM UTC 25 |
35806321 ps |
| T671 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.202722700 |
|
|
Feb 09 02:36:04 PM UTC 25 |
Feb 09 02:36:07 PM UTC 25 |
41521715 ps |
| T82 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2165210761 |
|
|
Feb 09 02:26:29 PM UTC 25 |
Feb 09 02:36:07 PM UTC 25 |
18507981212 ps |
| T162 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.724226344 |
|
|
Feb 09 02:33:46 PM UTC 25 |
Feb 09 02:36:08 PM UTC 25 |
3755417175 ps |
| T163 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.3385063343 |
|
|
Feb 09 02:32:28 PM UTC 25 |
Feb 09 02:36:08 PM UTC 25 |
11334539468 ps |
| T164 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.2071843018 |
|
|
Feb 09 02:35:49 PM UTC 25 |
Feb 09 02:36:10 PM UTC 25 |
1676375291 ps |
| T165 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.2474990781 |
|
|
Feb 09 02:35:58 PM UTC 25 |
Feb 09 02:36:12 PM UTC 25 |
553446412 ps |
| T166 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.3488276834 |
|
|
Feb 09 02:36:07 PM UTC 25 |
Feb 09 02:36:13 PM UTC 25 |
164794082 ps |
| T167 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.3354401307 |
|
|
Feb 09 02:36:07 PM UTC 25 |
Feb 09 02:36:13 PM UTC 25 |
194454015 ps |
| T168 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.456503607 |
|
|
Feb 09 02:35:56 PM UTC 25 |
Feb 09 02:36:13 PM UTC 25 |
1298018895 ps |
| T169 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.475917599 |
|
|
Feb 09 02:36:14 PM UTC 25 |
Feb 09 02:36:16 PM UTC 25 |
15780543 ps |
| T170 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.3398102142 |
|
|
Feb 09 02:36:10 PM UTC 25 |
Feb 09 02:36:19 PM UTC 25 |
262578137 ps |
| T672 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.1062278377 |
|
|
Feb 09 02:36:14 PM UTC 25 |
Feb 09 02:36:20 PM UTC 25 |
185006736 ps |
| T673 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.881728815 |
|
|
Feb 09 02:36:17 PM UTC 25 |
Feb 09 02:36:20 PM UTC 25 |
19630829 ps |
| T674 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_errors.291175581 |
|
|
Feb 09 02:36:07 PM UTC 25 |
Feb 09 02:36:20 PM UTC 25 |
1107549225 ps |
| T675 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.3146141441 |
|
|
Feb 09 02:36:10 PM UTC 25 |
Feb 09 02:36:25 PM UTC 25 |
366136453 ps |
| T676 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.4069765465 |
|
|
Feb 09 02:36:21 PM UTC 25 |
Feb 09 02:36:26 PM UTC 25 |
213076769 ps |
| T677 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.1056501840 |
|
|
Feb 09 02:36:10 PM UTC 25 |
Feb 09 02:36:26 PM UTC 25 |
419673340 ps |
| T678 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.3896867596 |
|
|
Feb 09 02:36:11 PM UTC 25 |
Feb 09 02:36:26 PM UTC 25 |
3203225008 ps |
| T679 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.100601447 |
|
|
Feb 09 02:31:42 PM UTC 25 |
Feb 09 02:36:26 PM UTC 25 |
45478441740 ps |
| T680 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.2615347836 |
|
|
Feb 09 02:36:21 PM UTC 25 |
Feb 09 02:36:30 PM UTC 25 |
1485618883 ps |
| T681 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.307147409 |
|
|
Feb 09 02:36:21 PM UTC 25 |
Feb 09 02:36:31 PM UTC 25 |
217610782 ps |
| T107 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.735596453 |
|
|
Feb 09 02:25:34 PM UTC 25 |
Feb 09 02:36:34 PM UTC 25 |
74546931980 ps |
| T200 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.2667076525 |
|
|
Feb 09 02:36:32 PM UTC 25 |
Feb 09 02:36:34 PM UTC 25 |
35694890 ps |
| T201 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.658788079 |
|
|
Feb 09 02:36:32 PM UTC 25 |
Feb 09 02:36:36 PM UTC 25 |
34314009 ps |
| T202 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.1257217541 |
|
|
Feb 09 02:36:21 PM UTC 25 |
Feb 09 02:36:36 PM UTC 25 |
73167388 ps |
| T203 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.1904168026 |
|
|
Feb 09 02:36:27 PM UTC 25 |
Feb 09 02:36:38 PM UTC 25 |
279512338 ps |
| T204 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1516839852 |
|
|
Feb 09 02:36:36 PM UTC 25 |
Feb 09 02:36:38 PM UTC 25 |
40438301 ps |
| T205 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.2483620552 |
|
|
Feb 09 02:36:27 PM UTC 25 |
Feb 09 02:36:38 PM UTC 25 |
243315037 ps |
| T206 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.1979393333 |
|
|
Feb 09 02:36:26 PM UTC 25 |
Feb 09 02:36:39 PM UTC 25 |
308801646 ps |
| T207 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.130414291 |
|
|
Feb 09 02:36:21 PM UTC 25 |
Feb 09 02:36:39 PM UTC 25 |
1144388945 ps |
| T208 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.1947777253 |
|
|
Feb 09 02:35:46 PM UTC 25 |
Feb 09 02:36:41 PM UTC 25 |
229168174 ps |
| T682 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3033188411 |
|
|
Feb 09 02:36:37 PM UTC 25 |
Feb 09 02:36:42 PM UTC 25 |
79222150 ps |
| T683 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.2205617904 |
|
|
Feb 09 02:34:28 PM UTC 25 |
Feb 09 02:36:45 PM UTC 25 |
10210507882 ps |
| T684 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.517570240 |
|
|
Feb 09 02:36:37 PM UTC 25 |
Feb 09 02:36:48 PM UTC 25 |
213669253 ps |
| T685 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.2470176433 |
|
|
Feb 09 02:36:39 PM UTC 25 |
Feb 09 02:36:51 PM UTC 25 |
614298384 ps |
| T686 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.3448089870 |
|
|
Feb 09 02:36:07 PM UTC 25 |
Feb 09 02:36:51 PM UTC 25 |
1089297471 ps |
| T687 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.3714719683 |
|
|
Feb 09 02:36:49 PM UTC 25 |
Feb 09 02:36:51 PM UTC 25 |
25462726 ps |
| T688 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.1085159042 |
|
|
Feb 09 02:36:40 PM UTC 25 |
Feb 09 02:36:54 PM UTC 25 |
546978198 ps |
| T689 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1475278851 |
|
|
Feb 09 02:36:52 PM UTC 25 |
Feb 09 02:36:54 PM UTC 25 |
26032603 ps |
| T690 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.2619701057 |
|
|
Feb 09 02:36:51 PM UTC 25 |
Feb 09 02:36:57 PM UTC 25 |
126677795 ps |
| T691 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.1088947184 |
|
|
Feb 09 02:36:39 PM UTC 25 |
Feb 09 02:36:57 PM UTC 25 |
538980801 ps |
| T692 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.2404736914 |
|
|
Feb 09 02:36:39 PM UTC 25 |
Feb 09 02:36:58 PM UTC 25 |
2406801086 ps |
| T693 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.1512574019 |
|
|
Feb 09 02:35:59 PM UTC 25 |
Feb 09 02:36:59 PM UTC 25 |
7518826247 ps |
| T694 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.501815123 |
|
|
Feb 09 02:36:55 PM UTC 25 |
Feb 09 02:37:00 PM UTC 25 |
123375139 ps |
| T695 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.630404657 |
|
|
Feb 09 02:36:42 PM UTC 25 |
Feb 09 02:37:01 PM UTC 25 |
1830604009 ps |
| T90 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.3091310399 |
|
|
Feb 09 02:36:43 PM UTC 25 |
Feb 09 02:37:03 PM UTC 25 |
1605344995 ps |
| T696 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.1960388567 |
|
|
Feb 09 02:36:54 PM UTC 25 |
Feb 09 02:37:06 PM UTC 25 |
249491825 ps |
| T60 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3782358565 |
|
|
Feb 09 02:29:56 PM UTC 25 |
Feb 09 02:37:08 PM UTC 25 |
18374075686 ps |
| T697 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.3644711711 |
|
|
Feb 09 02:36:40 PM UTC 25 |
Feb 09 02:37:08 PM UTC 25 |
818766312 ps |
| T698 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.911893460 |
|
|
Feb 09 02:36:59 PM UTC 25 |
Feb 09 02:37:09 PM UTC 25 |
2952209466 ps |
| T699 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.754493798 |
|
|
Feb 09 02:37:01 PM UTC 25 |
Feb 09 02:37:11 PM UTC 25 |
263590411 ps |
| T700 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.4176823437 |
|
|
Feb 09 02:36:58 PM UTC 25 |
Feb 09 02:37:11 PM UTC 25 |
374686702 ps |
| T701 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.929148320 |
|
|
Feb 09 02:37:10 PM UTC 25 |
Feb 09 02:37:12 PM UTC 25 |
14404660 ps |
| T702 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.3928793890 |
|
|
Feb 09 02:37:10 PM UTC 25 |
Feb 09 02:37:13 PM UTC 25 |
33720607 ps |
| T703 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.2776967329 |
|
|
Feb 09 02:37:10 PM UTC 25 |
Feb 09 02:37:13 PM UTC 25 |
44616165 ps |
| T704 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.2955531338 |
|
|
Feb 09 02:37:00 PM UTC 25 |
Feb 09 02:37:14 PM UTC 25 |
725220797 ps |
| T705 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.2544681182 |
|
|
Feb 09 02:37:01 PM UTC 25 |
Feb 09 02:37:15 PM UTC 25 |
481065468 ps |
| T706 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.1155890671 |
|
|
Feb 09 02:36:58 PM UTC 25 |
Feb 09 02:37:16 PM UTC 25 |
479167504 ps |
| T707 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.1391252180 |
|
|
Feb 09 02:37:12 PM UTC 25 |
Feb 09 02:37:17 PM UTC 25 |
150506154 ps |
| T708 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.2737115593 |
|
|
Feb 09 02:34:44 PM UTC 25 |
Feb 09 02:37:17 PM UTC 25 |
5489583232 ps |
| T709 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.2002611177 |
|
|
Feb 09 02:32:52 PM UTC 25 |
Feb 09 02:37:17 PM UTC 25 |
27315768000 ps |
| T710 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.788808955 |
|
|
Feb 09 02:37:14 PM UTC 25 |
Feb 09 02:37:18 PM UTC 25 |
137362522 ps |
| T711 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.4290181651 |
|
|
Feb 09 02:36:21 PM UTC 25 |
Feb 09 02:37:20 PM UTC 25 |
4640481147 ps |
| T712 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.3009086895 |
|
|
Feb 09 02:37:19 PM UTC 25 |
Feb 09 02:37:22 PM UTC 25 |
44080232 ps |
| T713 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.623526427 |
|
|
Feb 09 02:37:19 PM UTC 25 |
Feb 09 02:37:23 PM UTC 25 |
39793081 ps |
| T714 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.1244385962 |
|
|
Feb 09 02:37:14 PM UTC 25 |
Feb 09 02:37:23 PM UTC 25 |
505749833 ps |
| T715 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2402933619 |
|
|
Feb 09 02:37:22 PM UTC 25 |
Feb 09 02:37:24 PM UTC 25 |
13016033 ps |
| T716 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.189267955 |
|
|
Feb 09 02:37:16 PM UTC 25 |
Feb 09 02:37:26 PM UTC 25 |
1680247462 ps |
| T717 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.183597277 |
|
|
Feb 09 02:37:12 PM UTC 25 |
Feb 09 02:37:27 PM UTC 25 |
360228423 ps |
| T718 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.712464572 |
|
|
Feb 09 02:37:13 PM UTC 25 |
Feb 09 02:37:28 PM UTC 25 |
1398563686 ps |
| T719 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.3661573150 |
|
|
Feb 09 02:37:24 PM UTC 25 |
Feb 09 02:37:29 PM UTC 25 |
92301808 ps |
| T720 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.1965688918 |
|
|
Feb 09 02:36:36 PM UTC 25 |
Feb 09 02:37:30 PM UTC 25 |
1186810897 ps |
| T721 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.4106082163 |
|
|
Feb 09 02:37:18 PM UTC 25 |
Feb 09 02:37:32 PM UTC 25 |
977021253 ps |
| T722 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.2042165421 |
|
|
Feb 09 02:36:52 PM UTC 25 |
Feb 09 02:37:32 PM UTC 25 |
2083048852 ps |
| T723 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.2145526876 |
|
|
Feb 09 02:37:15 PM UTC 25 |
Feb 09 02:37:33 PM UTC 25 |
382390880 ps |
| T724 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.4272005760 |
|
|
Feb 09 02:37:28 PM UTC 25 |
Feb 09 02:37:34 PM UTC 25 |
849056208 ps |
| T725 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.4141287730 |
|
|
Feb 09 02:37:33 PM UTC 25 |
Feb 09 02:37:35 PM UTC 25 |
17584919 ps |
| T726 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.2985660933 |
|
|
Feb 09 02:33:20 PM UTC 25 |
Feb 09 02:37:35 PM UTC 25 |
17978588036 ps |
| T727 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.4131052013 |
|
|
Feb 09 02:37:35 PM UTC 25 |
Feb 09 02:37:37 PM UTC 25 |
19580189 ps |
| T148 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.652707478 |
|
|
Feb 09 02:34:15 PM UTC 25 |
Feb 09 02:37:37 PM UTC 25 |
8373346524 ps |
| T728 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.1424470647 |
|
|
Feb 09 02:37:24 PM UTC 25 |
Feb 09 02:37:38 PM UTC 25 |
187547671 ps |
| T729 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.3807344966 |
|
|
Feb 09 02:37:34 PM UTC 25 |
Feb 09 02:37:39 PM UTC 25 |
92564048 ps |
| T171 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.3845439678 |
|
|
Feb 09 02:37:27 PM UTC 25 |
Feb 09 02:37:40 PM UTC 25 |
395817198 ps |
| T730 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.1624635661 |
|
|
Feb 09 02:37:29 PM UTC 25 |
Feb 09 02:37:42 PM UTC 25 |
829389862 ps |
| T731 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.4280206185 |
|
|
Feb 09 02:37:39 PM UTC 25 |
Feb 09 02:37:44 PM UTC 25 |
58056578 ps |
| T732 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.3233415324 |
|
|
Feb 09 02:37:12 PM UTC 25 |
Feb 09 02:37:45 PM UTC 25 |
846782591 ps |
| T733 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.1345999226 |
|
|
Feb 09 02:37:29 PM UTC 25 |
Feb 09 02:37:46 PM UTC 25 |
821009077 ps |
| T734 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.1260017340 |
|
|
Feb 09 02:37:29 PM UTC 25 |
Feb 09 02:37:47 PM UTC 25 |
504531584 ps |
| T735 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.2732306339 |
|
|
Feb 09 02:37:25 PM UTC 25 |
Feb 09 02:37:48 PM UTC 25 |
2110524932 ps |
| T736 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.2529137500 |
|
|
Feb 09 02:37:48 PM UTC 25 |
Feb 09 02:37:51 PM UTC 25 |
67680762 ps |
| T737 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.2345309625 |
|
|
Feb 09 02:37:42 PM UTC 25 |
Feb 09 02:37:53 PM UTC 25 |
992308754 ps |
| T738 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.3423064425 |
|
|
Feb 09 02:37:40 PM UTC 25 |
Feb 09 02:37:53 PM UTC 25 |
1403373196 ps |
| T739 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.4170294794 |
|
|
Feb 09 02:37:49 PM UTC 25 |
Feb 09 02:37:54 PM UTC 25 |
202832013 ps |
| T740 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3722198410 |
|
|
Feb 09 02:37:51 PM UTC 25 |
Feb 09 02:37:54 PM UTC 25 |
20299782 ps |
| T741 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.2719289087 |
|
|
Feb 09 02:37:39 PM UTC 25 |
Feb 09 02:37:56 PM UTC 25 |
1916667303 ps |
| T742 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.2731918728 |
|
|
Feb 09 02:37:36 PM UTC 25 |
Feb 09 02:37:56 PM UTC 25 |
104685506 ps |
| T743 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.3201570516 |
|
|
Feb 09 02:37:39 PM UTC 25 |
Feb 09 02:37:57 PM UTC 25 |
643326788 ps |
| T150 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3434881284 |
|
|
Feb 09 02:27:53 PM UTC 25 |
Feb 09 02:37:59 PM UTC 25 |
56899480191 ps |
| T744 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.3939136893 |
|
|
Feb 09 02:36:13 PM UTC 25 |
Feb 09 02:38:00 PM UTC 25 |
4926803209 ps |
| T745 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.1127077454 |
|
|
Feb 09 02:37:54 PM UTC 25 |
Feb 09 02:38:00 PM UTC 25 |
70189274 ps |
| T746 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.2886207565 |
|
|
Feb 09 02:34:00 PM UTC 25 |
Feb 09 02:38:01 PM UTC 25 |
25435469844 ps |
| T747 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.3614995762 |
|
|
Feb 09 02:37:44 PM UTC 25 |
Feb 09 02:38:01 PM UTC 25 |
616021030 ps |
| T748 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.1536481917 |
|
|
Feb 09 02:37:41 PM UTC 25 |
Feb 09 02:38:01 PM UTC 25 |
1390580069 ps |
| T749 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.3826585798 |
|
|
Feb 09 02:37:23 PM UTC 25 |
Feb 09 02:38:02 PM UTC 25 |
578279765 ps |
| T750 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.1180139559 |
|
|
Feb 09 02:38:03 PM UTC 25 |
Feb 09 02:38:05 PM UTC 25 |
101314665 ps |
| T751 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.569382383 |
|
|
Feb 09 02:38:03 PM UTC 25 |
Feb 09 02:38:06 PM UTC 25 |
17295262 ps |
| T752 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.110203467 |
|
|
Feb 09 02:38:03 PM UTC 25 |
Feb 09 02:38:07 PM UTC 25 |
407730084 ps |
| T753 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.558423784 |
|
|
Feb 09 02:37:57 PM UTC 25 |
Feb 09 02:38:10 PM UTC 25 |
3011943455 ps |
| T754 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.2173053701 |
|
|
Feb 09 02:37:54 PM UTC 25 |
Feb 09 02:38:10 PM UTC 25 |
71567589 ps |
| T755 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.1836223868 |
|
|
Feb 09 02:38:06 PM UTC 25 |
Feb 09 02:38:10 PM UTC 25 |
96846285 ps |
| T756 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.4187492006 |
|
|
Feb 09 02:37:59 PM UTC 25 |
Feb 09 02:38:13 PM UTC 25 |
207737888 ps |
| T757 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.3962114239 |
|
|
Feb 09 02:38:03 PM UTC 25 |
Feb 09 02:38:14 PM UTC 25 |
524476282 ps |
| T758 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.3775388496 |
|
|
Feb 09 02:38:06 PM UTC 25 |
Feb 09 02:38:16 PM UTC 25 |
137346404 ps |
| T759 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.2605107007 |
|
|
Feb 09 02:37:55 PM UTC 25 |
Feb 09 02:38:17 PM UTC 25 |
1956205629 ps |
| T760 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.65960827 |
|
|
Feb 09 02:38:11 PM UTC 25 |
Feb 09 02:38:19 PM UTC 25 |
651199582 ps |
| T761 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.2073813760 |
|
|
Feb 09 02:37:36 PM UTC 25 |
Feb 09 02:38:19 PM UTC 25 |
1267777265 ps |
| T762 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.2180066339 |
|
|
Feb 09 02:37:58 PM UTC 25 |
Feb 09 02:38:22 PM UTC 25 |
785832932 ps |
| T763 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.2866750479 |
|
|
Feb 09 02:37:58 PM UTC 25 |
Feb 09 02:38:22 PM UTC 25 |
735856380 ps |
| T764 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.3788893009 |
|
|
Feb 09 02:38:20 PM UTC 25 |
Feb 09 02:38:23 PM UTC 25 |
12970669 ps |
| T765 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.2181765754 |
|
|
Feb 09 02:38:20 PM UTC 25 |
Feb 09 02:38:23 PM UTC 25 |
17858849 ps |
| T766 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3935361676 |
|
|
Feb 09 02:38:22 PM UTC 25 |
Feb 09 02:38:25 PM UTC 25 |
43218012 ps |
| T767 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.3945161281 |
|
|
Feb 09 02:38:10 PM UTC 25 |
Feb 09 02:38:26 PM UTC 25 |
344906391 ps |
| T768 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.3442542796 |
|
|
Feb 09 02:38:24 PM UTC 25 |
Feb 09 02:38:26 PM UTC 25 |
96928504 ps |
| T769 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.502175008 |
|
|
Feb 09 02:38:15 PM UTC 25 |
Feb 09 02:38:27 PM UTC 25 |
229634676 ps |
| T770 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.3822552398 |
|
|
Feb 09 02:38:11 PM UTC 25 |
Feb 09 02:38:28 PM UTC 25 |
1257670249 ps |
| T771 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.328986729 |
|
|
Feb 09 02:35:34 PM UTC 25 |
Feb 09 02:38:32 PM UTC 25 |
6769193721 ps |
| T772 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.2948193069 |
|
|
Feb 09 02:38:08 PM UTC 25 |
Feb 09 02:38:32 PM UTC 25 |
8402660102 ps |
| T773 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.3259405354 |
|
|
Feb 09 02:38:15 PM UTC 25 |
Feb 09 02:38:33 PM UTC 25 |
1013964270 ps |
| T774 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.121424573 |
|
|
Feb 09 02:38:24 PM UTC 25 |
Feb 09 02:38:35 PM UTC 25 |
494529416 ps |
| T775 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.2496435388 |
|
|
Feb 09 02:38:27 PM UTC 25 |
Feb 09 02:38:35 PM UTC 25 |
453987565 ps |
| T776 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.3380031848 |
|
|
Feb 09 02:38:36 PM UTC 25 |
Feb 09 02:38:38 PM UTC 25 |
69704790 ps |
| T777 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.806309319 |
|
|
Feb 09 02:38:27 PM UTC 25 |
Feb 09 02:38:40 PM UTC 25 |
216166794 ps |
| T778 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.741200444 |
|
|
Feb 09 02:38:36 PM UTC 25 |
Feb 09 02:38:40 PM UTC 25 |
34131684 ps |
| T779 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.291313116 |
|
|
Feb 09 02:39:23 PM UTC 25 |
Feb 09 02:39:44 PM UTC 25 |
1507038639 ps |
| T780 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.3836222858 |
|
|
Feb 09 02:38:26 PM UTC 25 |
Feb 09 02:38:41 PM UTC 25 |
390841238 ps |
| T781 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.255881068 |
|
|
Feb 09 02:38:04 PM UTC 25 |
Feb 09 02:38:42 PM UTC 25 |
1009743411 ps |
| T782 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.924234832 |
|
|
Feb 09 02:38:39 PM UTC 25 |
Feb 09 02:38:42 PM UTC 25 |
43717623 ps |
| T783 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.2961194842 |
|
|
Feb 09 02:38:33 PM UTC 25 |
Feb 09 02:38:43 PM UTC 25 |
977051927 ps |
| T784 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.3893470275 |
|
|
Feb 09 02:38:29 PM UTC 25 |
Feb 09 02:38:46 PM UTC 25 |
390018877 ps |
| T785 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.796540124 |
|
|
Feb 09 02:38:41 PM UTC 25 |
Feb 09 02:38:48 PM UTC 25 |
335433834 ps |
| T786 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.3019803708 |
|
|
Feb 09 02:38:28 PM UTC 25 |
Feb 09 02:38:48 PM UTC 25 |
317337626 ps |
| T787 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.4150532107 |
|
|
Feb 09 02:37:54 PM UTC 25 |
Feb 09 02:38:55 PM UTC 25 |
700728730 ps |
| T788 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1285325912 |
|
|
Feb 09 02:39:39 PM UTC 25 |
Feb 09 02:39:41 PM UTC 25 |
38384982 ps |
| T789 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.3096835979 |
|
|
Feb 09 02:38:41 PM UTC 25 |
Feb 09 02:38:57 PM UTC 25 |
84185839 ps |
| T790 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.3744917515 |
|
|
Feb 09 02:38:44 PM UTC 25 |
Feb 09 02:38:58 PM UTC 25 |
3446540063 ps |
| T791 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1695193331 |
|
|
Feb 09 02:38:58 PM UTC 25 |
Feb 09 02:39:00 PM UTC 25 |
62796947 ps |
| T792 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.3426722931 |
|
|
Feb 09 02:38:44 PM UTC 25 |
Feb 09 02:39:00 PM UTC 25 |
900300114 ps |
| T793 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.3783546797 |
|
|
Feb 09 02:38:58 PM UTC 25 |
Feb 09 02:39:01 PM UTC 25 |
63882391 ps |
| T794 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.1036580322 |
|
|
Feb 09 02:38:58 PM UTC 25 |
Feb 09 02:39:02 PM UTC 25 |
36834051 ps |
| T795 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.69741523 |
|
|
Feb 09 02:38:47 PM UTC 25 |
Feb 09 02:39:02 PM UTC 25 |
1566488901 ps |
| T796 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.1276961790 |
|
|
Feb 09 02:38:44 PM UTC 25 |
Feb 09 02:39:05 PM UTC 25 |
8586520652 ps |
| T797 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.1580060568 |
|
|
Feb 09 02:39:01 PM UTC 25 |
Feb 09 02:39:05 PM UTC 25 |
22489021 ps |
| T798 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.3343742123 |
|
|
Feb 09 02:38:49 PM UTC 25 |
Feb 09 02:39:05 PM UTC 25 |
374561578 ps |
| T799 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.298711854 |
|
|
Feb 09 02:38:44 PM UTC 25 |
Feb 09 02:39:06 PM UTC 25 |
1395494190 ps |
| T800 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.56546685 |
|
|
Feb 09 02:38:24 PM UTC 25 |
Feb 09 02:39:09 PM UTC 25 |
487647006 ps |
| T801 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.3006333074 |
|
|
Feb 09 02:39:06 PM UTC 25 |
Feb 09 02:39:14 PM UTC 25 |
596825531 ps |
| T802 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.2801101050 |
|
|
Feb 09 02:39:01 PM UTC 25 |
Feb 09 02:39:16 PM UTC 25 |
70372851 ps |
| T803 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.2752914728 |
|
|
Feb 09 02:39:06 PM UTC 25 |
Feb 09 02:39:17 PM UTC 25 |
1079143613 ps |
| T804 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.1073723141 |
|
|
Feb 09 02:39:03 PM UTC 25 |
Feb 09 02:39:18 PM UTC 25 |
2548561844 ps |
| T805 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.3698294195 |
|
|
Feb 09 02:39:17 PM UTC 25 |
Feb 09 02:39:19 PM UTC 25 |
67289639 ps |
| T806 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.3218679728 |
|
|
Feb 09 02:35:14 PM UTC 25 |
Feb 09 02:39:21 PM UTC 25 |
7075291384 ps |
| T807 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.850165642 |
|
|
Feb 09 02:39:19 PM UTC 25 |
Feb 09 02:39:21 PM UTC 25 |
26104307 ps |
| T808 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.3935799780 |
|
|
Feb 09 02:39:07 PM UTC 25 |
Feb 09 02:39:22 PM UTC 25 |
2050056313 ps |
| T809 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.2587420122 |
|
|
Feb 09 02:36:27 PM UTC 25 |
Feb 09 02:39:23 PM UTC 25 |
22530486374 ps |
| T810 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.1013180316 |
|
|
Feb 09 02:39:03 PM UTC 25 |
Feb 09 02:39:23 PM UTC 25 |
308476119 ps |
| T811 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.1547441883 |
|
|
Feb 09 02:39:19 PM UTC 25 |
Feb 09 02:39:23 PM UTC 25 |
36024380 ps |
| T812 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.2934048257 |
|
|
Feb 09 02:39:24 PM UTC 25 |
Feb 09 02:39:27 PM UTC 25 |
62668602 ps |
| T813 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.2026843376 |
|
|
Feb 09 02:39:06 PM UTC 25 |
Feb 09 02:39:27 PM UTC 25 |
1522737121 ps |
| T814 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.3191947338 |
|
|
Feb 09 02:39:23 PM UTC 25 |
Feb 09 02:39:28 PM UTC 25 |
61356142 ps |
| T815 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.3619122752 |
|
|
Feb 09 02:39:23 PM UTC 25 |
Feb 09 02:39:31 PM UTC 25 |
200952499 ps |
| T816 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.2122894960 |
|
|
Feb 09 02:38:40 PM UTC 25 |
Feb 09 02:39:34 PM UTC 25 |
482006444 ps |
| T817 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2166777250 |
|
|
Feb 09 02:39:28 PM UTC 25 |
Feb 09 02:39:37 PM UTC 25 |
284594654 ps |
| T818 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.3453144185 |
|
|
Feb 09 02:39:36 PM UTC 25 |
Feb 09 02:39:38 PM UTC 25 |
19888493 ps |
| T819 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.2948144984 |
|
|
Feb 09 02:39:28 PM UTC 25 |
Feb 09 02:39:39 PM UTC 25 |
357571141 ps |
| T820 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.2673662013 |
|
|
Feb 09 02:39:24 PM UTC 25 |
Feb 09 02:39:40 PM UTC 25 |
346290114 ps |
| T821 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.1667849041 |
|
|
Feb 09 02:39:38 PM UTC 25 |
Feb 09 02:39:44 PM UTC 25 |
292836876 ps |
| T822 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.2217628606 |
|
|
Feb 09 02:37:32 PM UTC 25 |
Feb 09 02:39:46 PM UTC 25 |
4738276401 ps |
| T823 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.3068497088 |
|
|
Feb 09 02:39:42 PM UTC 25 |
Feb 09 02:39:47 PM UTC 25 |
48579487 ps |
| T824 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.4129309477 |
|
|
Feb 09 02:39:20 PM UTC 25 |
Feb 09 02:39:53 PM UTC 25 |
953328799 ps |
| T825 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.966293689 |
|
|
Feb 09 02:34:58 PM UTC 25 |
Feb 09 02:39:53 PM UTC 25 |
60648374573 ps |
| T826 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.748997403 |
|
|
Feb 09 02:39:24 PM UTC 25 |
Feb 09 02:39:53 PM UTC 25 |
1908747472 ps |
| T827 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.93209451 |
|
|
Feb 09 02:39:47 PM UTC 25 |
Feb 09 02:39:54 PM UTC 25 |
186526624 ps |
| T828 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.689786845 |
|
|
Feb 09 02:39:01 PM UTC 25 |
Feb 09 02:39:55 PM UTC 25 |
1386003762 ps |
| T829 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.3527251527 |
|
|
Feb 09 02:39:41 PM UTC 25 |
Feb 09 02:39:55 PM UTC 25 |
272937382 ps |
| T830 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.1827950761 |
|
|
Feb 09 02:39:56 PM UTC 25 |
Feb 09 02:39:58 PM UTC 25 |
11495518 ps |
| T831 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.3304132249 |
|
|
Feb 09 02:39:55 PM UTC 25 |
Feb 09 02:39:58 PM UTC 25 |
25278082 ps |
| T832 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.3177732329 |
|
|
Feb 09 02:39:44 PM UTC 25 |
Feb 09 02:39:59 PM UTC 25 |
456115335 ps |
| T833 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.2033315463 |
|
|
Feb 09 02:39:44 PM UTC 25 |
Feb 09 02:39:59 PM UTC 25 |
4682434201 ps |
| T83 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.4073914564 |
|
|
Feb 09 02:39:56 PM UTC 25 |
Feb 09 02:40:01 PM UTC 25 |
206697606 ps |
| T834 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.2811167924 |
|
|
Feb 09 02:39:48 PM UTC 25 |
Feb 09 02:40:02 PM UTC 25 |
835893666 ps |
| T835 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.1327495202 |
|
|
Feb 09 02:40:00 PM UTC 25 |
Feb 09 02:40:04 PM UTC 25 |
75174768 ps |
| T836 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.2715494460 |
|
|
Feb 09 02:40:00 PM UTC 25 |
Feb 09 02:40:05 PM UTC 25 |
45425321 ps |
| T837 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.2542118410 |
|
|
Feb 09 02:39:54 PM UTC 25 |
Feb 09 02:40:05 PM UTC 25 |
179220142 ps |
| T838 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1972833498 |
|
|
Feb 09 02:39:39 PM UTC 25 |
Feb 09 02:40:05 PM UTC 25 |
854403886 ps |
| T839 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.1639427356 |
|
|
Feb 09 02:40:03 PM UTC 25 |
Feb 09 02:40:07 PM UTC 25 |
126475002 ps |
| T840 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.3303307717 |
|
|
Feb 09 02:37:03 PM UTC 25 |
Feb 09 02:40:08 PM UTC 25 |
17262850568 ps |
| T841 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.1200870233 |
|
|
Feb 09 02:40:06 PM UTC 25 |
Feb 09 02:40:09 PM UTC 25 |
57617483 ps |
| T842 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.728545383 |
|
|
Feb 09 02:39:51 PM UTC 25 |
Feb 09 02:40:12 PM UTC 25 |
3311171883 ps |
| T91 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2201195817 |
|
|
Feb 09 02:40:10 PM UTC 25 |
Feb 09 02:40:12 PM UTC 25 |
14127951 ps |
| T84 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.631723612 |
|
|
Feb 09 02:40:08 PM UTC 25 |
Feb 09 02:40:13 PM UTC 25 |
63190266 ps |
| T843 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.2395580829 |
|
|
Feb 09 02:40:03 PM UTC 25 |
Feb 09 02:40:16 PM UTC 25 |
484736322 ps |
| T844 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.430729210 |
|
|
Feb 09 02:40:13 PM UTC 25 |
Feb 09 02:40:18 PM UTC 25 |
386424386 ps |
| T845 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.1312508064 |
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Feb 09 02:40:03 PM UTC 25 |
Feb 09 02:40:19 PM UTC 25 |
269932796 ps |