| T846 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.3388489936 |
|
|
Feb 09 02:40:05 PM UTC 25 |
Feb 09 02:40:21 PM UTC 25 |
2414389961 ps |
| T847 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.2807580142 |
|
|
Feb 09 02:40:00 PM UTC 25 |
Feb 09 02:40:23 PM UTC 25 |
357980552 ps |
| T848 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.990004607 |
|
|
Feb 09 02:40:04 PM UTC 25 |
Feb 09 02:40:24 PM UTC 25 |
1958354686 ps |
| T849 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.3967188524 |
|
|
Feb 09 02:40:13 PM UTC 25 |
Feb 09 02:40:26 PM UTC 25 |
279537820 ps |
| T850 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.2926371218 |
|
|
Feb 09 02:40:18 PM UTC 25 |
Feb 09 02:40:28 PM UTC 25 |
716681128 ps |
| T851 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_errors.1181140049 |
|
|
Feb 09 02:40:14 PM UTC 25 |
Feb 09 02:40:29 PM UTC 25 |
373847349 ps |
| T85 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.1300036563 |
|
|
Feb 09 02:40:29 PM UTC 25 |
Feb 09 02:40:31 PM UTC 25 |
49610575 ps |
| T852 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.939795520 |
|
|
Feb 09 02:40:17 PM UTC 25 |
Feb 09 02:40:32 PM UTC 25 |
240652578 ps |
| T151 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.967218855 |
|
|
Feb 09 02:32:29 PM UTC 25 |
Feb 09 02:40:34 PM UTC 25 |
71786944797 ps |
| T853 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.517567526 |
|
|
Feb 09 02:40:21 PM UTC 25 |
Feb 09 02:40:34 PM UTC 25 |
348816653 ps |
| T854 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.579761798 |
|
|
Feb 09 02:40:32 PM UTC 25 |
Feb 09 02:40:35 PM UTC 25 |
120618203 ps |
| T855 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.3891969164 |
|
|
Feb 09 02:40:20 PM UTC 25 |
Feb 09 02:40:37 PM UTC 25 |
419260726 ps |
| T856 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.347817509 |
|
|
Feb 09 02:40:35 PM UTC 25 |
Feb 09 02:40:39 PM UTC 25 |
104837904 ps |
| T857 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.2815048638 |
|
|
Feb 09 02:40:30 PM UTC 25 |
Feb 09 02:40:40 PM UTC 25 |
473222615 ps |
| T111 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.289863252 |
|
|
Feb 09 02:33:48 PM UTC 25 |
Feb 09 02:40:42 PM UTC 25 |
11192852794 ps |
| T179 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.4073403121 |
|
|
Feb 09 02:40:25 PM UTC 25 |
Feb 09 02:40:48 PM UTC 25 |
1705533174 ps |
| T180 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.1509560260 |
|
|
Feb 09 02:40:40 PM UTC 25 |
Feb 09 02:40:50 PM UTC 25 |
508028907 ps |
| T181 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.1837200721 |
|
|
Feb 09 02:39:10 PM UTC 25 |
Feb 09 02:40:51 PM UTC 25 |
7395623142 ps |
| T182 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.3145273442 |
|
|
Feb 09 02:40:35 PM UTC 25 |
Feb 09 02:40:52 PM UTC 25 |
815709581 ps |
| T183 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.2565352318 |
|
|
Feb 09 02:40:38 PM UTC 25 |
Feb 09 02:40:52 PM UTC 25 |
283299130 ps |
| T184 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_errors.3617873324 |
|
|
Feb 09 02:40:36 PM UTC 25 |
Feb 09 02:40:54 PM UTC 25 |
251098250 ps |
| T185 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.4260391671 |
|
|
Feb 09 02:40:52 PM UTC 25 |
Feb 09 02:40:55 PM UTC 25 |
120742364 ps |
| T186 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.308624417 |
|
|
Feb 09 02:40:41 PM UTC 25 |
Feb 09 02:40:55 PM UTC 25 |
425613834 ps |
| T187 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.4139375685 |
|
|
Feb 09 02:40:55 PM UTC 25 |
Feb 09 02:40:57 PM UTC 25 |
15201210 ps |
| T858 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.1245514748 |
|
|
Feb 09 02:40:43 PM UTC 25 |
Feb 09 02:41:01 PM UTC 25 |
326680722 ps |
| T859 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.2124368124 |
|
|
Feb 09 02:39:59 PM UTC 25 |
Feb 09 02:41:02 PM UTC 25 |
459331072 ps |
| T860 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.929234033 |
|
|
Feb 09 02:40:58 PM UTC 25 |
Feb 09 02:41:03 PM UTC 25 |
166483901 ps |
| T861 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.856007416 |
|
|
Feb 09 02:40:49 PM UTC 25 |
Feb 09 02:41:03 PM UTC 25 |
320142532 ps |
| T105 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.1243170154 |
|
|
Feb 09 02:37:18 PM UTC 25 |
Feb 09 02:41:07 PM UTC 25 |
7525502562 ps |
| T862 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.3832000097 |
|
|
Feb 09 02:40:54 PM UTC 25 |
Feb 09 02:41:07 PM UTC 25 |
228686436 ps |
| T863 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.3995243120 |
|
|
Feb 09 02:40:10 PM UTC 25 |
Feb 09 02:41:07 PM UTC 25 |
1917140891 ps |
| T864 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.3250109329 |
|
|
Feb 09 02:40:32 PM UTC 25 |
Feb 09 02:41:08 PM UTC 25 |
400431657 ps |
| T865 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.2397927849 |
|
|
Feb 09 02:40:56 PM UTC 25 |
Feb 09 02:41:11 PM UTC 25 |
250654048 ps |
| T866 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.1437186330 |
|
|
Feb 09 02:38:03 PM UTC 25 |
Feb 09 02:41:12 PM UTC 25 |
40567101466 ps |
| T112 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2990077324 |
|
|
Feb 09 02:34:29 PM UTC 25 |
Feb 09 02:41:13 PM UTC 25 |
19545362732 ps |
| T867 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.849796777 |
|
|
Feb 09 02:41:03 PM UTC 25 |
Feb 09 02:41:13 PM UTC 25 |
267054366 ps |
| T868 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.4225738340 |
|
|
Feb 09 02:41:12 PM UTC 25 |
Feb 09 02:41:14 PM UTC 25 |
19080528 ps |
| T869 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.2359901129 |
|
|
Feb 09 02:41:05 PM UTC 25 |
Feb 09 02:41:14 PM UTC 25 |
570106003 ps |
| T870 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_errors.2700538879 |
|
|
Feb 09 02:41:02 PM UTC 25 |
Feb 09 02:41:16 PM UTC 25 |
1360739196 ps |
| T871 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.4196844031 |
|
|
Feb 09 02:41:05 PM UTC 25 |
Feb 09 02:41:19 PM UTC 25 |
1169425689 ps |
| T872 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.219155313 |
|
|
Feb 09 02:41:08 PM UTC 25 |
Feb 09 02:41:21 PM UTC 25 |
664207503 ps |
| T873 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.1181004968 |
|
|
Feb 09 02:41:08 PM UTC 25 |
Feb 09 02:41:28 PM UTC 25 |
2676600717 ps |
| T874 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.2851163431 |
|
|
Feb 09 02:40:56 PM UTC 25 |
Feb 09 02:41:28 PM UTC 25 |
202535429 ps |
| T875 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.420062744 |
|
|
Feb 09 02:38:49 PM UTC 25 |
Feb 09 02:41:30 PM UTC 25 |
14631137327 ps |
| T160 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.87732625 |
|
|
Feb 09 02:33:37 PM UTC 25 |
Feb 09 02:41:31 PM UTC 25 |
33440010725 ps |
| T152 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.475195841 |
|
|
Feb 09 02:37:33 PM UTC 25 |
Feb 09 02:41:57 PM UTC 25 |
132207930042 ps |
| T190 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.681969097 |
|
|
Feb 09 02:34:58 PM UTC 25 |
Feb 09 02:42:06 PM UTC 25 |
184611236827 ps |
| T191 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.2501581889 |
|
|
Feb 09 02:30:49 PM UTC 25 |
Feb 09 02:42:13 PM UTC 25 |
21393206320 ps |
| T192 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.3229404490 |
|
|
Feb 09 02:37:47 PM UTC 25 |
Feb 09 02:42:13 PM UTC 25 |
33963113112 ps |
| T193 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.1912630853 |
|
|
Feb 09 02:38:17 PM UTC 25 |
Feb 09 02:42:32 PM UTC 25 |
26436745162 ps |
| T194 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.4013299759 |
|
|
Feb 09 02:40:50 PM UTC 25 |
Feb 09 02:43:07 PM UTC 25 |
15138055234 ps |
| T106 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1611318276 |
|
|
Feb 09 02:29:13 PM UTC 25 |
Feb 09 02:43:38 PM UTC 25 |
147479465453 ps |
| T195 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.4215416980 |
|
|
Feb 09 02:38:18 PM UTC 25 |
Feb 09 02:43:39 PM UTC 25 |
5763416503 ps |
| T196 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.2109669858 |
|
|
Feb 09 02:39:29 PM UTC 25 |
Feb 09 02:43:42 PM UTC 25 |
6441582274 ps |
| T197 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2465997697 |
|
|
Feb 09 02:37:18 PM UTC 25 |
Feb 09 02:43:43 PM UTC 25 |
85401684372 ps |
| T116 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2273912042 |
|
|
Feb 09 02:32:52 PM UTC 25 |
Feb 09 02:44:55 PM UTC 25 |
196273916508 ps |
| T876 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.3176352023 |
|
|
Feb 09 02:39:55 PM UTC 25 |
Feb 09 02:45:12 PM UTC 25 |
12280299963 ps |
| T877 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.1144809872 |
|
|
Feb 09 02:40:25 PM UTC 25 |
Feb 09 02:45:24 PM UTC 25 |
71938347430 ps |
| T173 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2628290374 |
|
|
Feb 09 02:31:27 PM UTC 25 |
Feb 09 02:45:32 PM UTC 25 |
42733199082 ps |
| T878 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.3226141107 |
|
|
Feb 09 02:38:33 PM UTC 25 |
Feb 09 02:45:55 PM UTC 25 |
10472400808 ps |
| T234 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.651748660 |
|
|
Feb 09 02:34:45 PM UTC 25 |
Feb 09 02:47:06 PM UTC 25 |
20572677404 ps |
| T879 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.2503603256 |
|
|
Feb 09 02:40:06 PM UTC 25 |
Feb 09 02:47:39 PM UTC 25 |
18560999685 ps |
| T161 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3987262429 |
|
|
Feb 09 02:36:46 PM UTC 25 |
Feb 09 02:48:35 PM UTC 25 |
202366777099 ps |
| T880 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2722952388 |
|
|
Feb 09 02:40:27 PM UTC 25 |
Feb 09 02:48:36 PM UTC 25 |
12187121033 ps |
| T61 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2066874741 |
|
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Feb 09 02:30:32 PM UTC 25 |
Feb 09 02:48:52 PM UTC 25 |
35903817676 ps |
| T881 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.1376706422 |
|
|
Feb 09 02:41:08 PM UTC 25 |
Feb 09 02:49:00 PM UTC 25 |
68123963987 ps |
| T882 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.50182912 |
|
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Feb 09 02:28:22 PM UTC 25 |
Feb 09 02:50:06 PM UTC 25 |
35797033523 ps |
| T174 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3179490185 |
|
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Feb 09 02:27:18 PM UTC 25 |
Feb 09 02:50:10 PM UTC 25 |
136947797260 ps |
| T883 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2915929920 |
|
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Feb 09 02:40:52 PM UTC 25 |
Feb 09 02:51:07 PM UTC 25 |
105772840260 ps |
| T113 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2916057297 |
|
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Feb 09 02:39:15 PM UTC 25 |
Feb 09 02:54:29 PM UTC 25 |
214115779348 ps |
| T125 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.59966024 |
|
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Feb 09 02:33:20 PM UTC 25 |
Feb 09 02:54:50 PM UTC 25 |
208029013099 ps |
| T175 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.2505994335 |
|
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Feb 09 02:39:31 PM UTC 25 |
Feb 09 02:58:26 PM UTC 25 |
276623003868 ps |
| T188 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.1727114336 |
|
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Feb 09 02:41:08 PM UTC 25 |
Feb 09 02:58:27 PM UTC 25 |
61266083076 ps |
| T884 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3968092438 |
|
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Feb 09 02:38:03 PM UTC 25 |
Feb 09 03:02:22 PM UTC 25 |
138200528600 ps |
| T189 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.3035484526 |
|
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Feb 09 02:35:36 PM UTC 25 |
Feb 09 03:06:35 PM UTC 25 |
26178971792 ps |
| T885 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1292364309 |
|
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Feb 09 02:37:07 PM UTC 25 |
Feb 09 03:06:57 PM UTC 25 |
83257085065 ps |
| T176 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.193368969 |
|
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Feb 09 02:40:06 PM UTC 25 |
Feb 09 03:50:49 PM UTC 25 |
211777302372 ps |
| T122 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3123460762 |
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Feb 09 02:41:13 PM UTC 25 |
Feb 09 02:41:16 PM UTC 25 |
2039377928 ps |
| T118 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3127213360 |
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Feb 09 02:41:14 PM UTC 25 |
Feb 09 02:41:18 PM UTC 25 |
155673560 ps |
| T123 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2423541613 |
|
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Feb 09 02:41:15 PM UTC 25 |
Feb 09 02:41:19 PM UTC 25 |
27264034 ps |
| T149 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.91459319 |
|
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Feb 09 02:41:14 PM UTC 25 |
Feb 09 02:41:19 PM UTC 25 |
415711477 ps |
| T177 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1317149874 |
|
|
Feb 09 02:41:17 PM UTC 25 |
Feb 09 02:41:20 PM UTC 25 |
78606330 ps |
| T886 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4242842757 |
|
|
Feb 09 02:41:17 PM UTC 25 |
Feb 09 02:41:20 PM UTC 25 |
234868108 ps |
| T119 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.552039335 |
|
|
Feb 09 02:41:20 PM UTC 25 |
Feb 09 02:41:23 PM UTC 25 |
16276953 ps |
| T145 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4134758250 |
|
|
Feb 09 02:41:20 PM UTC 25 |
Feb 09 02:41:23 PM UTC 25 |
21424245 ps |
| T120 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.713145918 |
|
|
Feb 09 02:41:21 PM UTC 25 |
Feb 09 02:41:24 PM UTC 25 |
47623637 ps |
| T887 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3408699689 |
|
|
Feb 09 02:41:21 PM UTC 25 |
Feb 09 02:41:24 PM UTC 25 |
165544971 ps |
| T224 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.95591656 |
|
|
Feb 09 02:41:22 PM UTC 25 |
Feb 09 02:41:25 PM UTC 25 |
18459245 ps |
| T108 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2291440938 |
|
|
Feb 09 02:41:20 PM UTC 25 |
Feb 09 02:41:25 PM UTC 25 |
131355296 ps |
| T178 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2932971983 |
|
|
Feb 09 02:41:23 PM UTC 25 |
Feb 09 02:41:26 PM UTC 25 |
31435509 ps |
| T109 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2912395677 |
|
|
Feb 09 02:41:19 PM UTC 25 |
Feb 09 02:41:26 PM UTC 25 |
219129681 ps |
| T146 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.4154529233 |
|
|
Feb 09 02:41:23 PM UTC 25 |
Feb 09 02:41:28 PM UTC 25 |
1415316197 ps |
| T888 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4155115917 |
|
|
Feb 09 02:41:24 PM UTC 25 |
Feb 09 02:41:29 PM UTC 25 |
53810759 ps |
| T144 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.894510679 |
|
|
Feb 09 02:41:27 PM UTC 25 |
Feb 09 02:41:30 PM UTC 25 |
21639878 ps |
| T889 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.39817756 |
|
|
Feb 09 02:41:28 PM UTC 25 |
Feb 09 02:41:30 PM UTC 25 |
84519354 ps |
| T213 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4183713872 |
|
|
Feb 09 02:41:29 PM UTC 25 |
Feb 09 02:41:32 PM UTC 25 |
18259217 ps |
| T214 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.657890111 |
|
|
Feb 09 02:41:29 PM UTC 25 |
Feb 09 02:41:32 PM UTC 25 |
31319995 ps |
| T198 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.361189357 |
|
|
Feb 09 02:41:28 PM UTC 25 |
Feb 09 02:41:32 PM UTC 25 |
164390473 ps |
| T110 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1079826958 |
|
|
Feb 09 02:41:29 PM UTC 25 |
Feb 09 02:41:35 PM UTC 25 |
176246021 ps |
| T114 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2557062914 |
|
|
Feb 09 02:41:53 PM UTC 25 |
Feb 09 02:41:57 PM UTC 25 |
55108677 ps |
| T225 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2010687800 |
|
|
Feb 09 02:41:32 PM UTC 25 |
Feb 09 02:41:35 PM UTC 25 |
93028583 ps |
| T890 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.4259568755 |
|
|
Feb 09 02:41:32 PM UTC 25 |
Feb 09 02:41:35 PM UTC 25 |
139845181 ps |
| T199 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2684625164 |
|
|
Feb 09 02:41:32 PM UTC 25 |
Feb 09 02:41:35 PM UTC 25 |
27371324 ps |
| T115 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.790728052 |
|
|
Feb 09 02:41:29 PM UTC 25 |
Feb 09 02:41:35 PM UTC 25 |
434002198 ps |
| T215 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3602828605 |
|
|
Feb 09 02:41:32 PM UTC 25 |
Feb 09 02:41:36 PM UTC 25 |
59643838 ps |
| T147 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.409371571 |
|
|
Feb 09 02:41:26 PM UTC 25 |
Feb 09 02:41:36 PM UTC 25 |
513072021 ps |
| T891 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3732195527 |
|
|
Feb 09 02:41:33 PM UTC 25 |
Feb 09 02:41:37 PM UTC 25 |
399771762 ps |
| T892 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2520193630 |
|
|
Feb 09 02:41:33 PM UTC 25 |
Feb 09 02:41:38 PM UTC 25 |
434814262 ps |
| T226 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.3537550424 |
|
|
Feb 09 02:41:36 PM UTC 25 |
Feb 09 02:41:39 PM UTC 25 |
277321306 ps |
| T893 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4037105321 |
|
|
Feb 09 02:41:14 PM UTC 25 |
Feb 09 02:41:40 PM UTC 25 |
18722811589 ps |
| T216 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.52157737 |
|
|
Feb 09 02:41:37 PM UTC 25 |
Feb 09 02:41:40 PM UTC 25 |
48752138 ps |
| T117 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.267787707 |
|
|
Feb 09 02:41:37 PM UTC 25 |
Feb 09 02:41:40 PM UTC 25 |
236283064 ps |
| T894 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.853716899 |
|
|
Feb 09 02:41:37 PM UTC 25 |
Feb 09 02:41:40 PM UTC 25 |
156546104 ps |
| T895 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1716621605 |
|
|
Feb 09 02:41:38 PM UTC 25 |
Feb 09 02:41:40 PM UTC 25 |
124878217 ps |
| T896 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2277879446 |
|
|
Feb 09 02:41:25 PM UTC 25 |
Feb 09 02:41:41 PM UTC 25 |
974275649 ps |
| T897 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1247311742 |
|
|
Feb 09 02:41:33 PM UTC 25 |
Feb 09 02:41:41 PM UTC 25 |
417734536 ps |
| T898 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.832023622 |
|
|
Feb 09 02:41:39 PM UTC 25 |
Feb 09 02:41:42 PM UTC 25 |
67110489 ps |
| T899 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1186997818 |
|
|
Feb 09 02:41:40 PM UTC 25 |
Feb 09 02:41:43 PM UTC 25 |
33638379 ps |
| T900 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3994528327 |
|
|
Feb 09 02:41:36 PM UTC 25 |
Feb 09 02:41:43 PM UTC 25 |
416933960 ps |
| T217 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.705077678 |
|
|
Feb 09 02:41:53 PM UTC 25 |
Feb 09 02:41:55 PM UTC 25 |
59661547 ps |
| T130 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.4140416319 |
|
|
Feb 09 02:41:40 PM UTC 25 |
Feb 09 02:41:43 PM UTC 25 |
37968707 ps |
| T901 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2186589331 |
|
|
Feb 09 02:41:37 PM UTC 25 |
Feb 09 02:41:44 PM UTC 25 |
287680987 ps |
| T227 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.555889473 |
|
|
Feb 09 02:41:40 PM UTC 25 |
Feb 09 02:41:44 PM UTC 25 |
37351760 ps |
| T218 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.215734453 |
|
|
Feb 09 02:41:53 PM UTC 25 |
Feb 09 02:41:55 PM UTC 25 |
43406347 ps |
| T136 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.942529395 |
|
|
Feb 09 02:41:37 PM UTC 25 |
Feb 09 02:41:45 PM UTC 25 |
856188284 ps |
| T902 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3387200369 |
|
|
Feb 09 02:41:41 PM UTC 25 |
Feb 09 02:41:45 PM UTC 25 |
101321520 ps |
| T903 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3518451838 |
|
|
Feb 09 02:41:41 PM UTC 25 |
Feb 09 02:41:46 PM UTC 25 |
1077643087 ps |
| T228 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.4030094934 |
|
|
Feb 09 02:41:42 PM UTC 25 |
Feb 09 02:41:46 PM UTC 25 |
213582128 ps |
| T904 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.4115682983 |
|
|
Feb 09 02:41:44 PM UTC 25 |
Feb 09 02:41:46 PM UTC 25 |
67424078 ps |
| T905 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4121173999 |
|
|
Feb 09 02:41:43 PM UTC 25 |
Feb 09 02:41:47 PM UTC 25 |
67778502 ps |
| T229 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3510342885 |
|
|
Feb 09 02:41:45 PM UTC 25 |
Feb 09 02:41:48 PM UTC 25 |
25590507 ps |
| T906 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.502352318 |
|
|
Feb 09 02:41:45 PM UTC 25 |
Feb 09 02:41:48 PM UTC 25 |
62763895 ps |
| T142 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2648676347 |
|
|
Feb 09 02:41:45 PM UTC 25 |
Feb 09 02:41:49 PM UTC 25 |
45068531 ps |
| T129 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.738433374 |
|
|
Feb 09 02:41:45 PM UTC 25 |
Feb 09 02:41:49 PM UTC 25 |
89222371 ps |
| T907 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.843289545 |
|
|
Feb 09 02:41:46 PM UTC 25 |
Feb 09 02:41:49 PM UTC 25 |
20219593 ps |
| T908 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2398058943 |
|
|
Feb 09 02:41:46 PM UTC 25 |
Feb 09 02:41:50 PM UTC 25 |
97494837 ps |
| T909 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3023017562 |
|
|
Feb 09 02:41:48 PM UTC 25 |
Feb 09 02:41:51 PM UTC 25 |
64129586 ps |
| T230 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2913136789 |
|
|
Feb 09 02:41:48 PM UTC 25 |
Feb 09 02:41:51 PM UTC 25 |
65059296 ps |
| T910 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.367366645 |
|
|
Feb 09 02:41:50 PM UTC 25 |
Feb 09 02:41:52 PM UTC 25 |
20693997 ps |
| T911 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2495597174 |
|
|
Feb 09 02:41:50 PM UTC 25 |
Feb 09 02:41:53 PM UTC 25 |
74024387 ps |
| T912 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3092545567 |
|
|
Feb 09 02:41:53 PM UTC 25 |
Feb 09 02:41:55 PM UTC 25 |
83838563 ps |
| T913 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.455302279 |
|
|
Feb 09 02:41:48 PM UTC 25 |
Feb 09 02:41:55 PM UTC 25 |
2216600440 ps |
| T914 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3135271615 |
|
|
Feb 09 02:41:41 PM UTC 25 |
Feb 09 02:41:57 PM UTC 25 |
2351753215 ps |
| T915 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1186017466 |
|
|
Feb 09 02:41:50 PM UTC 25 |
Feb 09 02:41:58 PM UTC 25 |
1610645136 ps |
| T133 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.4246661 |
|
|
Feb 09 02:41:53 PM UTC 25 |
Feb 09 02:41:58 PM UTC 25 |
355845589 ps |
| T219 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4223726578 |
|
|
Feb 09 02:41:55 PM UTC 25 |
Feb 09 02:41:58 PM UTC 25 |
58708657 ps |
| T916 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3989537124 |
|
|
Feb 09 02:41:53 PM UTC 25 |
Feb 09 02:41:58 PM UTC 25 |
178711848 ps |
| T917 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1774610149 |
|
|
Feb 09 02:41:55 PM UTC 25 |
Feb 09 02:41:58 PM UTC 25 |
512789584 ps |
| T918 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1295687166 |
|
|
Feb 09 02:41:42 PM UTC 25 |
Feb 09 02:41:59 PM UTC 25 |
9367968793 ps |
| T919 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.435626159 |
|
|
Feb 09 02:41:58 PM UTC 25 |
Feb 09 02:42:01 PM UTC 25 |
30706459 ps |
| T920 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1821520414 |
|
|
Feb 09 02:41:58 PM UTC 25 |
Feb 09 02:42:01 PM UTC 25 |
93477539 ps |
| T921 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3054742172 |
|
|
Feb 09 02:41:58 PM UTC 25 |
Feb 09 02:42:01 PM UTC 25 |
71012115 ps |
| T922 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.332901806 |
|
|
Feb 09 02:41:58 PM UTC 25 |
Feb 09 02:42:01 PM UTC 25 |
43163252 ps |
| T923 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3229215979 |
|
|
Feb 09 02:41:58 PM UTC 25 |
Feb 09 02:42:03 PM UTC 25 |
1094494004 ps |
| T924 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.686200381 |
|
|
Feb 09 02:42:01 PM UTC 25 |
Feb 09 02:42:03 PM UTC 25 |
24042026 ps |
| T925 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.4039602828 |
|
|
Feb 09 02:42:01 PM UTC 25 |
Feb 09 02:42:03 PM UTC 25 |
305732016 ps |
| T926 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3844807727 |
|
|
Feb 09 02:42:00 PM UTC 25 |
Feb 09 02:42:03 PM UTC 25 |
58518243 ps |
| T927 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.4127818610 |
|
|
Feb 09 02:42:01 PM UTC 25 |
Feb 09 02:42:04 PM UTC 25 |
180641854 ps |
| T928 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1000770195 |
|
|
Feb 09 02:42:00 PM UTC 25 |
Feb 09 02:42:04 PM UTC 25 |
39578687 ps |
| T929 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.825213055 |
|
|
Feb 09 02:42:01 PM UTC 25 |
Feb 09 02:42:05 PM UTC 25 |
127690251 ps |
| T930 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2906476902 |
|
|
Feb 09 02:42:04 PM UTC 25 |
Feb 09 02:42:06 PM UTC 25 |
60420865 ps |
| T931 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3665943402 |
|
|
Feb 09 02:42:04 PM UTC 25 |
Feb 09 02:42:07 PM UTC 25 |
480898999 ps |
| T139 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3792709802 |
|
|
Feb 09 02:42:01 PM UTC 25 |
Feb 09 02:42:07 PM UTC 25 |
354977437 ps |
| T932 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4027741852 |
|
|
Feb 09 02:41:50 PM UTC 25 |
Feb 09 02:42:08 PM UTC 25 |
622547190 ps |
| T933 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2768981057 |
|
|
Feb 09 02:42:06 PM UTC 25 |
Feb 09 02:42:09 PM UTC 25 |
20962509 ps |
| T934 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2369191035 |
|
|
Feb 09 02:42:06 PM UTC 25 |
Feb 09 02:42:09 PM UTC 25 |
51689850 ps |
| T935 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3912981268 |
|
|
Feb 09 02:42:06 PM UTC 25 |
Feb 09 02:42:09 PM UTC 25 |
43149924 ps |
| T936 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2867789788 |
|
|
Feb 09 02:42:06 PM UTC 25 |
Feb 09 02:42:10 PM UTC 25 |
48996014 ps |
| T937 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1965430549 |
|
|
Feb 09 02:42:04 PM UTC 25 |
Feb 09 02:42:10 PM UTC 25 |
258262412 ps |
| T938 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.401949857 |
|
|
Feb 09 02:42:06 PM UTC 25 |
Feb 09 02:42:10 PM UTC 25 |
95172140 ps |
| T137 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.756284413 |
|
|
Feb 09 02:42:06 PM UTC 25 |
Feb 09 02:42:10 PM UTC 25 |
632232189 ps |
| T939 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1265417165 |
|
|
Feb 09 02:42:06 PM UTC 25 |
Feb 09 02:42:11 PM UTC 25 |
275270458 ps |
| T940 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.157076514 |
|
|
Feb 09 02:42:10 PM UTC 25 |
Feb 09 02:42:13 PM UTC 25 |
65991210 ps |
| T941 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2410097471 |
|
|
Feb 09 02:42:10 PM UTC 25 |
Feb 09 02:42:13 PM UTC 25 |
27034190 ps |
| T942 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3681653784 |
|
|
Feb 09 02:42:04 PM UTC 25 |
Feb 09 02:42:13 PM UTC 25 |
332491494 ps |
| T943 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.416131311 |
|
|
Feb 09 02:42:10 PM UTC 25 |
Feb 09 02:42:14 PM UTC 25 |
48086167 ps |
| T944 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2142565056 |
|
|
Feb 09 02:42:11 PM UTC 25 |
Feb 09 02:42:14 PM UTC 25 |
251543963 ps |
| T945 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1537792915 |
|
|
Feb 09 02:42:11 PM UTC 25 |
Feb 09 02:42:14 PM UTC 25 |
207120894 ps |
| T946 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2628671883 |
|
|
Feb 09 02:42:13 PM UTC 25 |
Feb 09 02:42:16 PM UTC 25 |
12997077 ps |
| T947 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3881920488 |
|
|
Feb 09 02:42:13 PM UTC 25 |
Feb 09 02:42:16 PM UTC 25 |
24900466 ps |
| T948 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2654476833 |
|
|
Feb 09 02:42:04 PM UTC 25 |
Feb 09 02:42:16 PM UTC 25 |
3882680989 ps |
| T949 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2315630400 |
|
|
Feb 09 02:42:13 PM UTC 25 |
Feb 09 02:42:16 PM UTC 25 |
102944928 ps |
| T140 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1851892646 |
|
|
Feb 09 02:42:11 PM UTC 25 |
Feb 09 02:42:16 PM UTC 25 |
108791370 ps |
| T950 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3079506488 |
|
|
Feb 09 02:42:11 PM UTC 25 |
Feb 09 02:42:16 PM UTC 25 |
157931433 ps |
| T951 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.999821324 |
|
|
Feb 09 02:42:10 PM UTC 25 |
Feb 09 02:42:17 PM UTC 25 |
145933734 ps |
| T952 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1915356332 |
|
|
Feb 09 02:42:13 PM UTC 25 |
Feb 09 02:42:17 PM UTC 25 |
290368016 ps |
| T953 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.4237133734 |
|
|
Feb 09 02:42:13 PM UTC 25 |
Feb 09 02:42:18 PM UTC 25 |
280555532 ps |
| T954 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1835294 |
|
|
Feb 09 02:42:16 PM UTC 25 |
Feb 09 02:42:19 PM UTC 25 |
21190469 ps |
| T955 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.77956670 |
|
|
Feb 09 02:42:16 PM UTC 25 |
Feb 09 02:42:19 PM UTC 25 |
93507282 ps |
| T956 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2476716599 |
|
|
Feb 09 02:42:16 PM UTC 25 |
Feb 09 02:42:20 PM UTC 25 |
338480491 ps |
| T957 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1387618130 |
|
|
Feb 09 02:42:18 PM UTC 25 |
Feb 09 02:42:21 PM UTC 25 |
29957736 ps |
| T958 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.579788282 |
|
|
Feb 09 02:42:18 PM UTC 25 |
Feb 09 02:42:21 PM UTC 25 |
27976152 ps |
| T959 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4044018730 |
|
|
Feb 09 02:42:18 PM UTC 25 |
Feb 09 02:42:21 PM UTC 25 |
18925491 ps |
| T960 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.496063683 |
|
|
Feb 09 02:42:18 PM UTC 25 |
Feb 09 02:42:21 PM UTC 25 |
57416697 ps |
| T961 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.853557371 |
|
|
Feb 09 02:42:18 PM UTC 25 |
Feb 09 02:42:21 PM UTC 25 |
34140591 ps |
| T127 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1449870524 |
|
|
Feb 09 02:42:16 PM UTC 25 |
Feb 09 02:42:21 PM UTC 25 |
279699488 ps |
| T962 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2251452653 |
|
|
Feb 09 02:42:16 PM UTC 25 |
Feb 09 02:42:22 PM UTC 25 |
99438037 ps |
| T963 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3473093577 |
|
|
Feb 09 02:42:10 PM UTC 25 |
Feb 09 02:42:22 PM UTC 25 |
373005986 ps |
| T964 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3430297885 |
|
|
Feb 09 02:42:18 PM UTC 25 |
Feb 09 02:42:22 PM UTC 25 |
49215366 ps |
| T965 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1694734725 |
|
|
Feb 09 02:42:16 PM UTC 25 |
Feb 09 02:42:23 PM UTC 25 |
855097506 ps |
| T966 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2365289387 |
|
|
Feb 09 02:42:21 PM UTC 25 |
Feb 09 02:42:23 PM UTC 25 |
118560579 ps |
| T967 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1916036299 |
|
|
Feb 09 02:42:10 PM UTC 25 |
Feb 09 02:42:23 PM UTC 25 |
3028988256 ps |
| T968 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3397778403 |
|
|
Feb 09 02:42:21 PM UTC 25 |
Feb 09 02:42:24 PM UTC 25 |
57004737 ps |
| T131 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1661436240 |
|
|
Feb 09 02:42:21 PM UTC 25 |
Feb 09 02:42:24 PM UTC 25 |
174194173 ps |
| T969 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.23049606 |
|
|
Feb 09 02:42:20 PM UTC 25 |
Feb 09 02:42:24 PM UTC 25 |
149806296 ps |
| T970 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3081182859 |
|
|
Feb 09 02:42:22 PM UTC 25 |
Feb 09 02:42:24 PM UTC 25 |
21816267 ps |
| T971 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4112597962 |
|
|
Feb 09 02:42:22 PM UTC 25 |
Feb 09 02:42:25 PM UTC 25 |
17524746 ps |
| T220 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2472258284 |
|
|
Feb 09 02:42:22 PM UTC 25 |
Feb 09 02:42:25 PM UTC 25 |
57288498 ps |
| T972 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3853618248 |
|
|
Feb 09 02:42:18 PM UTC 25 |
Feb 09 02:42:25 PM UTC 25 |
426423856 ps |
| T973 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1220411461 |
|
|
Feb 09 02:42:22 PM UTC 25 |
Feb 09 02:42:25 PM UTC 25 |
39214928 ps |
| T974 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3917137200 |
|
|
Feb 09 02:41:58 PM UTC 25 |
Feb 09 02:42:25 PM UTC 25 |
1439446904 ps |
| T143 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2188664118 |
|
|
Feb 09 02:42:22 PM UTC 25 |
Feb 09 02:42:26 PM UTC 25 |
167836613 ps |
| T975 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2687634860 |
|
|
Feb 09 02:42:24 PM UTC 25 |
Feb 09 02:42:26 PM UTC 25 |
40000021 ps |
| T976 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4004610223 |
|
|
Feb 09 02:42:24 PM UTC 25 |
Feb 09 02:42:26 PM UTC 25 |
103893557 ps |
| T977 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.738406328 |
|
|
Feb 09 02:42:24 PM UTC 25 |
Feb 09 02:42:26 PM UTC 25 |
129124743 ps |
| T978 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1503017307 |
|
|
Feb 09 02:42:24 PM UTC 25 |
Feb 09 02:42:27 PM UTC 25 |
134179337 ps |
| T979 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3217475397 |
|
|
Feb 09 02:42:22 PM UTC 25 |
Feb 09 02:42:27 PM UTC 25 |
74854656 ps |
| T132 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.50259680 |
|
|
Feb 09 02:42:24 PM UTC 25 |
Feb 09 02:42:28 PM UTC 25 |
84013172 ps |
| T980 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3676804849 |
|
|
Feb 09 02:42:25 PM UTC 25 |
Feb 09 02:42:28 PM UTC 25 |
49683425 ps |
| T981 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1294987441 |
|
|
Feb 09 02:42:25 PM UTC 25 |
Feb 09 02:42:28 PM UTC 25 |
16373073 ps |
| T982 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2524090681 |
|
|
Feb 09 02:42:25 PM UTC 25 |
Feb 09 02:42:28 PM UTC 25 |
85002025 ps |
| T983 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2327871762 |
|
|
Feb 09 02:42:24 PM UTC 25 |
Feb 09 02:42:28 PM UTC 25 |
56275214 ps |
| T984 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1075392266 |
|
|
Feb 09 02:42:25 PM UTC 25 |
Feb 09 02:42:29 PM UTC 25 |
46078955 ps |
| T985 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.923801187 |
|
|
Feb 09 02:42:25 PM UTC 25 |
Feb 09 02:42:29 PM UTC 25 |
23644710 ps |
| T986 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.313575237 |
|
|
Feb 09 02:42:25 PM UTC 25 |
Feb 09 02:42:29 PM UTC 25 |
54428741 ps |
| T124 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1193832018 |
|
|
Feb 09 02:42:25 PM UTC 25 |
Feb 09 02:42:29 PM UTC 25 |
45748257 ps |
| T221 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2026634781 |
|
|
Feb 09 02:42:27 PM UTC 25 |
Feb 09 02:42:29 PM UTC 25 |
18217855 ps |
| T987 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2886325352 |
|
|
Feb 09 02:42:27 PM UTC 25 |
Feb 09 02:42:29 PM UTC 25 |
28581148 ps |
| T988 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2084655478 |
|
|
Feb 09 02:42:27 PM UTC 25 |
Feb 09 02:42:29 PM UTC 25 |
43946772 ps |
| T989 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1569780092 |
|
|
Feb 09 02:42:27 PM UTC 25 |
Feb 09 02:42:30 PM UTC 25 |
58628909 ps |
| T138 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1068099966 |
|
|
Feb 09 02:42:27 PM UTC 25 |
Feb 09 02:42:31 PM UTC 25 |
266669269 ps |
| T128 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1869474884 |
|
|
Feb 09 02:42:27 PM UTC 25 |
Feb 09 02:42:31 PM UTC 25 |
108946863 ps |
| T990 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3730858884 |
|
|
Feb 09 02:42:28 PM UTC 25 |
Feb 09 02:42:31 PM UTC 25 |
32735500 ps |
| T121 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1458670756 |
|
|
Feb 09 02:42:28 PM UTC 25 |
Feb 09 02:42:32 PM UTC 25 |
223432591 ps |
| T222 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.944439151 |
|
|
Feb 09 02:42:30 PM UTC 25 |
Feb 09 02:42:32 PM UTC 25 |
14409954 ps |
| T223 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3946918548 |
|
|
Feb 09 02:42:30 PM UTC 25 |
Feb 09 02:42:32 PM UTC 25 |
14765827 ps |
| T991 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.380583864 |
|
|
Feb 09 02:42:28 PM UTC 25 |
Feb 09 02:42:32 PM UTC 25 |
321160730 ps |
| T992 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2632393553 |
|
|
Feb 09 02:42:30 PM UTC 25 |
Feb 09 02:42:32 PM UTC 25 |
30748187 ps |
| T993 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1746388088 |
|
|
Feb 09 02:42:28 PM UTC 25 |
Feb 09 02:42:32 PM UTC 25 |
200947293 ps |
| T994 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3861988945 |
|
|
Feb 09 02:42:30 PM UTC 25 |
Feb 09 02:42:33 PM UTC 25 |
24775006 ps |
| T995 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.202521757 |
|
|
Feb 09 02:42:30 PM UTC 25 |
Feb 09 02:42:33 PM UTC 25 |
75728496 ps |
| T996 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3181262034 |
|
|
Feb 09 02:42:31 PM UTC 25 |
Feb 09 02:42:34 PM UTC 25 |
43469840 ps |
| T997 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3242660153 |
|
|
Feb 09 02:42:31 PM UTC 25 |
Feb 09 02:42:34 PM UTC 25 |
24978018 ps |
| T998 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1360190259 |
|
|
Feb 09 02:42:31 PM UTC 25 |
Feb 09 02:42:34 PM UTC 25 |
11835394 ps |
| T999 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.703875109 |
|
|
Feb 09 02:42:31 PM UTC 25 |
Feb 09 02:42:34 PM UTC 25 |
96626065 ps |
| T1000 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3785159640 |
|
|
Feb 09 02:42:27 PM UTC 25 |
Feb 09 02:42:34 PM UTC 25 |
129673506 ps |
| T1001 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3855691474 |
|
|
Feb 09 02:42:33 PM UTC 25 |
Feb 09 02:42:36 PM UTC 25 |
29061561 ps |
| T1002 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2687185618 |
|
|
Feb 09 02:42:31 PM UTC 25 |
Feb 09 02:42:36 PM UTC 25 |
152586309 ps |
| T1003 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4138942822 |
|
|
Feb 09 02:42:33 PM UTC 25 |
Feb 09 02:42:36 PM UTC 25 |
90593752 ps |
| T1004 |
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3402519712 |
|
|
Feb 09 02:42:33 PM UTC 25 |
Feb 09 02:42:36 PM UTC 25 |
17529588 ps |