30db5a999| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 10.000s | 76.334us | 1 | 1 | 100.00 |
| V1 | single_binary | otbn_single | 2.317m | 623.986us | 95 | 100 | 95.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 6.000s | 35.809us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 6.000s | 19.963us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 9.000s | 534.401us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 6.000s | 19.453us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 10.000s | 41.562us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 6.000s | 19.963us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 6.000s | 19.453us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 36.000s | 1.167ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 17.000s | 947.554us | 5 | 5 | 100.00 |
| V1 | TOTAL | 161 | 166 | 96.99 | |||
| V2 | reset_recovery | otbn_reset | 31.000s | 136.381us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 1.100m | 283.395us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 1.033m | 254.740us | 8 | 10 | 80.00 |
| V2 | stress_all | otbn_stress_all | 1.317m | 375.149us | 8 | 10 | 80.00 |
| V2 | lc_escalation | otbn_escalate | 31.000s | 514.142us | 44 | 60 | 73.33 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 9.000s | 20.223us | 4 | 5 | 80.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 21.000s | 49.455us | 9 | 10 | 90.00 |
| V2 | alert_test | otbn_alert_test | 8.000s | 15.052us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 7.000s | 19.116us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 10.000s | 709.287us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 10.000s | 709.287us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 6.000s | 35.809us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 19.963us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 19.453us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 7.000s | 21.223us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 6.000s | 35.809us | 5 | 5 | 100.00 |
| otbn_csr_rw | 6.000s | 19.963us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 6.000s | 19.453us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 7.000s | 21.223us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 224 | 246 | 91.06 | |||
| V2S | mem_integrity | otbn_imem_err | 11.000s | 16.544us | 9 | 10 | 90.00 |
| otbn_dmem_err | 15.000s | 136.239us | 13 | 15 | 86.67 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 10.000s | 65.624us | 3 | 5 | 60.00 |
| otbn_controller_ispr_rdata_err | 9.000s | 140.140us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 5.150m | 1.471ms | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 12.000s | 57.547us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 8.000s | 89.330us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 8.000s | 35.308us | 2 | 2 | 100.00 |
| V2S | tl_intg_err | otbn_sec_cm | 5.033m | 5.437ms | 5 | 5 | 100.00 |
| otbn_tl_intg_err | 30.000s | 182.304us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 52.000s | 290.672us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 5.033m | 5.437ms | 5 | 5 | 100.00 |
| V2S | prim_count_check | otbn_sec_cm | 5.033m | 5.437ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 10.000s | 76.334us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 15.000s | 136.239us | 13 | 15 | 86.67 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 11.000s | 16.544us | 9 | 10 | 90.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 30.000s | 182.304us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 31.000s | 514.142us | 44 | 60 | 73.33 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 11.000s | 16.544us | 9 | 10 | 90.00 |
| otbn_dmem_err | 15.000s | 136.239us | 13 | 15 | 86.67 | ||
| otbn_zero_state_err_urnd | 9.000s | 20.223us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 89.330us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 5.033m | 5.437ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 5.033m | 5.437ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 2.317m | 623.986us | 95 | 100 | 95.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 16.544us | 9 | 10 | 90.00 |
| otbn_dmem_err | 15.000s | 136.239us | 13 | 15 | 86.67 | ||
| otbn_zero_state_err_urnd | 9.000s | 20.223us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 89.330us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 5.033m | 5.437ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 5.033m | 5.437ms | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 31.000s | 514.142us | 44 | 60 | 73.33 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 11.000s | 16.544us | 9 | 10 | 90.00 |
| otbn_dmem_err | 15.000s | 136.239us | 13 | 15 | 86.67 | ||
| otbn_zero_state_err_urnd | 9.000s | 20.223us | 4 | 5 | 80.00 | ||
| otbn_illegal_mem_acc | 8.000s | 89.330us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 5.033m | 5.437ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 5.033m | 5.437ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 2.317m | 623.986us | 95 | 100 | 95.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 9.000s | 65.411us | 10 | 12 | 83.33 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 8.000s | 20.654us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 1.117m | 172.499us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 1.117m | 172.499us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 11.000s | 31.315us | 9 | 10 | 90.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 5.033m | 5.437ms | 5 | 5 | 100.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 5.033m | 5.437ms | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 22.000s | 99.797us | 9 | 10 | 90.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 5.033m | 5.437ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 5.033m | 5.437ms | 5 | 5 | 100.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 1.167m | 10.017ms | 2 | 5 | 40.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 1.167m | 10.017ms | 2 | 5 | 40.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 20.000s | 35.054us | 6 | 7 | 85.71 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 2.317m | 623.986us | 95 | 100 | 95.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 2.317m | 623.986us | 95 | 100 | 95.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 2.317m | 623.986us | 95 | 100 | 95.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 1.033m | 254.740us | 8 | 10 | 80.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 2.317m | 623.986us | 95 | 100 | 95.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 2.317m | 623.986us | 95 | 100 | 95.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 29.000s | 960.725us | 4 | 5 | 80.00 |
| V2S | sec_cm_key_sideload | otbn_single | 2.317m | 623.986us | 95 | 100 | 95.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 5.033m | 5.437ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 139 | 153 | 90.85 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 10.933m | 10.172ms | 5 | 10 | 50.00 |
| V3 | TOTAL | 5 | 10 | 50.00 | |||
| TOTAL | 529 | 575 | 92.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 11 | 11 | 6 | 54.55 |
| V2S | 19 | 19 | 10 | 52.63 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.74 | 99.52 | 94.33 | 99.63 | 90.94 | 93.03 | 97.44 | 91.17 | 99.16 |
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 6 failures:
Test otbn_stack_addr_integ_chk has 2 failures.
0.otbn_stack_addr_integ_chk.2170334107
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 63022705 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 63022705 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 63022705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.otbn_stack_addr_integ_chk.79517254
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 6223380 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 6223380 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 6223380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_zero_state_err_urnd has 1 failures.
2.otbn_zero_state_err_urnd.2368072523
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_zero_state_err_urnd/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 6549134 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 6549134 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 6549134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 2 failures.
6.otbn_escalate.2969746748
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 22238479 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 22238479 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 22238479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.otbn_escalate.1482553562
Line 239, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 21231838 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 21231838 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 21231838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_ctrl_redun has 1 failures.
8.otbn_ctrl_redun.3412719851
Line 247, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 72484068 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 72484068 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 72484068 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 72484068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 4 failures:
3.otbn_escalate.2549538615
Line 262, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3527894 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 3527894 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 3527894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.otbn_escalate.397359802
Line 261, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/21.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 1480258 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 1480258 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 1480258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,270): Assertion MatchingStatus_A has failed has 4 failures:
Test otbn_rf_base_intg_err has 1 failures.
3.otbn_rf_base_intg_err.191746779
Line 244, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_rf_base_intg_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 57000512 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 57000512 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 57000512 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 57000512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_escalate has 3 failures.
7.otbn_escalate.543076003
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 5865817 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 5865817 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 5865817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
51.otbn_escalate.2580168738
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/51.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,270): (time 68428348 PS) Assertion tb.MatchingStatus_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 68428348 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 68428348 ps: (tb.sv:270) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 68428348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 4 failures:
41.otbn_single.2965045776
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/41.otbn_single/latest/run.log
UVM_FATAL @ 35949630 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 35949630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.otbn_single.262429012
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/49.otbn_single/latest/run.log
UVM_FATAL @ 54833983 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 54833983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 3 failures:
Test otbn_stress_all has 2 failures.
2.otbn_stress_all.1668213526
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all/latest/run.log
UVM_FATAL @ 104692182 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 104692182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.otbn_stress_all.3076064683
Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all/latest/run.log
UVM_FATAL @ 299673401 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 299673401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stress_all_with_rand_reset has 1 failures.
6.otbn_stress_all_with_rand_reset.1792312310
Line 292, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 48316539 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 48316539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
1.otbn_escalate.1813979394
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_escalate/latest/run.log
UVM_FATAL @ 21194767 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 21194767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
54.otbn_escalate.1223704812
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/54.otbn_escalate/latest/run.log
UVM_FATAL @ 13504959 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 13504959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 2 failures:
Test otbn_stress_all_with_rand_reset has 1 failures.
1.otbn_stress_all_with_rand_reset.868132721
Line 313, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1102593847 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 1102593847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_dmem_err has 1 failures.
5.otbn_dmem_err.537060563
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_dmem_err/latest/run.log
UVM_FATAL @ 9000305 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 9000305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
2.otbn_escalate.3179315508
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log
UVM_FATAL @ 22621414 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 22621414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.otbn_escalate.1790688491
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log
UVM_FATAL @ 38214872 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 38214872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_alu_bignum_mod_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 2 failures:
2.otbn_alu_bignum_mod_err.257601555
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_alu_bignum_mod_err/latest/run.log
UVM_FATAL @ 9306593 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_alu_bignum_mod_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 9306593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.otbn_alu_bignum_mod_err.3877924824
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_alu_bignum_mod_err/latest/run.log
UVM_FATAL @ 9450604 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_alu_bignum_mod_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 9450604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 2 failures:
Test otbn_stress_all_with_rand_reset has 1 failures.
3.otbn_stress_all_with_rand_reset.1190298305
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 103601119 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 103601119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_single has 1 failures.
95.otbn_single.1993403753
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/95.otbn_single/latest/run.log
UVM_FATAL @ 108008709 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 108008709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:495) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 2 failures:
Test otbn_sw_errs_fatal_chk has 1 failures.
3.otbn_sw_errs_fatal_chk.1141018987
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sw_errs_fatal_chk/latest/run.log
UVM_FATAL @ 30522011 ps: (otbn_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 400 cycles ago and we still don't think it should have done.
UVM_INFO @ 30522011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test otbn_stress_all_with_rand_reset has 1 failures.
7.otbn_stress_all_with_rand_reset.2931535454
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 467640200 ps: (otbn_scoreboard.sv:495) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 400 cycles ago and we still don't think it should have done.
UVM_INFO @ 467640200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 2 failures:
12.otbn_escalate.698070843
Line 261, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/12.otbn_escalate/latest/run.log
UVM_FATAL @ 9174995 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 9174995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.otbn_escalate.1031971874
Line 260, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/44.otbn_escalate/latest/run.log
UVM_FATAL @ 5105949 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
UVM_INFO @ 5105949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_sec_wipe_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
0.otbn_sec_wipe_err.1468972635
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log
UVM_FATAL @ 5151984 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_sec_wipe_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 5151984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_sw_no_acc_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
1.otbn_sw_no_acc.3147681040
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sw_no_acc/latest/run.log
UVM_FATAL @ 13784938 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_sw_no_acc_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 13784938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
1.otbn_stack_addr_integ_chk.703508539
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log
UVM_FATAL @ 10017152288 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
UVM_INFO @ 10017152288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_multi_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
2.otbn_multi.1574403583
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_multi/latest/run.log
UVM_FATAL @ 606714109 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_multi_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 606714109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,943): Assertion OnlyWriteLoadDataBignumWhenDMemValid_A has failed has 1 failures:
2.otbn_ctrl_redun.1828719784
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_ctrl_redun/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,943): (time 25440779 PS) Assertion tb.dut.u_otbn_core.OnlyWriteLoadDataBignumWhenDMemValid_A has failed
UVM_ERROR @ 25440779 ps: (otbn_core.sv:943) [ASSERT FAILED] OnlyWriteLoadDataBignumWhenDMemValid_A
UVM_INFO @ 25440779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_rf_bignum_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
3.otbn_rf_bignum_intg_err.4004132935
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_rf_bignum_intg_err/latest/run.log
UVM_FATAL @ 12964097 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_rf_bignum_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 12964097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_multi_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
4.otbn_multi.1506971030
Line 277, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_multi/latest/run.log
UVM_FATAL @ 23375107 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_multi_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 23375107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
4.otbn_dmem_err.2273598086
Line 240, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_dmem_err/latest/run.log
UVM_FATAL @ 11320600 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 11320600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:582) [otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
5.otbn_imem_err.2184618501
Line 241, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_imem_err/latest/run.log
UVM_FATAL @ 22934428 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 22934428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:369) [otbn_imem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
9.otbn_stress_all_with_rand_reset.1019089180
Line 349, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1534055367 ps: (otbn_base_vseq.sv:369) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 1534055367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:582) [otbn_escalate_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o) has 1 failures:
36.otbn_escalate.1299285127
Line 242, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/36.otbn_escalate/latest/run.log
UVM_FATAL @ 25647257 ps: (otbn_base_vseq.sv:582) [uvm_test_top.env.virtual_sequencer.otbn_escalate_vseq] Check failed (!(cfg.loop_vif.loop_stack_push || cfg.loop_vif.loop_stack_pop) && !cfg.trace_vif.locking_o)
UVM_INFO @ 25647257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---