OTBN Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	103.110us	1	1	100.00
V1	single_binary	otbn_single	1.617m	300.194us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	23.330us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	16.615us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	65.019us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	24.980us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	110.710us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	16.615us	20	20	100.00
		otbn_csr_aliasing	5.000s	24.980us	5	5	100.00
V1	mem_walk	otbn_mem_walk	35.000s	4.745ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	14.000s	158.161us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	48.000s	222.814us	10	10	100.00
V2	multi_error	otbn_multi_err	51.000s	556.011us	1	1	100.00
V2	back_to_back	otbn_multi	1.917m	205.857us	10	10	100.00
V2	stress_all	otbn_stress_all	1.550m	3.438ms	10	10	100.00
V2	lc_escalation	otbn_escalate	31.000s	203.324us	54	60	90.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	23.951us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	17.000s	374.584us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	150.804us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	19.664us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	9.000s	45.516us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	9.000s	45.516us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	23.330us	5	5	100.00
		otbn_csr_rw	6.000s	16.615us	20	20	100.00
		otbn_csr_aliasing	5.000s	24.980us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	19.066us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	23.330us	5	5	100.00
		otbn_csr_rw	6.000s	16.615us	20	20	100.00
		otbn_csr_aliasing	5.000s	24.980us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	19.066us	20	20	100.00
V2		TOTAL			239	246	97.15
V2S	mem_integrity	otbn_imem_err	12.000s	44.620us	10	10	100.00
		otbn_dmem_err	20.000s	71.954us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	63.752us	5	5	100.00
		otbn_controller_ispr_rdata_err	13.000s	67.310us	5	5	100.00
		otbn_mac_bignum_acc_err	11.000s	63.240us	5	5	100.00
		otbn_urnd_err	7.000s	10.810us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	76.517us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	21.316us	2	2	100.00
V2S	tl_intg_err	otbn_sec_cm	6.167m	1.790ms	4	5	80.00
		otbn_tl_intg_err	1.183m	548.003us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	39.000s	207.411us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.167m	1.790ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	6.167m	1.790ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	103.110us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	20.000s	71.954us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	44.620us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.183m	548.003us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	31.000s	203.324us	54	60	90.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	44.620us	10	10	100.00
		otbn_dmem_err	20.000s	71.954us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	23.951us	4	5	80.00
		otbn_illegal_mem_acc	7.000s	76.517us	5	5	100.00
		otbn_sec_cm	6.167m	1.790ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.167m	1.790ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.617m	300.194us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	44.620us	10	10	100.00
		otbn_dmem_err	20.000s	71.954us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	23.951us	4	5	80.00
		otbn_illegal_mem_acc	7.000s	76.517us	5	5	100.00
		otbn_sec_cm	6.167m	1.790ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.167m	1.790ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	31.000s	203.324us	54	60	90.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	44.620us	10	10	100.00
		otbn_dmem_err	20.000s	71.954us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	23.951us	4	5	80.00
		otbn_illegal_mem_acc	7.000s	76.517us	5	5	100.00
		otbn_sec_cm	6.167m	1.790ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.167m	1.790ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.617m	300.194us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	36.488us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	17.905us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.400m	574.186us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.400m	574.186us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	13.000s	76.958us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.167m	1.790ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.167m	1.790ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	82.589us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.167m	1.790ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.167m	1.790ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	1.467m	10.010ms	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	1.467m	10.010ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	4.083m	1.132ms	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.617m	300.194us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.617m	300.194us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.617m	300.194us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.917m	205.857us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.617m	300.194us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.617m	300.194us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	20.000s	43.167us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.617m	300.194us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.167m	1.790ms	4	5	80.00
V2S		TOTAL			151	153	98.69
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	11.333m	3.215ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			562	575	97.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	19	19	17	89.47
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.78	99.53	94.46	99.63	91.05	93.51	94.87	91.52	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 3 failures:

Test otbn_escalate has 3 failures.

5.otbn_escalate.95459441598529432931238010620689297858294685296600505592104283923566962781285
Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 3269974 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   3269974 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   3269974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.otbn_escalate.59981360299010243453080603750557108669065206205064189808771630680919483807957
Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/27.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 6141500 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   6141500 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @   6141500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 1.otbn_stress_all_with_rand_reset.76487374469226928860126483488545567948391128384822025952024693299111413816184
    Line 369, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 365950075 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 365950075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_stress_all_with_rand_reset.114758493078884694642958781175014450590327673495695044805698518506213641312632
    Line 322, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   3774997 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @   3774997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_zero_state_err_urnd has 1 failures.
  - 0.otbn_zero_state_err_urnd.85708693624613617833607440821131169988261829272394940204652958645019436537003
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19308607 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  19308607 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  19308607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1298): Assertion SecWipeNonZeroMod_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

0.otbn_sec_cm.42998205815610987919607410330662412385318050747982400852672722676080624516615
Line 263, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1298): (time 4381033 PS) Assertion tb.dut.SecWipeNonZeroMod_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1305): (time 4381033 PS) Assertion tb.dut.SecWipeNonZeroACC_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1259): (time 4381033 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[31].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1259): (time 4381033 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[30].InitSecWipeNonZeroWideRegs_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1259): (time 4381033 PS) Assertion tb.dut.g_secure_wipe_assertions.gen_sec_wipe_wdr_asserts[29].InitSecWipeNonZeroWideRegs_A has failed

UVM_FATAL (otbn_stack_addr_integ_chk_vseq.sv:72) [otbn_stack_addr_integ_chk_vseq] timeout occurred! has 1 failures:
- Test otbn_stack_addr_integ_chk has 1 failures.
  - 3.otbn_stack_addr_integ_chk.109898628391730019725057742851891246879418878564511246112258092715268323098564
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log
```
  UVM_FATAL @ 10009805296 ps: (otbn_stack_addr_integ_chk_vseq.sv:72) [uvm_test_top.env.virtual_sequencer.otbn_stack_addr_integ_chk_vseq] timeout occurred!
  UVM_INFO @ 10009805296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.51443020330852875199980253213752906194009805562330053006461002657606761237915
    Line 367, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 999790890 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 999790890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.5840734343628604341423993724950130560058962335463401938143932776671401785680
    Line 399, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3214654358 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 3214654358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == *) Failed to update CRC has 1 failures:
- Test otbn_escalate has 1 failures.
  - 17.otbn_escalate.83835937466253549914322294141143741874476132765309041321797849863859588061431
    Line 299, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/17.otbn_escalate/latest/run.log
```
  UVM_FATAL @   7716847 ps: (otbn_model_if.sv:77) [otbn_model_if] Check failed (u_model.otbn_model_step_crc(handle, item, crc_state) == 0) Failed to update CRC
  UVM_INFO @   7716847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 32.otbn_escalate.46803232543331266331922914278837447905333275804786309486858743844871117527625
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/32.otbn_escalate/latest/run.log
```
  UVM_FATAL @   8298548 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @   8298548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:538) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 35.otbn_escalate.81457819994169744247397051374509948167828825403302749780717421401679597901058
    Line 279, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/35.otbn_escalate/latest/run.log
```
  UVM_FATAL @  11958612 ps: (otbn_scoreboard.sv:538) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  11958612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```