OTP_CTRL Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: 30db5a999

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.780s	77.570us	1	1	100.00
V1	smoke	otp_ctrl_smoke	11.170s	4.087ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.210s	1.365ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.000s	549.260us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.230s	673.673us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	3.610s	1.150ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.780s	1.616ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.000s	549.260us	20	20	100.00
		otp_ctrl_csr_aliasing	3.610s	1.150ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.470s	109.219us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.770s	541.045us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	21.760s	12.909ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.840s	2.874ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	20.330s	8.399ms	10	10	100.00
		otp_ctrl_check_fail	27.670s	3.548ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.690s	4.573ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	25.450s	3.029ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	33.470s	14.474ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	23.990s	10.997ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	12.430s	1.880ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	21.840s	6.948ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.490m	10.240ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	22.800s	4.090ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	3.185m	51.259ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.020s	568.522us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.300s	577.915us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.170s	572.271us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.170s	572.271us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.210s	1.365ms	5	5	100.00
		otp_ctrl_csr_rw	2.000s	549.260us	20	20	100.00
		otp_ctrl_csr_aliasing	3.610s	1.150ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.430s	1.424ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.210s	1.365ms	5	5	100.00
		otp_ctrl_csr_rw	2.000s	549.260us	20	20	100.00
		otp_ctrl_csr_aliasing	3.610s	1.150ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.430s	1.424ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
		otp_ctrl_tl_intg_err	22.470s	18.973ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	22.470s	18.973ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	11.170s	4.087ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	11.170s	4.087ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.430s	1.880ms	200	200	100.00
		otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.430s	1.880ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.430s	1.880ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.430s	1.880ms	200	200	100.00
		otp_ctrl_macro_errs	1.490m	10.240ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.430s	1.880ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.430s	1.880ms	200	200	100.00
		otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.430s	1.880ms	200	200	100.00
		otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.430s	1.880ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.430s	1.880ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.430s	1.880ms	200	200	100.00
		otp_ctrl_macro_errs	1.490m	10.240ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.430s	1.880ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.430s	1.880ms	200	200	100.00
		otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.840s	2.874ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	27.670s	3.548ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	25.450s	3.029ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	25.450s	3.029ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	25.450s	3.029ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	25.450s	3.029ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	25.450s	3.029ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	11.170s	4.087ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	25.450s	3.029ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	11.170s	4.087ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	2.654m	30.207ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.690s	4.573ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	11.170s	4.087ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	11.170s	4.087ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.490m	10.240ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	14.210s	6.031ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.944h	7.683s	91	100	91.00
V3		TOTAL			92	101	91.09
		TOTAL			1334	1343	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.36	92.63	91.11	92.29	92.39	93.29	96.53	95.27

Failure Buckets

• Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 8 failures.

    • 24.otp_ctrl_stress_all_with_rand_reset.768159106
      Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:afccd78e-0203-4428-a3df-c3711c5e332e
      

    • 35.otp_ctrl_stress_all_with_rand_reset.3397804197
      Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:be642577-328e-4402-b0a4-bb7270a1e25c
      

    • ... and 6 more failures.

• UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 1 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 97.otp_ctrl_stress_all_with_rand_reset.3534273634
      Line 250, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  53520795 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @  53520795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.18_19.15.40
• 2023.05.17_17.59.32
• 2023.05.16_19.23.36
• 2023.05.15_18.41.17
• 2023.05.14_18.09.01
• 2023.05.13_18.52.45
• 2023.05.12_18.43.45