Unified Coverage Report :: Module :: otp_ctrl_ecc_reg

Module : otp_ctrl_ecc_reg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg	0.00	0.00	0.00			0.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg	0.00	0.00	0.00			0.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg	0.00	0.00	0.00			0.00
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	0.00	0.00	0.00			0.00
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	0.00	0.00	0.00			0.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	0.00	0.00	0.00			0.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	0.00	0.00	0.00			0.00
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[3].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[4].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_partitions[7].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	0.00			0.00
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	0.00			0.00
u_prim_secded_inv_72_64_enc	0.00			0.00

Line Coverage for Module : otp_ctrl_ecc_reg ( parameter Width=64,Depth=1,Aw=1,EccWidth=8 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	0	0.00
ALWAYS	45	5	0	0.00
CONT_ASSIGN	78	1	0	0.00
ALWAYS	81	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
47	0	1
49	0	1
50	0	1
			==> MISSING_ELSE
78	0	1
81	0	1
82	0	1
83	0	1
85	0	1
86	0	1

---

Line Coverage for Module : otp_ctrl_ecc_reg ( parameter Width=64,Depth=10,Aw=4,EccWidth=8 + Width=64,Depth=5,Aw=3,EccWidth=8 + Width=64,Depth=11,Aw=4,EccWidth=8 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	0	0.00
ALWAYS	55	5	0	0.00
CONT_ASSIGN	78	1	0	0.00
ALWAYS	81	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	0	1
56	0	1
57	0	1
59	0	1
60	0	1
			==> MISSING_ELSE
78	0	1
81	0	1
82	0	1
83	0	1
85	0	1
86	0	1

---

Cond Coverage for Module : otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	0	0.00
IF	81	2	0	0.00
IF	49	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	0	0.00
ALWAYS	45	5	0	0.00
CONT_ASSIGN	78	1	0	0.00
ALWAYS	81	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
47	0	1
49	0	1
50	0	1
			==> MISSING_ELSE
78	0	1
81	0	1
82	0	1
83	0	1
85	0	1
86	0	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	2	0	0.00
Logical	2	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	0	0.00
IF	81	2	0	0.00
IF	49	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	0	0.00
ALWAYS	45	5	0	0.00
CONT_ASSIGN	78	1	0	0.00
ALWAYS	81	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
47	0	1
49	0	1
50	0	1
			==> MISSING_ELSE
78	0	1
81	0	1
82	0	1
83	0	1
85	0	1
86	0	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	2	0	0.00
Logical	2	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	0	0.00
IF	81	2	0	0.00
IF	49	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	0	0.00
ALWAYS	45	5	0	0.00
CONT_ASSIGN	78	1	0	0.00
ALWAYS	81	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
47	0	1
49	0	1
50	0	1
			==> MISSING_ELSE
78	0	1
81	0	1
82	0	1
83	0	1
85	0	1
86	0	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	2	0	0.00
Logical	2	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	0	0.00
IF	81	2	0	0.00
IF	49	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	0	0.00
ALWAYS	55	5	0	0.00
CONT_ASSIGN	78	1	0	0.00
ALWAYS	81	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	0	1
56	0	1
57	0	1
59	0	1
60	0	1
			==> MISSING_ELSE
78	0	1
81	0	1
82	0	1
83	0	1
85	0	1
86	0	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	0	0.00
IF	81	2	0	0.00
IF	49	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	0	0.00
ALWAYS	55	5	0	0.00
CONT_ASSIGN	78	1	0	0.00
ALWAYS	81	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	0	1
56	0	1
57	0	1
59	0	1
60	0	1
			==> MISSING_ELSE
78	0	1
81	0	1
82	0	1
83	0	1
85	0	1
86	0	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	0	0.00
IF	81	2	0	0.00
IF	49	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	0	0.00
ALWAYS	55	5	0	0.00
CONT_ASSIGN	78	1	0	0.00
ALWAYS	81	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	0	1
56	0	1
57	0	1
59	0	1
60	0	1
			==> MISSING_ELSE
78	0	1
81	0	1
82	0	1
83	0	1
85	0	1
86	0	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	0	0.00
IF	81	2	0	0.00
IF	49	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	0	0.00
ALWAYS	55	5	0	0.00
CONT_ASSIGN	78	1	0	0.00
ALWAYS	81	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	0	1
56	0	1
57	0	1
59	0	1
60	0	1
			==> MISSING_ELSE
78	0	1
81	0	1
82	0	1
83	0	1
85	0	1
86	0	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	0	0.00
IF	81	2	0	0.00
IF	49	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	0	0.00
ALWAYS	55	5	0	0.00
CONT_ASSIGN	78	1	0	0.00
ALWAYS	81	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	0	1
56	0	1
57	0	1
59	0	1
60	0	1
			==> MISSING_ELSE
78	0	1
81	0	1
82	0	1
83	0	1
85	0	1
86	0	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	0	0.00
IF	81	2	0	0.00
IF	49	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered