Unified Coverage Report :: Module :: otp_ctrl_part_unbuf

Module : otp_ctrl_part_unbuf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf	0.00	0.00	0.00		0.00	0.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf	0.00	0.00	0.00		0.00	0.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
7.86	0.00	0.00	31.46		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	0.00	0.00				0.00
u_otp_ctrl_ecc_reg	0.00	0.00	0.00	0.00		0.00
u_prim_mubi8_sender_read_lock_pre	0.00	0.00				0.00
u_prim_mubi8_sender_write_lock_pre	0.00	0.00				0.00
u_state_regs	0.00	0.00				0.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
7.86	0.00	0.00	31.46		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	0.00	0.00				0.00
u_otp_ctrl_ecc_reg	0.00	0.00	0.00	0.00		0.00
u_prim_mubi8_sender_read_lock_pre	0.00	0.00				0.00
u_prim_mubi8_sender_write_lock_pre	0.00	0.00				0.00
u_state_regs	0.00	0.00				0.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
7.86	0.00	0.00	31.46		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	0.00	0.00				0.00
u_otp_ctrl_ecc_reg	0.00	0.00	0.00	0.00		0.00
u_prim_mubi8_sender_read_lock_pre	0.00	0.00				0.00
u_prim_mubi8_sender_write_lock_pre	0.00	0.00				0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	0	0.00
CONT_ASSIGN	137	1	0	0.00
ALWAYS	147	67	0	0.00
CONT_ASSIGN	328	1	0	0.00
CONT_ASSIGN	330	1	0	0.00
CONT_ASSIGN	335	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
CONT_ASSIGN	340	1	0	0.00
CONT_ASSIGN	344	1	0	0.00
CONT_ASSIGN	371	1	0	0.00
CONT_ASSIGN	396	1	0	0.00
CONT_ASSIGN	430	1	0	0.00
ALWAYS	437	3	0	0.00
ALWAYS	440	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	0	1
147	0	1
150	0	1
153	0	1
154	0	1
157	0	1
158	0	1
159	0	1
162	0	1
165	0	1
166	0	1
167	0	1
169	0	1
174	0	1
175	0	1
			==> MISSING_ELSE
183	0	1
184	0	1
185	0	1
			==> MISSING_ELSE
193	0	1
194	0	1
197	0	1
199	0	1
205	0	1
206	0	1
			==> MISSING_ELSE
209	0	1
210	0	1
			==> MISSING_ELSE
218	0	1
219	0	1
220	0	1
221	0	1
222	0	1
			==> MISSING_ELSE
231	0	1
233	0	1
236	0	1
237	0	1
238	0	1
239	0	1
			==> MISSING_ELSE
242	0	1
243	0	1
244	0	1
245	0	1
253	0	1
254	0	1
255	0	1
258	0	1
260	0	1
266	0	1
267	0	1
			==> MISSING_ELSE
270	0	1
271	0	1
273	0	1
			==> MISSING_ELSE
282	0	1
283	0	1
			==> MISSING_ELSE
287	0	1
288	0	1
289	0	1
290	0	1
291	0	1
292	0	1
			==> MISSING_ELSE
308	0	1
309	0	1
310	0	1
311	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
315	0	1
316	0	1
317	0	1
318	0	1
319	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
328	0	1
330	0	1
335	0	1
336	0	1
340	0	1
344	0	1
371	0	1
396	0	1
430	0	1
437	0	3
440	0	1
441	0	1
442	0	1
443	0	1
445	0	1
446	0	1
447	0	1
448	0	1
			==> MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	0	0.00
CONT_ASSIGN	137	1	0	0.00
ALWAYS	147	67	0	0.00
CONT_ASSIGN	328	1	0	0.00
CONT_ASSIGN	330	1	0	0.00
CONT_ASSIGN	335	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
CONT_ASSIGN	340	1	0	0.00
CONT_ASSIGN	344	1	0	0.00
CONT_ASSIGN	371	1	0	0.00
CONT_ASSIGN	396	1	0	0.00
CONT_ASSIGN	430	1	0	0.00
ALWAYS	437	3	0	0.00
ALWAYS	440	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	0	1
147	0	1
150	0	1
153	0	1
154	0	1
157	0	1
158	0	1
159	0	1
162	0	1
165	0	1
166	0	1
167	0	1
169	0	1
174	0	1
175	0	1
			==> MISSING_ELSE
183	0	1
184	0	1
185	0	1
			==> MISSING_ELSE
193	0	1
194	0	1
197	0	1
199	0	1
205	0	1
206	0	1
			==> MISSING_ELSE
209	0	1
210	0	1
			==> MISSING_ELSE
218	0	1
219	0	1
220	0	1
221	0	1
222	0	1
			==> MISSING_ELSE
231	0	1
233	0	1
236	0	1
237	0	1
238	0	1
239	0	1
			==> MISSING_ELSE
242	0	1
243	0	1
244	0	1
245	0	1
253	0	1
254	0	1
255	0	1
258	0	1
260	0	1
266	0	1
267	0	1
			==> MISSING_ELSE
270	0	1
271	0	1
273	0	1
			==> MISSING_ELSE
282	0	1
283	0	1
			==> MISSING_ELSE
287	0	1
288	0	1
289	0	1
290	0	1
291	0	1
292	0	1
			==> MISSING_ELSE
308	0	1
309	0	1
310	0	1
311	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
315	0	1
316	0	1
317	0	1
318	0	1
319	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
328	0	1
330	0	1
335	0	1
336	0	1
340	0	1
344	0	1
371	0	1
396	0	1
430	0	1
437	0	3
440	0	1
441	0	1
442	0	1
443	0	1
445	0	1
446	0	1
447	0	1
448	0	1
			==> MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=226594821,DigestOffset=1656,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	0	0.00
CONT_ASSIGN	137	1	0	0.00
ALWAYS	147	67	0	0.00
CONT_ASSIGN	328	1	0	0.00
CONT_ASSIGN	330	1	0	0.00
CONT_ASSIGN	335	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
CONT_ASSIGN	340	1	0	0.00
CONT_ASSIGN	344	1	0	0.00
CONT_ASSIGN	371	1	0	0.00
CONT_ASSIGN	396	1	0	0.00
CONT_ASSIGN	430	1	0	0.00
ALWAYS	437	3	0	0.00
ALWAYS	440	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	0	1
147	0	1
150	0	1
153	0	1
154	0	1
157	0	1
158	0	1
159	0	1
162	0	1
165	0	1
166	0	1
167	0	1
169	0	1
174	0	1
175	0	1
			==> MISSING_ELSE
183	0	1
184	0	1
185	0	1
			==> MISSING_ELSE
193	0	1
194	0	1
197	0	1
199	0	1
205	0	1
206	0	1
			==> MISSING_ELSE
209	0	1
210	0	1
			==> MISSING_ELSE
218	0	1
219	0	1
220	0	1
221	0	1
222	0	1
			==> MISSING_ELSE
231	0	1
233	0	1
236	0	1
237	0	1
238	0	1
239	0	1
			==> MISSING_ELSE
242	0	1
243	0	1
244	0	1
245	0	1
253	0	1
254	0	1
255	0	1
258	0	1
260	0	1
266	0	1
267	0	1
			==> MISSING_ELSE
270	0	1
271	0	1
273	0	1
			==> MISSING_ELSE
282	0	1
283	0	1
			==> MISSING_ELSE
287	0	1
288	0	1
289	0	1
290	0	1
291	0	1
292	0	1
			==> MISSING_ELSE
308	0	1
309	0	1
310	0	1
311	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
315	0	1
316	0	1
317	0	1
318	0	1
319	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
328	0	1
330	0	1
335	0	1
336	0	1
340	0	1
344	0	1
371	0	1
396	0	1
430	0	1
437	0	3
440	0	1
441	0	1
442	0	1
443	0	1
445	0	1
446	0	1
447	0	1
448	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	45	0	0.00
Logical	45	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       197
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Not Covered
-	1	Not Covered

 LINE       197
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       258
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       258
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Not Covered
-	1	Not Covered

 LINE       258
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 + Info=226594821,DigestOffset=1656,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

SCORE	COND
0.00	0.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	0	0.00
Logical	35	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : otp_ctrl_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Not Covered
IdleSt	199	Not Covered
InitSt	175	Not Covered
InitWaitSt	185	Not Covered
ReadSt	221	Not Covered
ReadWaitSt	239	Not Covered
ResetSt	173	Not Covered

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Not Covered
IdleSt->ReadSt	221	Not Covered
InitSt->ErrorSt	309	Not Covered
InitSt->InitWaitSt	185	Not Covered
InitWaitSt->ErrorSt	209	Not Covered
InitWaitSt->IdleSt	199	Not Covered
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Not Covered
ReadSt->ReadWaitSt	239	Not Covered
ReadWaitSt->ErrorSt	270	Not Covered
ReadWaitSt->IdleSt	260	Not Covered
ResetSt->ErrorSt	309	Not Covered
ResetSt->InitSt	175	Not Covered

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	20	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Not Covered
CheckFailError	311	Not Covered
FsmStateError	283	Not Covered
MacroEccCorrError	206	Not Covered
NoError	220	Not Covered

transitions	Line No.	Covered	Tests
AccessError->CheckFailError	311	Not Covered
AccessError->FsmStateError	319	Not Covered
AccessError->MacroEccCorrError	206	Not Covered
AccessError->NoError	220	Not Covered
CheckFailError->AccessError	243	Not Covered
CheckFailError->FsmStateError	319	Not Covered
CheckFailError->MacroEccCorrError	206	Not Covered
CheckFailError->NoError	220	Not Covered
FsmStateError->AccessError	243	Not Covered
FsmStateError->CheckFailError	311	Not Covered
FsmStateError->MacroEccCorrError	206	Not Covered
FsmStateError->NoError	220	Not Covered
MacroEccCorrError->AccessError	243	Not Covered
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Not Covered
MacroEccCorrError->NoError	220	Not Covered
NoError->AccessError	243	Not Covered
NoError->CheckFailError	311	Not Covered
NoError->FsmStateError	283	Not Covered
NoError->MacroEccCorrError	206	Not Covered

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	0	0.00
TERNARY	330	2	0	0.00
TERNARY	335	2	0	0.00
TERNARY	344	2	0	0.00
TERNARY	371	2	0	0.00
TERNARY	396	2	0	0.00
CASE	169	23	0	0.00
IF	308	3	0	0.00
IF	315	3	0	0.00
IF	437	2	0	0.00
IF	440	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=226594821,DigestOffset=1656,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	0	0.00
TERNARY	330	2	0	0.00
TERNARY	335	2	0	0.00
TERNARY	344	2	0	0.00
TERNARY	371	2	0	0.00
TERNARY	396	2	0	0.00
CASE	169	23	0	0.00
IF	308	3	0	0.00
IF	315	3	0	0.00
IF	437	2	0	0.00
IF	440	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	0	0.00
TERNARY	330	2	0	0.00
TERNARY	335	2	0	0.00
TERNARY	344	2	0	0.00
TERNARY	371	2	0	0.00
TERNARY	396	2	0	0.00
CASE	169	23	0	0.00
IF	308	3	0	0.00
IF	315	3	0	0.00
IF	437	2	0	0.00
IF	440	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b0) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		84	0	0.00
CONT_ASSIGN	137	1	0	0.00
ALWAYS	147	63	0	0.00
CONT_ASSIGN	328	1	0	0.00
CONT_ASSIGN	330	1	0	0.00
CONT_ASSIGN	335	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
CONT_ASSIGN	340	1	0	0.00
CONT_ASSIGN	344	1	0	0.00
CONT_ASSIGN	371	1	0	0.00
CONT_ASSIGN	396	1	0	0.00
CONT_ASSIGN	430	1	0	0.00
ALWAYS	437	3	0	0.00
ALWAYS	440	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	0	1
147	0	1
150	0	1
153	0	1
154	0	1
157	0	1
158	0	1
159	0	1
162	0	1
165	0	1
166	0	1
167	0	1
169	0	1
174	0	1
175	0	1
			==> MISSING_ELSE
183	0	1
184	0	1
185	0	1
			==> MISSING_ELSE
193	0	1
194	0	1
197	0	1
199	0	1
205	0	1
206	0	1
			==> MISSING_ELSE
209	0	1
210	0	1
			==> MISSING_ELSE
218	0	1
219	0	1
220	0	1
221	0	1
222	0	1
			==> MISSING_ELSE
231	0	1
233	0	1
236	0	1
237	0	1
238	0	1
239	0	1
			==> MISSING_ELSE
242	0	1
243	0	1
244	0	1
245	0	1
253	0	1
254	0	1
255	0	1
258	0	1
260	0	1
266	0	1
267	0	1
			==> MISSING_ELSE
270		excluded
			Exclude Annotation: VC_COV_UNR
271		excluded
			Exclude Annotation: VC_COV_UNR
273		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
282	0	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
287	0	1
288	0	1
289	0	1
290	0	1
291	0	1
292	0	1
			==> MISSING_ELSE
308	0	1
309	0	1
310	0	1
311	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
315	0	1
316	0	1
317	0	1
318	0	1
319	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
328	0	1
330	0	1
335	0	1
336	0	1
340	0	1
344	0	1
371	0	1
396	0	1
430	0	1
437	0	3
440	0	1
441	0	1
442	0	1
443	0	1
445	0	1
446	0	1
447	0	1
448	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	45	0	0.00
Logical	45	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       197
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Not Covered
-	1	Not Covered

 LINE       197
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       258
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       258
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Not Covered
-	1	Not Covered

 LINE       258
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Not Covered
IdleSt	199	Not Covered
InitSt	175	Not Covered
InitWaitSt	185	Not Covered
ReadSt	221	Not Covered
ReadWaitSt	239	Not Covered
ResetSt	173	Not Covered

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Not Covered
IdleSt->ReadSt	221	Not Covered
InitSt->ErrorSt	309	Not Covered
InitSt->InitWaitSt	185	Not Covered
InitWaitSt->ErrorSt	209	Not Covered
InitWaitSt->IdleSt	199	Not Covered
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Not Covered
ReadSt->ReadWaitSt	239	Not Covered
ReadWaitSt->ErrorSt	270	Not Covered
ReadWaitSt->IdleSt	260	Not Covered
ResetSt->ErrorSt	309	Not Covered
ResetSt->InitSt	175	Not Covered

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	11	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Not Covered
CheckFailError	311	Not Covered
FsmStateError	283	Not Covered
MacroEccCorrError	206	Not Covered
NoError	220	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Not Covered
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Not Covered
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Not Covered
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Not Covered
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Not Covered
MacroEccCorrError->NoError	220	Not Covered
NoError->AccessError	243	Not Covered
NoError->CheckFailError	311	Not Covered
NoError->FsmStateError	283	Not Covered
NoError->MacroEccCorrError	206	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	0	0.00
TERNARY	330	2	0	0.00
TERNARY	335	2	0	0.00
TERNARY	344	2	0	0.00
TERNARY	371	2	0	0.00
TERNARY	396	2	0	0.00
CASE	169	23	0	0.00
IF	308	3	0	0.00
IF	315	3	0	0.00
IF	437	2	0	0.00
IF	440	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b0) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		87	0	0.00
CONT_ASSIGN	137	1	0	0.00
ALWAYS	147	66	0	0.00
CONT_ASSIGN	328	1	0	0.00
CONT_ASSIGN	330	1	0	0.00
CONT_ASSIGN	335	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
CONT_ASSIGN	340	1	0	0.00
CONT_ASSIGN	344	1	0	0.00
CONT_ASSIGN	371	1	0	0.00
CONT_ASSIGN	396	1	0	0.00
CONT_ASSIGN	430	1	0	0.00
ALWAYS	437	3	0	0.00
ALWAYS	440	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	0	1
147	0	1
150	0	1
153	0	1
154	0	1
157	0	1
158	0	1
159	0	1
162	0	1
165	0	1
166	0	1
167	0	1
169	0	1
174	0	1
175	0	1
			==> MISSING_ELSE
183	0	1
184	0	1
185	0	1
			==> MISSING_ELSE
193	0	1
194	0	1
197	0	1
199	0	1
205	0	1
206	0	1
			==> MISSING_ELSE
209	0	1
210	0	1
			==> MISSING_ELSE
218	0	1
219	0	1
220	0	1
221	0	1
222	0	1
			==> MISSING_ELSE
231	0	1
233	0	1
236	0	1
237	0	1
238	0	1
239	0	1
			==> MISSING_ELSE
242	0	1
243	0	1
244	0	1
245	0	1
253	0	1
254	0	1
255	0	1
258	0	1
260	0	1
266	0	1
267	0	1
			==> MISSING_ELSE
270	0	1
271	0	1
273	0	1
			==> MISSING_ELSE
282	0	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
287	0	1
288	0	1
289	0	1
290	0	1
291	0	1
292	0	1
			==> MISSING_ELSE
308	0	1
309	0	1
310	0	1
311	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
315	0	1
316	0	1
317	0	1
318	0	1
319	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
328	0	1
330	0	1
335	0	1
336	0	1
340	0	1
344	0	1
371	0	1
396	0	1
430	0	1
437	0	3
440	0	1
441	0	1
442	0	1
443	0	1
445	0	1
446	0	1
447	0	1
448	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	0	0.00
Logical	35	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Not Covered
IdleSt	199	Not Covered
InitSt	175	Not Covered
InitWaitSt	185	Not Covered
ReadSt	221	Not Covered
ReadWaitSt	239	Not Covered
ResetSt	173	Not Covered

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Not Covered
IdleSt->ReadSt	221	Not Covered
InitSt->ErrorSt	309	Not Covered
InitSt->InitWaitSt	185	Not Covered
InitWaitSt->ErrorSt	209	Not Covered
InitWaitSt->IdleSt	199	Not Covered
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Not Covered
ReadSt->ReadWaitSt	239	Not Covered
ReadWaitSt->ErrorSt	270	Not Covered
ReadWaitSt->IdleSt	260	Not Covered
ResetSt->ErrorSt	309	Not Covered
ResetSt->InitSt	175	Not Covered

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	11	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Not Covered
CheckFailError	311	Not Covered
FsmStateError	283	Not Covered
MacroEccCorrError	206	Not Covered
NoError	220	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Not Covered
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Not Covered
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Not Covered
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Not Covered
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Not Covered
MacroEccCorrError->NoError	220	Not Covered
NoError->AccessError	243	Not Covered
NoError->CheckFailError	311	Not Covered
NoError->FsmStateError	283	Not Covered
NoError->MacroEccCorrError	206	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	0	0.00
TERNARY	330	2	0	0.00
TERNARY	335	2	0	0.00
TERNARY	344	2	0	0.00
TERNARY	371	2	0	0.00
TERNARY	396	2	0	0.00
CASE	169	23	0	0.00
IF	308	3	0	0.00
IF	315	3	0	0.00
IF	437	2	0	0.00
IF	440	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		87	0	0.00
CONT_ASSIGN	137	1	0	0.00
ALWAYS	147	66	0	0.00
CONT_ASSIGN	328	1	0	0.00
CONT_ASSIGN	330	1	0	0.00
CONT_ASSIGN	335	1	0	0.00
CONT_ASSIGN	336	1	0	0.00
CONT_ASSIGN	340	1	0	0.00
CONT_ASSIGN	344	1	0	0.00
CONT_ASSIGN	371	1	0	0.00
CONT_ASSIGN	396	1	0	0.00
CONT_ASSIGN	430	1	0	0.00
ALWAYS	437	3	0	0.00
ALWAYS	440	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	0	1
147	0	1
150	0	1
153	0	1
154	0	1
157	0	1
158	0	1
159	0	1
162	0	1
165	0	1
166	0	1
167	0	1
169	0	1
174	0	1
175	0	1
			==> MISSING_ELSE
183	0	1
184	0	1
185	0	1
			==> MISSING_ELSE
193	0	1
194	0	1
197	0	1
199	0	1
205	0	1
206	0	1
			==> MISSING_ELSE
209	0	1
210	0	1
			==> MISSING_ELSE
218	0	1
219	0	1
220	0	1
221	0	1
222	0	1
			==> MISSING_ELSE
231	0	1
233	0	1
236	0	1
237	0	1
238	0	1
239	0	1
			==> MISSING_ELSE
242	0	1
243	0	1
244	0	1
245	0	1
253	0	1
254	0	1
255	0	1
258	0	1
260	0	1
266	0	1
267	0	1
			==> MISSING_ELSE
270	0	1
271	0	1
273	0	1
			==> MISSING_ELSE
282	0	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
287	0	1
288	0	1
289	0	1
290	0	1
291	0	1
292	0	1
			==> MISSING_ELSE
308	0	1
309	0	1
310	0	1
311	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
315	0	1
316	0	1
317	0	1
318	0	1
319	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
328	0	1
330	0	1
335	0	1
336	0	1
340	0	1
344	0	1
371	0	1
396	0	1
430	0	1
437	0	3
440	0	1
441	0	1
442	0	1
443	0	1
445	0	1
446	0	1
447	0	1
448	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	0	0.00
Logical	35	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Not Covered
IdleSt	199	Not Covered
InitSt	175	Not Covered
InitWaitSt	185	Not Covered
ReadSt	221	Not Covered
ReadWaitSt	239	Not Covered
ResetSt	173	Not Covered

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Not Covered
IdleSt->ReadSt	221	Not Covered
InitSt->ErrorSt	309	Not Covered
InitSt->InitWaitSt	185	Not Covered
InitWaitSt->ErrorSt	209	Not Covered
InitWaitSt->IdleSt	199	Not Covered
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Not Covered
ReadSt->ReadWaitSt	239	Not Covered
ReadWaitSt->ErrorSt	270	Not Covered
ReadWaitSt->IdleSt	260	Not Covered
ResetSt->ErrorSt	309	Not Covered
ResetSt->InitSt	175	Not Covered

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	11	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Not Covered
CheckFailError	311	Not Covered
FsmStateError	283	Not Covered
MacroEccCorrError	206	Not Covered
NoError	220	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Not Covered
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Not Covered
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Not Covered
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Not Covered
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Not Covered
MacroEccCorrError->NoError	220	Not Covered
NoError->AccessError	243	Not Covered
NoError->CheckFailError	311	Not Covered
NoError->FsmStateError	283	Not Covered
NoError->MacroEccCorrError	206	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	0	0.00
TERNARY	330	2	0	0.00
TERNARY	335	2	0	0.00
TERNARY	344	2	0	0.00
TERNARY	371	2	0	0.00
TERNARY	396	2	0	0.00
CASE	169	23	0	0.00
IF	308	3	0	0.00
IF	315	3	0	0.00
IF	437	2	0	0.00
IF	440	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Not Covered
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered