OTP_CTRL Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: `0c759b93ab`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.980s	118.372us	1	1	100.00
V1	smoke	otp_ctrl_smoke	12.280s	4.212ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.770s	932.152us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.090s	606.375us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.720s	537.624us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	4.430s	417.519us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.020s	402.951us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.090s	606.375us	20	20	100.00
		otp_ctrl_csr_aliasing	4.430s	417.519us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.980s	545.960us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.300s	36.521us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	17.930s	816.319us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.740s	2.504ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	27.680s	6.938ms	10	10	100.00
		otp_ctrl_check_fail	34.420s	3.645ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	9.470s	3.583ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	30.330s	10.124ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	40.780s	1.854ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	25.920s	9.225ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	13.540s	5.645ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	16.330s	6.692ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	43.220s	3.794ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.849m	28.934ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	3.358m	123.669ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	2.180s	601.970us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.350s	563.349us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.380s	662.418us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.380s	662.418us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.770s	932.152us	5	5	100.00
		otp_ctrl_csr_rw	2.090s	606.375us	20	20	100.00
		otp_ctrl_csr_aliasing	4.430s	417.519us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.400s	928.647us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.770s	932.152us	5	5	100.00
		otp_ctrl_csr_rw	2.090s	606.375us	20	20	100.00
		otp_ctrl_csr_aliasing	4.430s	417.519us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.400s	928.647us	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
		otp_ctrl_tl_intg_err	37.700s	18.932ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	37.700s	18.932ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	12.280s	4.212ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	12.280s	4.212ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.540s	5.645ms	200	200	100.00
		otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.540s	5.645ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.540s	5.645ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.540s	5.645ms	200	200	100.00
		otp_ctrl_macro_errs	43.220s	3.794ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.540s	5.645ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.540s	5.645ms	200	200	100.00
		otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.540s	5.645ms	200	200	100.00
		otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.540s	5.645ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.540s	5.645ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.540s	5.645ms	200	200	100.00
		otp_ctrl_macro_errs	43.220s	3.794ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.540s	5.645ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.540s	5.645ms	200	200	100.00
		otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.740s	2.504ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	34.420s	3.645ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	30.330s	10.124ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	30.330s	10.124ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	30.330s	10.124ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	30.330s	10.124ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	30.330s	10.124ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	12.280s	4.212ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	30.330s	10.124ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	12.280s	4.212ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.262m	139.284ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	9.470s	3.583ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	12.280s	4.212ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	12.280s	4.212ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	43.220s	3.794ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	19.560s	7.301ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.799h	5.013s	91	100	91.00
V3		TOTAL			92	101	91.09
		TOTAL			1332	1343	99.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.37	92.57	90.98	92.29	92.68	93.28	96.53	95.27

Failure Buckets

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 9.otp_ctrl_stress_all_with_rand_reset.29204070606485368303775391156651554136500655696324405844660697855179807858177
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:69f3856e-a56a-48e6-a99f-d470a730fb80
```
  - 28.otp_ctrl_stress_all_with_rand_reset.30792483313382044063294902674040333368084694123273025424171509080881404153202
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:9b826b20-41a4-46a0-96b5-7a0c6ae712eb
```
  - ... and 4 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 4.otp_ctrl_csr_mem_rw_with_rand_reset.42245849848512104267082336923075362127353966076442761817946503611162073930697
    Line 272, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 122875576 ps: (otp_ctrl_if.sv:262) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 122875576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 34.otp_ctrl_stress_all_with_rand_reset.88141872141367285829208017742151556593808558614643530952712297939542392272187
    Line 653, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 467908820194 ps: (otp_ctrl_if.sv:262) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 467908820194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@694830) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all has 1 failures.

29.otp_ctrl_stress_all.3178311345374264282466881687864523000466838390980106502940596749607796105078
Line 286, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 21482798226 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@694830) { a_addr: 'heef4b24c  a_data: 'h41f4d2ed  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5b  a_opcode: 'h1  a_user: 'h27786  d_param: 'h0  d_source: 'h5b  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 21482798226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@63940963) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 35.otp_ctrl_stress_all_with_rand_reset.75888294646311079610275586022616875178341108603568158012462854170926985216229
    Line 2168, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 368414179972 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@63940963) { a_addr: 'hb7db66dc  a_data: 'hd4cc06d3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hbc  a_opcode: 'h0  a_user: 'h27606  d_param: 'h0  d_source: 'hbc  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 368414179972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 53.otp_ctrl_stress_all_with_rand_reset.22268839325331497378740061892300481087671878038805249089607703897390484257981
    Line 505, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 64384840100 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 64384840100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```