Assert Coverage for Module :
otp_ctrl_core_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1910540985 |
18713551 |
0 |
0 |
T114 |
5238 |
163 |
0 |
0 |
T115 |
4491 |
0 |
0 |
0 |
T116 |
5356 |
0 |
0 |
0 |
T117 |
4470 |
0 |
0 |
0 |
T118 |
4114 |
0 |
0 |
0 |
T119 |
3570 |
0 |
0 |
0 |
T120 |
3728 |
0 |
0 |
0 |
T121 |
10860 |
0 |
0 |
0 |
T183 |
6893 |
97 |
0 |
0 |
T184 |
6847 |
549 |
0 |
0 |
T185 |
0 |
123 |
0 |
0 |
T186 |
0 |
418 |
0 |
0 |
T187 |
0 |
48 |
0 |
0 |
T188 |
0 |
13 |
0 |
0 |
T189 |
0 |
29 |
0 |
0 |
T190 |
0 |
265 |
0 |
0 |
T208 |
0 |
6 |
0 |
0 |
check_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1910540985 |
4059 |
0 |
0 |
T121 |
10860 |
16 |
0 |
0 |
T122 |
12323 |
0 |
0 |
0 |
T123 |
6309 |
1 |
0 |
0 |
T185 |
8398 |
0 |
0 |
0 |
T186 |
12504 |
0 |
0 |
0 |
T187 |
6703 |
4 |
0 |
0 |
T208 |
109884 |
0 |
0 |
0 |
T210 |
0 |
9 |
0 |
0 |
T228 |
0 |
15 |
0 |
0 |
T230 |
0 |
8 |
0 |
0 |
T232 |
0 |
12 |
0 |
0 |
T242 |
3640 |
0 |
0 |
0 |
T243 |
3167 |
0 |
0 |
0 |
T262 |
0 |
32 |
0 |
0 |
T263 |
0 |
5 |
0 |
0 |
T264 |
0 |
17 |
0 |
0 |
T265 |
3572 |
0 |
0 |
0 |
check_timeout_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1910540985 |
4134 |
0 |
0 |
T121 |
10860 |
35 |
0 |
0 |
T122 |
12323 |
0 |
0 |
0 |
T123 |
6309 |
50 |
0 |
0 |
T185 |
8398 |
0 |
0 |
0 |
T186 |
12504 |
0 |
0 |
0 |
T187 |
6703 |
0 |
0 |
0 |
T188 |
0 |
7 |
0 |
0 |
T208 |
109884 |
0 |
0 |
0 |
T228 |
0 |
2 |
0 |
0 |
T230 |
0 |
1 |
0 |
0 |
T242 |
3640 |
0 |
0 |
0 |
T243 |
3167 |
0 |
0 |
0 |
T262 |
0 |
70 |
0 |
0 |
T264 |
0 |
7 |
0 |
0 |
T265 |
3572 |
0 |
0 |
0 |
T266 |
0 |
7 |
0 |
0 |
T267 |
0 |
29 |
0 |
0 |
T268 |
0 |
18 |
0 |
0 |
check_trigger_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1910540985 |
3969 |
0 |
0 |
T118 |
4114 |
6 |
0 |
0 |
T120 |
3728 |
4 |
0 |
0 |
T121 |
10860 |
32 |
0 |
0 |
T122 |
12323 |
0 |
0 |
0 |
T123 |
6309 |
5 |
0 |
0 |
T185 |
8398 |
0 |
0 |
0 |
T186 |
12504 |
0 |
0 |
0 |
T187 |
6703 |
13 |
0 |
0 |
T188 |
0 |
3 |
0 |
0 |
T208 |
109884 |
0 |
0 |
0 |
T210 |
0 |
4 |
0 |
0 |
T228 |
0 |
2 |
0 |
0 |
T230 |
0 |
18 |
0 |
0 |
T242 |
3640 |
0 |
0 |
0 |
T262 |
0 |
50 |
0 |
0 |
consistency_check_period_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1910540985 |
4736 |
0 |
0 |
T118 |
4114 |
8 |
0 |
0 |
T120 |
3728 |
4 |
0 |
0 |
T121 |
10860 |
67 |
0 |
0 |
T122 |
12323 |
0 |
0 |
0 |
T123 |
6309 |
37 |
0 |
0 |
T185 |
8398 |
0 |
0 |
0 |
T186 |
12504 |
0 |
0 |
0 |
T187 |
6703 |
7 |
0 |
0 |
T188 |
0 |
6 |
0 |
0 |
T208 |
109884 |
0 |
0 |
0 |
T210 |
0 |
4 |
0 |
0 |
T228 |
0 |
15 |
0 |
0 |
T230 |
0 |
49 |
0 |
0 |
T242 |
3640 |
0 |
0 |
0 |
T262 |
0 |
37 |
0 |
0 |
creator_sw_cfg_read_lock_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1910540985 |
4381 |
0 |
0 |
T121 |
10860 |
51 |
0 |
0 |
T122 |
12323 |
0 |
0 |
0 |
T123 |
6309 |
29 |
0 |
0 |
T185 |
8398 |
0 |
0 |
0 |
T186 |
12504 |
0 |
0 |
0 |
T187 |
6703 |
0 |
0 |
0 |
T208 |
109884 |
0 |
0 |
0 |
T210 |
0 |
1 |
0 |
0 |
T228 |
0 |
7 |
0 |
0 |
T230 |
0 |
42 |
0 |
0 |
T242 |
3640 |
0 |
0 |
0 |
T243 |
3167 |
0 |
0 |
0 |
T262 |
0 |
62 |
0 |
0 |
T263 |
0 |
9 |
0 |
0 |
T264 |
0 |
3 |
0 |
0 |
T265 |
3572 |
0 |
0 |
0 |
T267 |
0 |
62 |
0 |
0 |
T268 |
0 |
24 |
0 |
0 |
direct_access_address_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1910540985 |
3700 |
0 |
0 |
T12 |
0 |
141 |
0 |
0 |
T33 |
0 |
74 |
0 |
0 |
T210 |
6823 |
1 |
0 |
0 |
T224 |
14285 |
0 |
0 |
0 |
T230 |
5680 |
0 |
0 |
0 |
T241 |
0 |
109 |
0 |
0 |
T247 |
0 |
4 |
0 |
0 |
T262 |
9394 |
0 |
0 |
0 |
T263 |
6377 |
2 |
0 |
0 |
T264 |
0 |
16 |
0 |
0 |
T269 |
0 |
2 |
0 |
0 |
T270 |
0 |
5 |
0 |
0 |
T271 |
0 |
55 |
0 |
0 |
T272 |
3703 |
0 |
0 |
0 |
T273 |
3712 |
0 |
0 |
0 |
T274 |
4559 |
0 |
0 |
0 |
T275 |
3595 |
0 |
0 |
0 |
T276 |
3681 |
0 |
0 |
0 |
direct_access_wdata_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1910540985 |
2615 |
0 |
0 |
T12 |
393152 |
94 |
0 |
0 |
T13 |
232981 |
0 |
0 |
0 |
T25 |
10655 |
0 |
0 |
0 |
T33 |
119248 |
22 |
0 |
0 |
T70 |
17001 |
0 |
0 |
0 |
T94 |
463639 |
0 |
0 |
0 |
T95 |
513147 |
0 |
0 |
0 |
T168 |
13008 |
0 |
0 |
0 |
T241 |
0 |
127 |
0 |
0 |
T271 |
0 |
12 |
0 |
0 |
T277 |
0 |
43 |
0 |
0 |
T278 |
0 |
31 |
0 |
0 |
T279 |
0 |
94 |
0 |
0 |
T280 |
0 |
210 |
0 |
0 |
T281 |
0 |
131 |
0 |
0 |
T282 |
0 |
71 |
0 |
0 |
T283 |
11071 |
0 |
0 |
0 |
T284 |
5401 |
0 |
0 |
0 |
direct_access_wdata_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1910540985 |
3294 |
0 |
0 |
T12 |
393152 |
136 |
0 |
0 |
T13 |
232981 |
0 |
0 |
0 |
T25 |
10655 |
0 |
0 |
0 |
T33 |
119248 |
18 |
0 |
0 |
T70 |
17001 |
0 |
0 |
0 |
T94 |
463639 |
0 |
0 |
0 |
T95 |
513147 |
0 |
0 |
0 |
T168 |
13008 |
0 |
0 |
0 |
T241 |
0 |
82 |
0 |
0 |
T271 |
0 |
20 |
0 |
0 |
T277 |
0 |
61 |
0 |
0 |
T278 |
0 |
11 |
0 |
0 |
T279 |
0 |
103 |
0 |
0 |
T280 |
0 |
305 |
0 |
0 |
T281 |
0 |
153 |
0 |
0 |
T282 |
0 |
99 |
0 |
0 |
T283 |
11071 |
0 |
0 |
0 |
T284 |
5401 |
0 |
0 |
0 |
integrity_check_period_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1910540985 |
4133 |
0 |
0 |
T118 |
4114 |
7 |
0 |
0 |
T120 |
3728 |
0 |
0 |
0 |
T121 |
10860 |
40 |
0 |
0 |
T122 |
12323 |
0 |
0 |
0 |
T123 |
6309 |
51 |
0 |
0 |
T185 |
8398 |
0 |
0 |
0 |
T186 |
12504 |
0 |
0 |
0 |
T187 |
6703 |
3 |
0 |
0 |
T188 |
0 |
2 |
0 |
0 |
T208 |
109884 |
0 |
0 |
0 |
T210 |
0 |
1 |
0 |
0 |
T228 |
0 |
26 |
0 |
0 |
T230 |
0 |
16 |
0 |
0 |
T242 |
3640 |
0 |
0 |
0 |
T262 |
0 |
35 |
0 |
0 |
T263 |
0 |
4 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1910540985 |
5149 |
0 |
0 |
T18 |
3702 |
17 |
0 |
0 |
T114 |
5238 |
0 |
0 |
0 |
T115 |
4491 |
0 |
0 |
0 |
T116 |
5356 |
0 |
0 |
0 |
T117 |
4470 |
0 |
0 |
0 |
T118 |
4114 |
6 |
0 |
0 |
T119 |
3570 |
0 |
0 |
0 |
T120 |
3728 |
1 |
0 |
0 |
T121 |
0 |
35 |
0 |
0 |
T123 |
0 |
20 |
0 |
0 |
T183 |
6893 |
0 |
0 |
0 |
T184 |
6847 |
0 |
0 |
0 |
T187 |
0 |
4 |
0 |
0 |
T188 |
0 |
4 |
0 |
0 |
T228 |
0 |
38 |
0 |
0 |
T265 |
0 |
7 |
0 |
0 |
T285 |
0 |
17 |
0 |
0 |
owner_sw_cfg_read_lock_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1910540985 |
3750 |
0 |
0 |
T121 |
10860 |
34 |
0 |
0 |
T122 |
12323 |
0 |
0 |
0 |
T123 |
6309 |
6 |
0 |
0 |
T185 |
8398 |
0 |
0 |
0 |
T186 |
12504 |
0 |
0 |
0 |
T187 |
6703 |
0 |
0 |
0 |
T208 |
109884 |
0 |
0 |
0 |
T210 |
0 |
2 |
0 |
0 |
T228 |
0 |
52 |
0 |
0 |
T230 |
0 |
25 |
0 |
0 |
T242 |
3640 |
0 |
0 |
0 |
T243 |
3167 |
0 |
0 |
0 |
T262 |
0 |
56 |
0 |
0 |
T263 |
0 |
4 |
0 |
0 |
T264 |
0 |
9 |
0 |
0 |
T265 |
3572 |
0 |
0 |
0 |
T267 |
0 |
49 |
0 |
0 |
T268 |
0 |
11 |
0 |
0 |
vendor_test_read_lock_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1910540985 |
3659 |
0 |
0 |
T121 |
10860 |
24 |
0 |
0 |
T122 |
12323 |
0 |
0 |
0 |
T123 |
6309 |
23 |
0 |
0 |
T185 |
8398 |
0 |
0 |
0 |
T186 |
12504 |
0 |
0 |
0 |
T187 |
6703 |
4 |
0 |
0 |
T188 |
0 |
2 |
0 |
0 |
T208 |
109884 |
0 |
0 |
0 |
T228 |
0 |
22 |
0 |
0 |
T230 |
0 |
7 |
0 |
0 |
T242 |
3640 |
0 |
0 |
0 |
T243 |
3167 |
0 |
0 |
0 |
T262 |
0 |
69 |
0 |
0 |
T263 |
0 |
4 |
0 |
0 |
T264 |
0 |
11 |
0 |
0 |
T265 |
3572 |
0 |
0 |
0 |
T267 |
0 |
19 |
0 |
0 |