Unified Coverage Report :: Module :: otp_ctrl

Module : otp_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.72	97.18	88.57	95.90		96.97	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	95.90	97.18	88.57	96.76		96.97	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.90	97.18	88.57	96.76		96.97	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.22	92.55	91.52	92.59	92.68	93.44	96.53

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
core_tlul_assert_device	100.00	100.00				100.00	100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_alert_tx[2].u_prim_alert_sender	100.00			100.00
gen_alert_tx[3].u_prim_alert_sender	100.00			100.00
gen_alert_tx[4].u_prim_alert_sender	77.78			77.78
gen_bufs[0].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[0].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_partitions[0].gen_unbuffered.u_part_unbuf	94.53	98.44	95.74	97.87	83.33	94.64	97.14
gen_partitions[1].gen_unbuffered.u_part_unbuf	98.26	100.00	100.00	97.87	91.67	100.00	100.00
gen_partitions[2].gen_unbuffered.u_part_unbuf	98.26	100.00	100.00	97.87	91.67	100.00	100.00
gen_partitions[3].gen_buffered.u_part_buf	87.50	84.80	86.79	93.78	93.10	80.49	86.05
gen_partitions[4].gen_buffered.u_part_buf	92.46	93.87	86.44	94.30	97.22	87.36	95.56
gen_partitions[5].gen_buffered.u_part_buf	91.44	93.87	86.44	93.73	91.67	87.36	95.56
gen_partitions[6].gen_buffered.u_part_buf	91.90	93.87	86.44	93.73	94.44	87.36	95.56
gen_partitions[7].gen_lifecycle.u_part_buf	80.09	71.86	77.42	74.10	95.24	76.56	85.37
otp_ctrl_core_csr_assert	100.00						100.00
prim_tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_arb	92.49	92.31	84.31			100.00	93.33
u_intr_error	100.00	100.00	100.00			100.00	100.00
u_intr_operation_done	100.00	100.00	100.00			100.00	100.00
u_keygmr_key_valid	100.00	100.00				100.00
u_otp	96.17	91.72	94.58	100.00	100.00	90.71	100.00
u_otp_arb	94.34	93.01	90.61			100.00	93.75
u_otp_ctrl_dai	91.68	90.73	93.06	100.00	89.47	90.43	86.36
u_otp_ctrl_kdi	96.34	98.43	96.90	100.00	90.91	94.44	97.37
u_otp_ctrl_lci	100.00	100.00	100.00	100.00	100.00	100.00	100.00
u_otp_ctrl_lfsr_timer	97.05	100.00	96.25	86.06	100.00	100.00	100.00
u_otp_ctrl_scrmbl	96.62	81.50	100.00	100.00	100.00	98.21	100.00
u_otp_init_sync	100.00	100.00				100.00
u_otp_rsp_fifo	94.70	100.00	78.79			100.00	100.00
u_part_sel_idx	82.27	76.81	98.44			100.00	53.85
u_prim_edn_req	92.19	100.00	93.75			100.00	75.00
u_prim_lc_sender_rma_token_valid	100.00	100.00				100.00
u_prim_lc_sender_secrets_valid	100.00	100.00				100.00
u_prim_lc_sender_test_tokens_valid	100.00	100.00				100.00
u_prim_lc_sync_check_byp_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_creator_seed_sw_rw_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_escalate_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_seed_hw_rd_en	100.00	100.00				100.00	100.00
u_reg_core	99.28	99.59	96.83	100.00		100.00	100.00
u_scrmbl_mtx	76.66	83.33	79.54			100.00	43.75
u_tlul_adapter_sram	91.72	89.54	84.55			92.77	100.00
u_tlul_lc_gate	93.35	99.24	100.00		85.71	94.29	87.50

Line Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
TOTAL		142	138	97.18
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
ALWAYS	265	14	13	92.86
ALWAYS	289	3	3	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
ALWAYS	320	11	11	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
ALWAYS	399	3	3	100.00
ALWAYS	421	20	20	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
ALWAYS	499	9	9	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	607	1	1	100.00
CONT_ASSIGN	730	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
ALWAYS	841	2	2	100.00
ALWAYS	899	2	2	100.00
ALWAYS	926	4	4	100.00
CONT_ASSIGN	953	1	1	100.00
ALWAYS	956	3	3	100.00
CONT_ASSIGN	1008	1	1	100.00
CONT_ASSIGN	1010	1	1	100.00
CONT_ASSIGN	1044	1	1	100.00
CONT_ASSIGN	1095	1	0	0.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1205	1	1	100.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1205	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1301	1	1	100.00
CONT_ASSIGN	1304	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1311	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1335	1	1	100.00
CONT_ASSIGN	1337	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1343	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1347	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
CONT_ASSIGN	1354	1	1	100.00
CONT_ASSIGN	1356	1	1	100.00
CONT_ASSIGN	1388	1	1	100.00
CONT_ASSIGN	1390	1	1	100.00
CONT_ASSIGN	1394	1	1	100.00
CONT_ASSIGN	1398	1	1	100.00
CONT_ASSIGN	1402	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
235	8	8
265	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
273	0	1
			MISSING_ELSE
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
289	1	1
290	1	1
292	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
310	1	1
320	1	1
324	1	1
325	1	1
329	1	1
330	1	1
			MISSING_ELSE
332	1	1
333	1	1
			MISSING_ELSE
335	1	1
336	1	1
			MISSING_ELSE
339	1	1
340	1	1
			MISSING_ELSE
375	1	1
379	1	1
383	1	1
384	1	1
385	1	1
387	1	1
395	1	1
396	1	1
399	1	1
400	1	1
402	1	1
421	1	1
424	1	1
425	1	1
426	1	1
428	1	1
430	1	1
433	1	1
435	1	1
438	1	1
439	1	1
			MISSING_ELSE
443	1	1
445	1	1
449	1	1
452	1	1
454	1	1
459	1	1
460	1	1
			MISSING_ELSE
462	1	1
463	1	1
			MISSING_ELSE
468	1	1
475	1	1
488	1	1
496	1	1
499	1	1
500	1	1
501	1	1
502	1	1
503	1	1
505	1	1
506	1	1
507	1	1
508	1	1
550	1	1
558	1	1
605	1	1
607	1	1
730	1	1
731	1	1
732	1	1
762	1	1
764	1	1
841	1	1
842	1	1
899	1	1
900	1	1
926	1	1
927	1	1
928	1	1
929	1	1
953	1	1
956	1	1
957	1	1
959	1	1
1008	1	1
1010	1	1
1044	1	1
1095	0	1
1150	3	3
1205	2	4
1265	1	1
1277	1	1
1300	1	1
1301	1	1
1304	1	1
1305	1	1
1306	1	1
1311	1	1
1334	1	1
1335	1	1
1337	1	1
1339	1	1
1343	1	1
1345	1	1
1347	1	1
1352	1	1
1354	1	1
1356	1	1
1388	1	1
1390	1	1
1394	1	1
1398	1	1
1402	1	1

---

Cond Coverage for Module : otp_ctrl

	Total	Covered	Percent
Conditions	105	93	88.57
Logical	105	93	88.57
Non-Logical	0	0
Event	0	0

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b0) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[0].PartEnd))
             --------------1-------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b01101100000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T13,T14
1	1	Covered	T1,T2,T3

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11010000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T12,T13,T14

 LINE       269
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       278
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       279
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       375
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       395
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Not Covered

 LINE       435
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       439
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       459
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T11
1	0	Covered	T2,T4,T6

 LINE       468
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T4,T6
0	0	1	0	Covered	T21,T22,T23
0	1	0	0	Covered	T21,T22,T23
1	0	0	0	Covered	T57,T35,T12

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T206,T207
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T206,T207

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T206,T207
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T206,T207

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T206,T207
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T206,T207

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T206,T207
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T206,T207

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T206,T207
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T206,T207

 LINE       605
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       607
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       730
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       731
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       732
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       842
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1300
 EXPRESSION (part_init_done[HwCfgIdx] ? On : Off)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1304
 EXPRESSION (part_digest[Secret2Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1334
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       1352
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T11

 LINE       1352
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T11

 LINE       1354
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1354
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1356
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1356
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Module : otp_ctrl

	Total	Covered	Percent
Totals	145	135	93.10
Total Bits	9412	9026	95.90
Total Bits 0->1	4706	4513	95.90
Total Bits 1->0	4706	4513	95.90

Ports	145	135	93.10
Port Bits	9412	9026	95.90
Port Bits 0->1	4706	4513	95.90
Port Bits 1->0	4706	4513	95.90

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
rst_ni	Yes	Yes	T121,T187,T208	Yes	T18,T114,T115	INPUT
clk_edn_i	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
rst_edn_ni	Yes	Yes	T121,T187,T208	Yes	T18,T114,T115	INPUT
edn_o.edn_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i.edn_fips	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
core_tl_i.d_ready	Yes	Yes	T18,T183,T118	Yes	T18,T114,T115	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T18,T114,T117	Yes	T18,T114,T117	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_valid	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_o.a_ready	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
core_tl_o.d_error	Yes	Yes	T114,T183,T184	Yes	T114,T183,T184	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T115,T116	Yes	T18,T115,T116	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T18,T114,*T115	Yes	T18,T114,T115	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T18,*T114,*T115	Yes	T18,T114,T115	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T18,T183,T118	Yes	T18,T114,T115	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T114,T116,T119	Yes	T114,T116,T183	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T114,T116,T183	Yes	T114,T116,T183	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T114,T116,T183	Yes	T114,T116,T119	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T114,T116,T183	Yes	T114,T116,T119	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	INPUT
prim_tl_i.a_valid	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	INPUT
prim_tl_o.a_ready	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
prim_tl_o.d_error	Yes	Yes	T18,T114,T115	Yes	T114,T183,T184	OUTPUT
prim_tl_o.d_user.data_intg[6:0]	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	OUTPUT
prim_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T114,T116,*T117	Yes	T114,T116,T117	OUTPUT
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T18,T114,T115	Yes	T114,T116,T117	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T114,T116,T183	Yes	T114,T116,T183	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T18,*T114,*T115	Yes	T114,T116,T117	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T18,T115,T119	Yes	T18,T115,T119	OUTPUT
intr_otp_error_o	Yes	Yes	T18,T115,T119	Yes	T18,T115,T119	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T117,T118,T121	Yes	T117,T118,T121	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T117,T118,T121	Yes	T117,T118,T121	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T117,T118,T121	Yes	T117,T118,T121	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T117,T118,T121	Yes	T117,T118,T121	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	No	No		No		OUTPUT
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T121,T208,T188	Yes	T187,T208,T209	INPUT
pwr_otp_i.otp_init	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T121,T187,T208	Yes	T18,T114,T115	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T121,T187,T208	Yes	T18,T114,T115	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	No	No		No		OUTPUT
lc_otp_program_i.count[383:0]	Yes	Yes	T35,T94,T13	Yes	T35,T94,T13	INPUT
lc_otp_program_i.state[319:0]	Yes	Yes	T35,T94,T13	Yes	T35,T94,T13	INPUT
lc_otp_program_i.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_otp_program_o.ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
lc_otp_program_o.err	Yes	Yes	T35,T94,T13	Yes	T35,T94,T13	OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T121,T208,T188	Yes	T208,T189,T209	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T187,T208,T188	Yes	T18,T114,T115	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T3,T11,T109	Yes	T3,T11,T109	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
otp_lc_data_o.rma_token[127:0]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T1,T2,T15	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_exit_token[127:0]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T1,T11,T94	Yes	T1,T3,T9	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T1,T11,T15	Yes	T1,T9,T11	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T1,T2,T15	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[3:0]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[4]	No	No		No		OUTPUT
otp_lc_data_o.count[14:5]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[15]	No	No		No		OUTPUT
otp_lc_data_o.count[27:16]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[32:28]	No	No		No		OUTPUT
otp_lc_data_o.count[41:33]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[42]	No	No		No		OUTPUT
otp_lc_data_o.count[46:43]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[47]	No	No		No		OUTPUT
otp_lc_data_o.count[61:48]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[62]	No	No		No		OUTPUT
otp_lc_data_o.count[63]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[64]	No	No		No		OUTPUT
otp_lc_data_o.count[78:65]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[79]	No	No		No		OUTPUT
otp_lc_data_o.count[85:80]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[86]	No	No		No		OUTPUT
otp_lc_data_o.count[105:87]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[106]	No	No		No		OUTPUT
otp_lc_data_o.count[115:107]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[116]	No	No		No		OUTPUT
otp_lc_data_o.count[118:117]	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
otp_lc_data_o.count[119]	No	No		No		OUTPUT
otp_lc_data_o.count[124:120]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[125]	No	No		No		OUTPUT
otp_lc_data_o.count[134:126]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[135]	No	No		No		OUTPUT
otp_lc_data_o.count[138:136]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[139]	No	No		No		OUTPUT
otp_lc_data_o.count[151:140]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[153:152]	No	No		No		OUTPUT
otp_lc_data_o.count[159:154]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[160]	No	No		No		OUTPUT
otp_lc_data_o.count[164:161]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[165]	No	No		No		OUTPUT
otp_lc_data_o.count[174:166]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[176:175]	No	No		No		OUTPUT
otp_lc_data_o.count[180:177]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[181]	No	No		No		OUTPUT
otp_lc_data_o.count[186:182]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[187]	No	No		No		OUTPUT
otp_lc_data_o.count[194:188]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[195]	No	No		No		OUTPUT
otp_lc_data_o.count[196]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[197]	No	No		No		OUTPUT
otp_lc_data_o.count[198]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[199]	No	No		No		OUTPUT
otp_lc_data_o.count[207:200]	Yes	Yes	*T1,*T15,*T57	Yes	T1,T15,T57	OUTPUT
otp_lc_data_o.count[208]	No	No		No		OUTPUT
otp_lc_data_o.count[217:209]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[219:218]	No	No		No		OUTPUT
otp_lc_data_o.count[225:220]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[226]	No	No		No		OUTPUT
otp_lc_data_o.count[232:227]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[233]	No	No		No		OUTPUT
otp_lc_data_o.count[237:234]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[238]	No	No		No		OUTPUT
otp_lc_data_o.count[240:239]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[241]	No	No		No		OUTPUT
otp_lc_data_o.count[254:242]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[255]	No	No		No		OUTPUT
otp_lc_data_o.count[263:256]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[264]	No	No		No		OUTPUT
otp_lc_data_o.count[266:265]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[267]	No	No		No		OUTPUT
otp_lc_data_o.count[269:268]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[270]	No	No		No		OUTPUT
otp_lc_data_o.count[272:271]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[273]	No	No		No		OUTPUT
otp_lc_data_o.count[274]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[275]	No	No		No		OUTPUT
otp_lc_data_o.count[302:276]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[303]	No	No		No		OUTPUT
otp_lc_data_o.count[327:304]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[328]	No	No		No		OUTPUT
otp_lc_data_o.count[330:329]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[331]	No	No		No		OUTPUT
otp_lc_data_o.count[333:332]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[334]	No	No		No		OUTPUT
otp_lc_data_o.count[345:335]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[346]	No	No		No		OUTPUT
otp_lc_data_o.count[365:347]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[367:366]	No	No		No		OUTPUT
otp_lc_data_o.count[379:368]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[380]	No	No		No		OUTPUT
otp_lc_data_o.count[383:381]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[6]	No	No		No		OUTPUT
otp_lc_data_o.state[9:7]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[10]	No	No		No		OUTPUT
otp_lc_data_o.state[14:11]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[15]	No	No		No		OUTPUT
otp_lc_data_o.state[17:16]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[20:18]	No	No		No		OUTPUT
otp_lc_data_o.state[31:21]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[32]	No	No		No		OUTPUT
otp_lc_data_o.state[34:33]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[35]	No	No		No		OUTPUT
otp_lc_data_o.state[36]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[37]	No	No		No		OUTPUT
otp_lc_data_o.state[42:38]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[43]	No	No		No		OUTPUT
otp_lc_data_o.state[50:44]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[53:51]	No	No		No		OUTPUT
otp_lc_data_o.state[61:54]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[62]	No	No		No		OUTPUT
otp_lc_data_o.state[77:63]	Yes	Yes	*T2,*T4,*T15	Yes	T2,T4,T15	OUTPUT
otp_lc_data_o.state[78]	No	No		No		OUTPUT
otp_lc_data_o.state[79]	Yes	Yes	*T2,*T4,*T15	Yes	T2,T4,T15	OUTPUT
otp_lc_data_o.state[80]	No	No		No		OUTPUT
otp_lc_data_o.state[83:81]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[84]	No	No		No		OUTPUT
otp_lc_data_o.state[87:85]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[88]	No	No		No		OUTPUT
otp_lc_data_o.state[95:89]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[96]	No	No		No		OUTPUT
otp_lc_data_o.state[101:97]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[102]	No	No		No		OUTPUT
otp_lc_data_o.state[103]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[104]	No	No		No		OUTPUT
otp_lc_data_o.state[110:105]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[111]	No	No		No		OUTPUT
otp_lc_data_o.state[113:112]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[115:114]	No	No		No		OUTPUT
otp_lc_data_o.state[123:116]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[124]	No	No		No		OUTPUT
otp_lc_data_o.state[126:125]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[127]	No	No		No		OUTPUT
otp_lc_data_o.state[131:128]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[132]	No	No		No		OUTPUT
otp_lc_data_o.state[136:133]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[137]	No	No		No		OUTPUT
otp_lc_data_o.state[141:138]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[142]	No	No		No		OUTPUT
otp_lc_data_o.state[146:143]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[147]	No	No		No		OUTPUT
otp_lc_data_o.state[149:148]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[150]	No	No		No		OUTPUT
otp_lc_data_o.state[151]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[152]	No	No		No		OUTPUT
otp_lc_data_o.state[156:153]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[158:157]	No	No		No		OUTPUT
otp_lc_data_o.state[160:159]	Yes	Yes	*T1,T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[161]	No	No		No		OUTPUT
otp_lc_data_o.state[163:162]	Yes	Yes	*T1,T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[166:164]	No	No		No		OUTPUT
otp_lc_data_o.state[177:167]	Yes	Yes	*T2,*T15,*T57	Yes	T2,T4,T15	OUTPUT
otp_lc_data_o.state[178]	No	No		No		OUTPUT
otp_lc_data_o.state[180:179]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[182:181]	No	No		No		OUTPUT
otp_lc_data_o.state[186:183]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[187]	No	No		No		OUTPUT
otp_lc_data_o.state[198:188]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[200:199]	No	No		No		OUTPUT
otp_lc_data_o.state[210:201]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[211]	No	No		No		OUTPUT
otp_lc_data_o.state[217:212]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[218]	No	No		No		OUTPUT
otp_lc_data_o.state[219]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[220]	No	No		No		OUTPUT
otp_lc_data_o.state[243:221]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[244]	No	No		No		OUTPUT
otp_lc_data_o.state[250:245]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[251]	No	No		No		OUTPUT
otp_lc_data_o.state[273:252]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[274]	No	No		No		OUTPUT
otp_lc_data_o.state[279:275]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[280]	No	No		No		OUTPUT
otp_lc_data_o.state[294:281]	Yes	Yes	*T57,*T127,*T35	Yes	T57,T127,T35	OUTPUT
otp_lc_data_o.state[295]	No	No		No		OUTPUT
otp_lc_data_o.state[301:296]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[302]	No	No		No		OUTPUT
otp_lc_data_o.state[307:303]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[308]	No	No		No		OUTPUT
otp_lc_data_o.state[316:309]	Yes	Yes	*T57,*T35,*T102	Yes	T57,T35,T102	OUTPUT
otp_lc_data_o.state[317]	No	No		No		OUTPUT
otp_lc_data_o.state[319:318]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.error	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T121,T187,T208	Yes	T18,T114,T115	OUTPUT
otp_keymgr_key_o.key_share1[255:0]	Yes	Yes	T114,T116,T117	Yes	T121,T187,T208	OUTPUT
otp_keymgr_key_o.key_share0[255:0]	Yes	Yes	T102,T94,T98	Yes	T102,T94,T98	OUTPUT
otp_keymgr_key_o.valid	Yes	Yes	T1,T2,T15	Yes	T1,T2,T3	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
flash_otp_key_i.data_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
sram_otp_key_i[1].req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
sram_otp_key_i[2].req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
otp_hw_cfg_o.data.device_id[255:0]	Yes	Yes	T127,T94,T95	Yes	T127,T94,T95	OUTPUT
otp_hw_cfg_o.data.manuf_state[255:0]	Yes	Yes	T95,T101,T175	Yes	T95,T101,T175	OUTPUT
otp_hw_cfg_o.data.en_sram_ifetch[7:0]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_hw_cfg_o.data.en_csrng_sw_app_read[7:0]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_read[7:0]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[7:0]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_hw_cfg_o.data.unallocated[31:0]	Yes	Yes	T4,T15,T127	Yes	T4,T15,T127	OUTPUT
otp_hw_cfg_o.data.hw_cfg_digest[63:0]	Yes	Yes	T1,T15,T35	Yes	T1,T15,T35	OUTPUT
otp_hw_cfg_o.valid[3:0]	Yes	Yes	T121,T187,T208	Yes	T18,T114,T115	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T208,T191,T210	Yes	T208,T209,T211	INPUT
scan_rst_ni	Yes	Yes	T208,T188,T209	Yes	T208,T209,T211	INPUT
scanmode_i[3:0]	Yes	Yes	T208,T189,T191	Yes	T121,T208,T188	INPUT
cio_test_o[7:0]	No	No		No		OUTPUT
cio_test_en_o[7:0]	Yes	Yes	T121,T187,T208	Yes	T18,T114,T115	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
Branches		33	32	96.97
TERNARY	1300	2	2	100.00
TERNARY	1352	2	2	100.00
TERNARY	1354	2	2	100.00
TERNARY	1356	2	2	100.00
IF	268	3	2	66.67
IF	289	2	2	100.00
IF	329	2	2	100.00
IF	332	2	2	100.00
IF	335	2	2	100.00
IF	339	2	2	100.00
IF	399	2	2	100.00
IF	438	2	2	100.00
IF	459	2	2	100.00
IF	462	2	2	100.00
IF	499	2	2	100.00
IF	956	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1300	(part_init_done[HwCfgIdx]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1352	((part_digest[Secret0Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1354	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1356	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	if (tlul_req)
-2-:	269	if ((tlul_part_sel_oh != '0))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	329	if ((!reg2hw.vendor_test_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	332	if ((!reg2hw.creator_sw_cfg_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	if ((!reg2hw.owner_sw_cfg_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	339	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	399	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	438	if (otp_ctrl_part_pkg::PartInfo[k].ecc_fatal)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	459	if ((fatal_macro_error_q || fatal_check_error_q))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	462	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	499	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	956	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	64	64	100.00	64	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	64	64	100.00	64	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	1907808725	1906948445	0	0
CoreTlOutKnown_A	1907808725	1906948445	0	0
CreatorRootKeyShare0Size_A	1155	1155	0	0
CreatorRootKeyShare1Size_A	1155	1155	0	0
ErrorCodeWidth_A	1155	1155	0	0
FlashAddrKeySeedSize_A	1155	1155	0	0
FlashDataKeySeedSize_A	1155	1155	0	0
FlashOtpKeyRspKnown_A	1907808725	1906948445	0	0
FpvSecCmCntCnstyCheck_A	1907808725	50	0	0
FpvSecCmCntDaiCheck_A	1907808725	50	0	0
FpvSecCmCntIntegCheck_A	1907808725	50	0	0
FpvSecCmCntKdiEntropyCheck_A	1907808725	50	0	0
FpvSecCmCntKdiSeedCheck_A	1907808725	50	0	0
FpvSecCmCntLciCheck_A	1907808725	50	0	0
FpvSecCmCntScrmblCheck_A	1907808725	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	1907808725	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	1907808725	50	0	0
FpvSecCmCtrlLciFsmCheck_A	1907808725	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	1907808725	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	1907808725	50	0	0
FpvSecCmDoubleLfsrCheck_A	1907808725	50	0	0
FpvSecCmRegWeOnehotCheck_A	1907808725	50	0	0
FpvSecCmTlLcGateFsm_A	1907808725	50	0	0
IntrOtpErrorKnown_A	1907808725	1906948445	0	0
IntrOtpOperationDoneKnown_A	1907808725	1906948445	0	0
LcOtpProgramRspKnown_A	1907808725	1906948445	0	0
LcSeedHwRdEnStable_A	1907808725	2360	0	0
LcStateSize_A	1155	1155	0	0
LcTransitionCntSize_A	1155	1155	0	0
OtpAstPwrSeqKnown_A	1907808725	1906948445	0	0
OtpErrorCode0_A	1155	1155	0	0
OtpErrorCode1_A	1155	1155	0	0
OtpErrorCode2_A	1155	1155	0	0
OtpErrorCode3_A	1155	1155	0	0
OtpErrorCode4_A	1155	1155	0	0
OtpHwCfgKnown_A	1907808725	1906948445	0	0
OtpIfWidth_A	1155	1155	0	0
OtpKeymgrKeyKnown_A	1907808725	1906948445	0	0
OtpLcDataKnown_A	1907808725	1906948445	0	0
OtpOtgnKeyKnown_A	1907808725	1906948445	0	0
OtpRespFifoUnderflow_A	1907808725	1561281	0	0
OtpSramKeyKnown_A	1907808725	1906948445	0	0
PartSelMustBeOnehot_A	1907808725	1906948445	0	0
PrimTlOutKnown_A	1907808725	1906948445	0	0
PwrOtpInitRspKnown_A	1907808725	1906948445	0	0
RmaTokenSize_A	1155	1155	0	0
SramDataKeySeedSize_A	1155	1155	0	0
TestExitTokenSize_A	1155	1155	0	0
TestUnlockTokenSize_A	1155	1155	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1907808725	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1907808725	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1907808725	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A	1907808725	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1907808725	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A	1907808725	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1907808725	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	1907808725	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1907808725	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	1907808725	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1907808725	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A	1907808725	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	1907808725	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	1907808725	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	1907808725	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

LcSeedHwRdEnStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	2360	0	0
T1	74746	10	0	0
T2	85442	1	0	0
T3	16626	1	0	0
T4	29296	0	0	0
T6	10723	0	0	0
T7	8457	0	0	0
T8	12849	0	0	0
T9	8680	1	0	0
T10	11811	0	0	0
T11	39774	0	0	0
T15	0	3	0	0
T35	0	8	0	0
T93	0	6	0	0
T94	0	48	0	0
T102	0	8	0	0
T112	0	1	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpHwCfgKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1561281	0	0
T1	74746	1130	0	0
T2	85442	1694	0	0
T3	16626	193	0	0
T4	29296	629	0	0
T6	10723	127	0	0
T7	8457	132	0	0
T8	12849	137	0	0
T9	8680	172	0	0
T10	11811	197	0	0
T11	39774	285	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		142	138	97.18
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
ALWAYS	265	14	13	92.86
ALWAYS	289	3	3	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
ALWAYS	320	11	11	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
ALWAYS	399	3	3	100.00
ALWAYS	421	20	20	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
ALWAYS	499	9	9	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	607	1	1	100.00
CONT_ASSIGN	730	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
ALWAYS	841	2	2	100.00
ALWAYS	899	2	2	100.00
ALWAYS	926	4	4	100.00
CONT_ASSIGN	953	1	1	100.00
ALWAYS	956	3	3	100.00
CONT_ASSIGN	1008	1	1	100.00
CONT_ASSIGN	1010	1	1	100.00
CONT_ASSIGN	1044	1	1	100.00
CONT_ASSIGN	1095	1	0	0.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1205	1	1	100.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1205	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1301	1	1	100.00
CONT_ASSIGN	1304	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1311	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1335	1	1	100.00
CONT_ASSIGN	1337	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1343	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1347	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
CONT_ASSIGN	1354	1	1	100.00
CONT_ASSIGN	1356	1	1	100.00
CONT_ASSIGN	1388	1	1	100.00
CONT_ASSIGN	1390	1	1	100.00
CONT_ASSIGN	1394	1	1	100.00
CONT_ASSIGN	1398	1	1	100.00
CONT_ASSIGN	1402	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
235	8	8
265	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
273	0	1
			MISSING_ELSE
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
289	1	1
290	1	1
292	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
310	1	1
320	1	1
324	1	1
325	1	1
329	1	1
330	1	1
			MISSING_ELSE
332	1	1
333	1	1
			MISSING_ELSE
335	1	1
336	1	1
			MISSING_ELSE
339	1	1
340	1	1
			MISSING_ELSE
375	1	1
379	1	1
383	1	1
384	1	1
385	1	1
387	1	1
395	1	1
396	1	1
399	1	1
400	1	1
402	1	1
421	1	1
424	1	1
425	1	1
426	1	1
428	1	1
430	1	1
433	1	1
435	1	1
438	1	1
439	1	1
			MISSING_ELSE
443	1	1
445	1	1
449	1	1
452	1	1
454	1	1
459	1	1
460	1	1
			MISSING_ELSE
462	1	1
463	1	1
			MISSING_ELSE
468	1	1
475	1	1
488	1	1
496	1	1
499	1	1
500	1	1
501	1	1
502	1	1
503	1	1
505	1	1
506	1	1
507	1	1
508	1	1
550	1	1
558	1	1
605	1	1
607	1	1
730	1	1
731	1	1
732	1	1
762	1	1
764	1	1
841	1	1
842	1	1
899	1	1
900	1	1
926	1	1
927	1	1
928	1	1
929	1	1
953	1	1
956	1	1
957	1	1
959	1	1
1008	1	1
1010	1	1
1044	1	1
1095	0	1
1150	3	3
1205	2	4
1265	1	1
1277	1	1
1300	1	1
1301	1	1
1304	1	1
1305	1	1
1306	1	1
1311	1	1
1334	1	1
1335	1	1
1337	1	1
1339	1	1
1343	1	1
1345	1	1
1347	1	1
1352	1	1
1354	1	1
1356	1	1
1388	1	1
1390	1	1
1394	1	1
1398	1	1
1402	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	105	93	88.57
Logical	105	93	88.57
Non-Logical	0	0
Event	0	0

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b0) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[0].PartEnd))
             --------------1-------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b01101100000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T13,T14
1	1	Covered	T1,T2,T3

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11010000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T12,T13,T14

 LINE       269
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       278
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       279
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       375
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       395
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       426
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Not Covered

 LINE       435
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       439
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       459
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T11
1	0	Covered	T2,T4,T6

 LINE       468
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T2,T4,T6
0	0	1	0	Covered	T21,T22,T23
0	1	0	0	Covered	T21,T22,T23
1	0	0	0	Covered	T57,T35,T12

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T206,T207
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T206,T207

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T206,T207
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T206,T207

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T206,T207
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T206,T207

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T206,T207
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T206,T207

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T206,T207
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T206,T207

 LINE       605
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       607
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       730
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       731
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       732
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       842
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       1300
 EXPRESSION (part_init_done[HwCfgIdx] ? On : Off)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1304
 EXPRESSION (part_digest[Secret2Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1334
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       1352
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T11

 LINE       1352
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T11

 LINE       1354
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1354
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1356
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1356
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	141	134	95.04
Total Bits	9308	9006	96.76
Total Bits 0->1	4654	4503	96.76
Total Bits 1->0	4654	4503	96.76

Ports	141	134	95.04
Port Bits	9308	9006	96.76
Port Bits 0->1	4654	4503	96.76
Port Bits 1->0	4654	4503	96.76

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
rst_ni	Yes	Yes	T121,T187,T208	Yes	T18,T114,T115	INPUT
clk_edn_i	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
rst_edn_ni	Yes	Yes	T121,T187,T208	Yes	T18,T114,T115	INPUT
edn_o.edn_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i.edn_fips	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
core_tl_i.d_ready	Yes	Yes	T18,T183,T118	Yes	T18,T114,T115	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T18,T114,T117	Yes	T18,T114,T117	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_i.a_valid	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
core_tl_o.a_ready	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
core_tl_o.d_error	Yes	Yes	T114,T183,T184	Yes	T114,T183,T184	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T115,T116	Yes	T18,T115,T116	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T18,T114,*T115	Yes	T18,T114,T115	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T18,*T114,*T115	Yes	T18,T114,T115	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T18,T183,T118	Yes	T18,T114,T115	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T114,T116,T119	Yes	T114,T116,T183	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T114,T116,T183	Yes	T114,T116,T183	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T114,T116,T183	Yes	T114,T116,T119	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T114,T116,T183	Yes	T114,T116,T119	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	INPUT
prim_tl_i.a_valid	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	INPUT
prim_tl_o.a_ready	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
prim_tl_o.d_error	Yes	Yes	T18,T114,T115	Yes	T114,T183,T184	OUTPUT
prim_tl_o.d_user.data_intg[0]	Excluded	Excluded	*T116,*T117,*T118	Excluded	T116,T117,T118	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[1]	Yes	Yes	*T116,*T117,*T118	Yes	T116,T117,T118	OUTPUT
prim_tl_o.d_user.data_intg[2]	Excluded	Excluded	*T116,*T117,*T118	Excluded	T116,T117,T118	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[3]	Yes	Yes	*T116,*T117,*T118	Yes	T116,T117,T118	OUTPUT
prim_tl_o.d_user.data_intg[4]	Excluded	Excluded	*T116,*T117,*T118	Excluded	T116,T117,T118	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[5]	Yes	Yes	*T116,*T117,*T118	Yes	T116,T117,T118	OUTPUT
prim_tl_o.d_user.data_intg[6]	Excluded	Excluded	T116,T117,T118	Excluded	T116,T117,T118	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.rsp_intg[5:0]	Excluded	Excluded	T114,T116,*T117	Excluded	T114,T116,T117	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T18,T114,T115	Yes	T114,T116,T117	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T114,T116,T183	Yes	T114,T116,T183	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T18,*T114,*T115	Yes	T114,T116,T117	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T18,T115,T119	Yes	T18,T115,T119	OUTPUT
intr_otp_error_o	Yes	Yes	T18,T115,T119	Yes	T18,T115,T119	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T117,T118,T121	Yes	T117,T118,T121	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T117,T118,T121	Yes	T117,T118,T121	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T117,T118,T121	Yes	T117,T118,T121	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T117,T118,T121	Yes	T117,T118,T121	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T121,T208,T188	Yes	T187,T208,T209	INPUT
pwr_otp_i.otp_init	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T121,T187,T208	Yes	T18,T114,T115	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T121,T187,T208	Yes	T18,T114,T115	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
lc_otp_program_i.count[383:0]	Yes	Yes	T35,T94,T13	Yes	T35,T94,T13	INPUT
lc_otp_program_i.state[319:0]	Yes	Yes	T35,T94,T13	Yes	T35,T94,T13	INPUT
lc_otp_program_i.req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_otp_program_o.ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
lc_otp_program_o.err	Yes	Yes	T35,T94,T13	Yes	T35,T94,T13	OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T121,T208,T188	Yes	T208,T189,T209	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T187,T208,T188	Yes	T18,T114,T115	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T3,T11,T109	Yes	T3,T11,T109	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T18,T114,T115	Yes	T18,T114,T115	INPUT
otp_lc_data_o.rma_token[127:0]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T1,T2,T15	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.test_exit_token[127:0]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T1,T11,T94	Yes	T1,T3,T9	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T1,T11,T15	Yes	T1,T9,T11	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T1,T2,T15	Yes	T1,T2,T3	OUTPUT
otp_lc_data_o.count[3:0]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[4]	No	No		No		OUTPUT
otp_lc_data_o.count[14:5]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[15]	No	No		No		OUTPUT
otp_lc_data_o.count[27:16]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[32:28]	No	No		No		OUTPUT
otp_lc_data_o.count[41:33]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[42]	No	No		No		OUTPUT
otp_lc_data_o.count[46:43]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[47]	No	No		No		OUTPUT
otp_lc_data_o.count[61:48]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[62]	No	No		No		OUTPUT
otp_lc_data_o.count[63]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[64]	No	No		No		OUTPUT
otp_lc_data_o.count[78:65]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[79]	No	No		No		OUTPUT
otp_lc_data_o.count[85:80]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[86]	No	No		No		OUTPUT
otp_lc_data_o.count[105:87]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[106]	No	No		No		OUTPUT
otp_lc_data_o.count[115:107]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[116]	No	No		No		OUTPUT
otp_lc_data_o.count[118:117]	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
otp_lc_data_o.count[119]	No	No		No		OUTPUT
otp_lc_data_o.count[124:120]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[125]	No	No		No		OUTPUT
otp_lc_data_o.count[134:126]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[135]	No	No		No		OUTPUT
otp_lc_data_o.count[138:136]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[139]	No	No		No		OUTPUT
otp_lc_data_o.count[151:140]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[153:152]	No	No		No		OUTPUT
otp_lc_data_o.count[159:154]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[160]	No	No		No		OUTPUT
otp_lc_data_o.count[164:161]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[165]	No	No		No		OUTPUT
otp_lc_data_o.count[174:166]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[176:175]	No	No		No		OUTPUT
otp_lc_data_o.count[180:177]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[181]	No	No		No		OUTPUT
otp_lc_data_o.count[186:182]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[187]	No	No		No		OUTPUT
otp_lc_data_o.count[194:188]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[195]	No	No		No		OUTPUT
otp_lc_data_o.count[196]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[197]	No	No		No		OUTPUT
otp_lc_data_o.count[198]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[199]	No	No		No		OUTPUT
otp_lc_data_o.count[207:200]	Yes	Yes	*T1,*T15,*T57	Yes	T1,T15,T57	OUTPUT
otp_lc_data_o.count[208]	No	No		No		OUTPUT
otp_lc_data_o.count[217:209]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[219:218]	No	No		No		OUTPUT
otp_lc_data_o.count[225:220]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[226]	No	No		No		OUTPUT
otp_lc_data_o.count[232:227]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[233]	No	No		No		OUTPUT
otp_lc_data_o.count[237:234]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[238]	No	No		No		OUTPUT
otp_lc_data_o.count[240:239]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[241]	No	No		No		OUTPUT
otp_lc_data_o.count[254:242]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[255]	No	No		No		OUTPUT
otp_lc_data_o.count[263:256]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[264]	No	No		No		OUTPUT
otp_lc_data_o.count[266:265]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[267]	No	No		No		OUTPUT
otp_lc_data_o.count[269:268]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[270]	No	No		No		OUTPUT
otp_lc_data_o.count[272:271]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[273]	No	No		No		OUTPUT
otp_lc_data_o.count[274]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[275]	No	No		No		OUTPUT
otp_lc_data_o.count[302:276]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[303]	No	No		No		OUTPUT
otp_lc_data_o.count[327:304]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[328]	No	No		No		OUTPUT
otp_lc_data_o.count[330:329]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[331]	No	No		No		OUTPUT
otp_lc_data_o.count[333:332]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[334]	No	No		No		OUTPUT
otp_lc_data_o.count[345:335]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.count[346]	No	No		No		OUTPUT
otp_lc_data_o.count[365:347]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[367:366]	No	No		No		OUTPUT
otp_lc_data_o.count[379:368]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.count[380]	No	No		No		OUTPUT
otp_lc_data_o.count[383:381]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[6]	No	No		No		OUTPUT
otp_lc_data_o.state[9:7]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[10]	No	No		No		OUTPUT
otp_lc_data_o.state[14:11]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[15]	No	No		No		OUTPUT
otp_lc_data_o.state[17:16]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[20:18]	No	No		No		OUTPUT
otp_lc_data_o.state[31:21]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[32]	No	No		No		OUTPUT
otp_lc_data_o.state[34:33]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[35]	No	No		No		OUTPUT
otp_lc_data_o.state[36]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[37]	No	No		No		OUTPUT
otp_lc_data_o.state[42:38]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[43]	No	No		No		OUTPUT
otp_lc_data_o.state[50:44]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[53:51]	No	No		No		OUTPUT
otp_lc_data_o.state[61:54]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[62]	No	No		No		OUTPUT
otp_lc_data_o.state[77:63]	Yes	Yes	*T2,*T4,*T15	Yes	T2,T4,T15	OUTPUT
otp_lc_data_o.state[78]	No	No		No		OUTPUT
otp_lc_data_o.state[79]	Yes	Yes	*T2,*T4,*T15	Yes	T2,T4,T15	OUTPUT
otp_lc_data_o.state[80]	No	No		No		OUTPUT
otp_lc_data_o.state[83:81]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[84]	No	No		No		OUTPUT
otp_lc_data_o.state[87:85]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[88]	No	No		No		OUTPUT
otp_lc_data_o.state[95:89]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[96]	No	No		No		OUTPUT
otp_lc_data_o.state[101:97]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[102]	No	No		No		OUTPUT
otp_lc_data_o.state[103]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[104]	No	No		No		OUTPUT
otp_lc_data_o.state[110:105]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[111]	No	No		No		OUTPUT
otp_lc_data_o.state[113:112]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[115:114]	No	No		No		OUTPUT
otp_lc_data_o.state[123:116]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[124]	No	No		No		OUTPUT
otp_lc_data_o.state[126:125]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[127]	No	No		No		OUTPUT
otp_lc_data_o.state[131:128]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[132]	No	No		No		OUTPUT
otp_lc_data_o.state[136:133]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[137]	No	No		No		OUTPUT
otp_lc_data_o.state[141:138]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[142]	No	No		No		OUTPUT
otp_lc_data_o.state[146:143]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[147]	No	No		No		OUTPUT
otp_lc_data_o.state[149:148]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[150]	No	No		No		OUTPUT
otp_lc_data_o.state[151]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[152]	No	No		No		OUTPUT
otp_lc_data_o.state[156:153]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[158:157]	No	No		No		OUTPUT
otp_lc_data_o.state[160:159]	Yes	Yes	*T1,T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[161]	No	No		No		OUTPUT
otp_lc_data_o.state[163:162]	Yes	Yes	*T1,T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[166:164]	No	No		No		OUTPUT
otp_lc_data_o.state[177:167]	Yes	Yes	*T2,*T15,*T57	Yes	T2,T4,T15	OUTPUT
otp_lc_data_o.state[178]	No	No		No		OUTPUT
otp_lc_data_o.state[180:179]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[182:181]	No	No		No		OUTPUT
otp_lc_data_o.state[186:183]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[187]	No	No		No		OUTPUT
otp_lc_data_o.state[198:188]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[200:199]	No	No		No		OUTPUT
otp_lc_data_o.state[210:201]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[211]	No	No		No		OUTPUT
otp_lc_data_o.state[217:212]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[218]	No	No		No		OUTPUT
otp_lc_data_o.state[219]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[220]	No	No		No		OUTPUT
otp_lc_data_o.state[243:221]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[244]	No	No		No		OUTPUT
otp_lc_data_o.state[250:245]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[251]	No	No		No		OUTPUT
otp_lc_data_o.state[273:252]	Yes	Yes	*T18,*T114,*T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[274]	No	No		No		OUTPUT
otp_lc_data_o.state[279:275]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[280]	No	No		No		OUTPUT
otp_lc_data_o.state[294:281]	Yes	Yes	*T57,*T127,*T35	Yes	T57,T127,T35	OUTPUT
otp_lc_data_o.state[295]	No	No		No		OUTPUT
otp_lc_data_o.state[301:296]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.state[302]	No	No		No		OUTPUT
otp_lc_data_o.state[307:303]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
otp_lc_data_o.state[308]	No	No		No		OUTPUT
otp_lc_data_o.state[316:309]	Yes	Yes	*T57,*T35,*T102	Yes	T57,T35,T102	OUTPUT
otp_lc_data_o.state[317]	No	No		No		OUTPUT
otp_lc_data_o.state[319:318]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_lc_data_o.error	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T121,T187,T208	Yes	T18,T114,T115	OUTPUT
otp_keymgr_key_o.key_share1[255:0]	Yes	Yes	T114,T116,T117	Yes	T121,T187,T208	OUTPUT
otp_keymgr_key_o.key_share0[255:0]	Yes	Yes	T102,T94,T98	Yes	T102,T94,T98	OUTPUT
otp_keymgr_key_o.valid	Yes	Yes	T1,T2,T15	Yes	T1,T2,T3	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
flash_otp_key_i.data_req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
sram_otp_key_i[1].req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
sram_otp_key_i[2].req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T1,T2,T15	Yes	T1,T2,T15	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
otp_hw_cfg_o.data.device_id[255:0]	Yes	Yes	T127,T94,T95	Yes	T127,T94,T95	OUTPUT
otp_hw_cfg_o.data.manuf_state[255:0]	Yes	Yes	T95,T101,T175	Yes	T95,T101,T175	OUTPUT
otp_hw_cfg_o.data.en_sram_ifetch[7:0]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_hw_cfg_o.data.en_csrng_sw_app_read[7:0]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_read[7:0]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[7:0]	Yes	Yes	T18,T114,T115	Yes	T121,T187,T208	OUTPUT
otp_hw_cfg_o.data.unallocated[31:0]	Yes	Yes	T4,T15,T127	Yes	T4,T15,T127	OUTPUT
otp_hw_cfg_o.data.hw_cfg_digest[63:0]	Yes	Yes	T1,T15,T35	Yes	T1,T15,T35	OUTPUT
otp_hw_cfg_o.valid[3:0]	Yes	Yes	T121,T187,T208	Yes	T18,T114,T115	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T208,T191,T210	Yes	T208,T209,T211	INPUT
scan_rst_ni	Yes	Yes	T208,T188,T209	Yes	T208,T209,T211	INPUT
scanmode_i[3:0]	Yes	Yes	T208,T189,T191	Yes	T121,T208,T188	INPUT
cio_test_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
cio_test_en_o[7:0]	Yes	Yes	T121,T187,T208	Yes	T18,T114,T115	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		33	32	96.97
TERNARY	1300	2	2	100.00
TERNARY	1352	2	2	100.00
TERNARY	1354	2	2	100.00
TERNARY	1356	2	2	100.00
IF	268	3	2	66.67
IF	289	2	2	100.00
IF	329	2	2	100.00
IF	332	2	2	100.00
IF	335	2	2	100.00
IF	339	2	2	100.00
IF	399	2	2	100.00
IF	438	2	2	100.00
IF	459	2	2	100.00
IF	462	2	2	100.00
IF	499	2	2	100.00
IF	956	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1300	(part_init_done[HwCfgIdx]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1352	((part_digest[Secret0Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1354	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1356	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	if (tlul_req)
-2-:	269	if ((tlul_part_sel_oh != '0))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	289	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	329	if ((!reg2hw.vendor_test_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	332	if ((!reg2hw.creator_sw_cfg_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	if ((!reg2hw.owner_sw_cfg_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	339	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	399	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	438	if (otp_ctrl_part_pkg::PartInfo[k].ecc_fatal)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	459	if ((fatal_macro_error_q || fatal_check_error_q))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	462	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	499	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	956	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	64	64	100.00	64	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	64	64	100.00	64	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	1907808725	1906948445	0	0
CoreTlOutKnown_A	1907808725	1906948445	0	0
CreatorRootKeyShare0Size_A	1155	1155	0	0
CreatorRootKeyShare1Size_A	1155	1155	0	0
ErrorCodeWidth_A	1155	1155	0	0
FlashAddrKeySeedSize_A	1155	1155	0	0
FlashDataKeySeedSize_A	1155	1155	0	0
FlashOtpKeyRspKnown_A	1907808725	1906948445	0	0
FpvSecCmCntCnstyCheck_A	1907808725	50	0	0
FpvSecCmCntDaiCheck_A	1907808725	50	0	0
FpvSecCmCntIntegCheck_A	1907808725	50	0	0
FpvSecCmCntKdiEntropyCheck_A	1907808725	50	0	0
FpvSecCmCntKdiSeedCheck_A	1907808725	50	0	0
FpvSecCmCntLciCheck_A	1907808725	50	0	0
FpvSecCmCntScrmblCheck_A	1907808725	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	1907808725	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	1907808725	50	0	0
FpvSecCmCtrlLciFsmCheck_A	1907808725	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	1907808725	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	1907808725	50	0	0
FpvSecCmDoubleLfsrCheck_A	1907808725	50	0	0
FpvSecCmRegWeOnehotCheck_A	1907808725	50	0	0
FpvSecCmTlLcGateFsm_A	1907808725	50	0	0
IntrOtpErrorKnown_A	1907808725	1906948445	0	0
IntrOtpOperationDoneKnown_A	1907808725	1906948445	0	0
LcOtpProgramRspKnown_A	1907808725	1906948445	0	0
LcSeedHwRdEnStable_A	1907808725	2360	0	0
LcStateSize_A	1155	1155	0	0
LcTransitionCntSize_A	1155	1155	0	0
OtpAstPwrSeqKnown_A	1907808725	1906948445	0	0
OtpErrorCode0_A	1155	1155	0	0
OtpErrorCode1_A	1155	1155	0	0
OtpErrorCode2_A	1155	1155	0	0
OtpErrorCode3_A	1155	1155	0	0
OtpErrorCode4_A	1155	1155	0	0
OtpHwCfgKnown_A	1907808725	1906948445	0	0
OtpIfWidth_A	1155	1155	0	0
OtpKeymgrKeyKnown_A	1907808725	1906948445	0	0
OtpLcDataKnown_A	1907808725	1906948445	0	0
OtpOtgnKeyKnown_A	1907808725	1906948445	0	0
OtpRespFifoUnderflow_A	1907808725	1561281	0	0
OtpSramKeyKnown_A	1907808725	1906948445	0	0
PartSelMustBeOnehot_A	1907808725	1906948445	0	0
PrimTlOutKnown_A	1907808725	1906948445	0	0
PwrOtpInitRspKnown_A	1907808725	1906948445	0	0
RmaTokenSize_A	1155	1155	0	0
SramDataKeySeedSize_A	1155	1155	0	0
TestExitTokenSize_A	1155	1155	0	0
TestUnlockTokenSize_A	1155	1155	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1907808725	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1907808725	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1907808725	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A	1907808725	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1907808725	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A	1907808725	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1907808725	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	1907808725	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1907808725	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	1907808725	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1907808725	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A	1907808725	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	1907808725	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	1907808725	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	1907808725	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

LcSeedHwRdEnStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	2360	0	0
T1	74746	10	0	0
T2	85442	1	0	0
T3	16626	1	0	0
T4	29296	0	0	0
T6	10723	0	0	0
T7	8457	0	0	0
T8	12849	0	0	0
T9	8680	1	0	0
T10	11811	0	0	0
T11	39774	0	0	0
T15	0	3	0	0
T35	0	8	0	0
T93	0	6	0	0
T94	0	48	0	0
T102	0	8	0	0
T112	0	1	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpHwCfgKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1561281	0	0
T1	74746	1130	0	0
T2	85442	1694	0	0
T3	16626	193	0	0
T4	29296	629	0	0
T6	10723	127	0	0
T7	8457	132	0	0
T8	12849	137	0	0
T9	8680	172	0	0
T10	11811	197	0	0
T11	39774	285	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	50	0	0
T21	862527	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T87	34869	0	0	0
T88	8675	0	0	0
T89	8239	0	0	0
T90	17355	0	0	0
T91	14910	0	0	0
T92	24522	0	0	0
T212	0	10	0	0
T213	0	10	0	0
T214	15338	0	0	0
T215	3492	0	0	0
T216	3674	0	0	0