Unified Coverage Report :: Module :: otp_ctrl_dai

Module : otp_ctrl_dai

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.06	94.47	88.75		85.00	87.06	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_dai	91.95	94.47	88.75		89.47	87.06	100.00

---

Module Instance : tb.dut.u_otp_ctrl_dai

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.95	94.47	88.75		89.47	87.06	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.68	90.73	93.06	100.00	89.47	90.43	86.36

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.76		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_part_sel_idx	82.27	76.81	98.44			100.00	53.85
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : otp_ctrl_dai

	Line No.	Total	Covered	Percent
TOTAL		235	222	94.47
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
ALWAYS	174	193	180	93.26
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
ALWAYS	720	11	11	100.00
CONT_ASSIGN	761	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
ALWAYS	768	3	3	100.00
ALWAYS	771	14	14	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
164	1	1
166	1	1
167	1	1
171	1	1
174	1	1
177	1	1
178	1	1
181	1	1
182	1	1
183	1	1
186	1	1
187	1	1
190	1	1
193	1	1
194	1	1
195	1	1
196	1	1
199	1	1
200	1	1
201	1	1
204	1	1
205	1	1
206	1	1
209	1	1
210	1	1
212	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			==> MISSING_ELSE
			MISSING_ELSE
234	1	1
235	1	1
236	1	1
237	1	1
238	0	1
239	0	1
241	1	1
			MISSING_ELSE
250	1	1
251	1	1
252	1	1
253	1	1
254	1	1
			MISSING_ELSE
261	1	1
262	1	1
264	1	1
265	1	1
266	1	1
268	1	1
270	1	1
271	1	1
274	1	1
276	1	1
277	1	1
279	1	1
280	1	1
282	1	1
286	1	1
287	1	1
288	1	1
			MISSING_ELSE
300	1	1
303	1	1
304	1	1
305	1	1
306	1	1
			MISSING_ELSE
309	1	1
310	1	1
311	1	1
321	1	1
324	1	1
327	1	1
329	1	1
331	1	1
332	1	1
334	1	1
335	1	1
342	1	1
343	1	1
			MISSING_ELSE
346	1	1
347	1	1
			MISSING_ELSE
354	0	1
355	0	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
			MISSING_ELSE
378	1	1
379	1	1
380	1	1
381	1	1
382	1	1
383	1	1
384	1	1
			MISSING_ELSE
395	1	1
396	1	1
405	1	1
406	1	1
407	1	1
408	1	1
			MISSING_ELSE
412	1	1
413	1	1
414	1	1
415	1	1
423	1	1
425	1	1
435	1	1
437	1	1
438	0	1
439	0	1
442	1	1
443	1	1
444	1	1
446	1	1
447	1	1
			MISSING_ELSE
			MISSING_ELSE
455	0	1
456	0	1
466	1	1
468	1	1
474	1	1
475	1	1
476	1	1
477	1	1
478	1	1
			MISSING_ELSE
481	1	1
482	1	1
483	1	1
491	1	1
493	1	1
498	1	1
499	1	1
500	1	1
501	1	1
			MISSING_ELSE
507	0	1
508	0	1
515	1	1
516	1	1
518	1	1
519	1	1
520	1	1
			MISSING_ELSE
528	1	1
529	1	1
531	1	1
532	1	1
533	1	1
534	1	1
			MISSING_ELSE
537	1	1
538	1	1
539	1	1
549	1	1
550	1	1
551	1	1
553	1	1
554	0	1
555	0	1
557	1	1
558	1	1
560	1	1
561	0	1
			MISSING_ELSE
			MISSING_ELSE
572	1	1
573	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
			==> MISSING_ELSE
583	1	1
584	1	1
			MISSING_ELSE
588	1	1
589	1	1
			MISSING_ELSE
592	1	1
593	1	1
			MISSING_ELSE
602	1	1
603	1	1
604	1	1
605	1	1
606	1	1
			==> MISSING_ELSE
613	1	1
614	1	1
615	1	1
616	1	1
617	1	1
			MISSING_ELSE
628	1	1
629	1	1
630	1	1
631	1	1
632	1	1
			MISSING_ELSE
640	1	1
641	1	1
			MISSING_ELSE
656	1	1
657	1	1
658	1	1
659	1	1
660	1	1
			MISSING_ELSE
			MISSING_ELSE
689	8	8
720	1	1
721	1	1
724	1	1
725	1	1
726	1	1
728	1	1
729	1	1
730	1	1
732	1	1
734	1	1
735	1	1
			MISSING_ELSE
761	1	1
762	1	1
768	3	3
771	1	1
772	1	1
773	1	1
774	1	1
776	1	1
777	1	1
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
785	1	1
786	1	1
788	1	1
			MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_dai

	Total	Covered	Percent
Conditions	80	71	88.75
Logical	80	71	88.75
Non-Logical	0	0
Event	0	0

 LINE       171
 EXPRESSION ((state_q == IdleSt) ? data_q : '0)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 SUB-EXPRESSION (state_q == IdleSt)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       253
 EXPRESSION (part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}})
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       327
 EXPRESSION 
 Number  Term
      1  (((!otp_ctrl_part_pkg::PartInfo[part_idx].ecc_fatal)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || 
      2  (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T127,T128,T129

 LINE       327
 SUB-EXPRESSION (((!otp_ctrl_part_pkg::PartInfo[part_idx].ecc_fatal)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 --------------------------1-------------------------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T127,T128,T129

 LINE       327
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T8

 LINE       331
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx]))
             ----------------------1---------------------    --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       331
 SUB-EXPRESSION (otp_addr_o != digest_addr_lut[part_idx])
                --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T2,T4,T57

 LINE       369
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       446
 EXPRESSION (otp_err_e'(otp_err_i) == MacroWriteBlankError)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T130,T35

 LINE       477
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       519
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION (otp_err_e'(otp_err_i) == MacroEccCorrError)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       575
 EXPRESSION (otp_addr_o == digest_addr_lut[part_idx])
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       640
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T21,T22,T23

 LINE       659
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b0) & ({1'b0, dai_addr_i} < gen_part_sel[0].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ----------1----------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b00001000000) & ({1'b0, dai_addr_i} < gen_part_sel[1].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b01101100000) & ({1'b0, dai_addr_i} < gen_part_sel[2].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b11010000000) & ({1'b0, dai_addr_i} < gen_part_sel[3].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b11011010000) & ({1'b0, dai_addr_i} < gen_part_sel[4].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b11011111000) & ({1'b0, dai_addr_i} < gen_part_sel[5].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b11101010000) & ({1'b0, dai_addr_i} < gen_part_sel[6].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b11110101000) & ({1'b0, dai_addr_i} < gen_part_sel[7].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       728
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset))
             -----------------------1-----------------------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T15

 LINE       728
 SUB-EXPRESSION (base_sel_q == PartOffset)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T15

 LINE       732
 EXPRESSION ((base_sel_q == DaiOffset) && ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx]))
             ------------1------------    ----------------------------------------------2----------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       732
 SUB-EXPRESSION (base_sel_q == DaiOffset)
                ------------1------------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T1,T2,T3

 LINE       732
 SUB-EXPRESSION ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])
                ----------------------------------------------1----------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       783
 EXPRESSION (data_sel == ScrmblData)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       785
 EXPRESSION (data_sel == DaiData)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : otp_ctrl_dai

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	48	43	89.58
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DescrSt	332	Covered	T18
DescrWaitSt	370	Covered	T18
DigClrSt	286	Covered	T18
DigFinSt	580	Covered	T18
DigPadSt	584	Covered	T18
DigReadSt	520	Covered	T18
DigReadWaitSt	534	Covered	T18
DigSt	558	Covered	T18
DigWaitSt	617	Covered	T18
ErrorSt	238	Covered	T18
IdleSt	254	Covered	T18
InitOtpSt	225	Covered	T18
InitPartSt	241	Covered	T18
ReadSt	268	Covered	T18
ReadWaitSt	306	Covered	T18
ResetSt	218	Covered	T18
ScrSt	280	Covered	T18
ScrWaitSt	478	Covered	T18
WriteSt	282	Covered	T18
WriteWaitSt	408	Covered	T18

transitions	Line No.	Covered	Tests
DescrSt->DescrWaitSt	370	Covered	T18
DescrSt->ErrorSt	657	Covered	T18
DescrWaitSt->ErrorSt	657	Covered	T18
DescrWaitSt->IdleSt	382	Covered	T18
DigClrSt->DigReadSt	520	Covered	T18
DigClrSt->ErrorSt	657	Not Covered
DigFinSt->DigWaitSt	617	Covered	T18
DigFinSt->ErrorSt	657	Covered	T18
DigPadSt->DigFinSt	606	Covered	T18
DigPadSt->ErrorSt	657	Covered	T18
DigReadSt->DigReadWaitSt	534	Covered	T18
DigReadSt->ErrorSt	657	Covered	T18
DigReadSt->IdleSt	537	Covered	T18
DigReadWaitSt->DigSt	558	Covered	T18
DigReadWaitSt->ErrorSt	554	Covered	T18
DigSt->DigFinSt	580	Covered	T18
DigSt->DigPadSt	584	Covered	T18
DigSt->DigReadSt	593	Covered	T18
DigSt->ErrorSt	657	Covered	T18
DigWaitSt->ErrorSt	657	Covered	T18
DigWaitSt->WriteSt	631	Covered	T18
IdleSt->DigClrSt	286	Covered	T18
IdleSt->ErrorSt	657	Covered	T18
IdleSt->ReadSt	268	Covered	T18
IdleSt->ScrSt	280	Covered	T18
IdleSt->WriteSt	282	Covered	T18
InitOtpSt->ErrorSt	238	Covered	T18
InitOtpSt->InitPartSt	241	Covered	T18
InitPartSt->ErrorSt	657	Covered	T18
InitPartSt->IdleSt	254	Covered	T18
ReadSt->ErrorSt	657	Not Covered
ReadSt->IdleSt	309	Covered	T18
ReadSt->ReadWaitSt	306	Covered	T18
ReadWaitSt->DescrSt	332	Covered	T18
ReadWaitSt->ErrorSt	346	Covered	T18
ReadWaitSt->IdleSt	334	Covered	T18
ResetSt->ErrorSt	657	Covered	T18
ResetSt->InitOtpSt	225	Covered	T18
ScrSt->ErrorSt	657	Not Covered
ScrSt->IdleSt	481	Covered	T18
ScrSt->ScrWaitSt	478	Covered	T18
ScrWaitSt->ErrorSt	507	Not Covered
ScrWaitSt->WriteSt	500	Covered	T18
WriteSt->ErrorSt	657	Not Covered
WriteSt->IdleSt	413	Covered	T18
WriteSt->WriteWaitSt	408	Covered	T18
WriteWaitSt->ErrorSt	438	Covered	T18
WriteWaitSt->IdleSt	443	Covered	T18

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	12	8	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	310	Covered	T18
FsmStateError	355	Covered	T18
MacroEccCorrError	343	Covered	T18
NoError	264	Covered	T18

transitions	Line No.	Covered	Tests
AccessError->FsmStateError	355	Covered	T18
AccessError->MacroEccCorrError	343	Not Covered
AccessError->NoError	264	Covered	T18
FsmStateError->AccessError	310	Not Covered
FsmStateError->MacroEccCorrError	343	Not Covered
FsmStateError->NoError	264	Covered	T18
MacroEccCorrError->AccessError	310	Not Covered
MacroEccCorrError->FsmStateError	355	Covered	T18
MacroEccCorrError->NoError	264	Covered	T18
NoError->AccessError	310	Covered	T18
NoError->FsmStateError	355	Covered	T18
NoError->MacroEccCorrError	343	Covered	T18

---

Branch Coverage for Module : otp_ctrl_dai

	Line No.	Total	Covered	Percent
Branches		85	74	87.06
TERNARY	171	2	2	100.00
CASE	212	68	57	83.82
IF	656	3	3	100.00
IF	724	4	4	100.00
IF	768	2	2	100.00
IF	771	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	171	((state_q == IdleSt)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	212	case (state_q)
-2-:	222	if (init_req_i)
-3-:	224	if (otp_gnt_i)
-4-:	236	if (otp_rvalid_i)
-5-:	237	if ((!(otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	253	if ((part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}}))
-7-:	262	if (dai_req_i)
-8-:	266	case (dai_cmd_i)
-9-:	279	if (otp_ctrl_part_pkg::PartInfo[part_idx].secret)
-10-:	300	if ((prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx]))))
-11-:	305	if (otp_gnt_i)
-12-:	321	if ((prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx]))))
-13-:	324	if (otp_rvalid_i)
-14-:	327	if ((((!otp_ctrl_part_pkg::PartInfo[part_idx].ecc_fatal) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-15-:	331	if ((otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx])))
-16-:	342	if ((otp_err_e'(otp_err_i) != NoError))
-17-:	369	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-18-:	381	if (scrmbl_valid_i)
-19-:	396	if ((prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset)))))
-20-:	407	if (otp_gnt_i)
-21-:	425	if ((prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset)))))
-22-:	435	if (otp_rvalid_i)
-23-:	437	if ((!(otp_err_e'(otp_err_i) inside {NoError, MacroWriteBlankError})))
-24-:	446	if ((otp_err_e'(otp_err_i) == MacroWriteBlankError))
-25-:	468	if ((prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))))
-26-:	477	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-:	493	if ((prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))))
-28-:	499	if (scrmbl_valid_i)
-29-:	519	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-30-:	529	if ((prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)))
-31-:	533	if (otp_gnt_i)
-32-:	550	if (otp_rvalid_i)
-33-:	553	if ((!(otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-34-:	560	if ((otp_err_e'(otp_err_i) == MacroEccCorrError))
-35-:	575	if ((otp_addr_o == digest_addr_lut[part_idx]))
-36-:	577	if ((!cnt[0]))
-37-:	579	if (scrmbl_ready_i)
-38-:	583	if (scrmbl_ready_i)
-39-:	588	if ((!cnt[0]))
-40-:	592	if (scrmbl_ready_i)
-41-:	605	if (scrmbl_ready_i)
-42-:	616	if (scrmbl_ready_i)
-43-:	630	if (scrmbl_valid_i)
-44-:	640	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	-41-	-42-	-43-	-44-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitOtpSt	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitOtpSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitOtpSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitPartSt	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitPartSt	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	DaiRead	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	DaiWrite	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	DaiWrite	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	DaiDigest	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T12,T95
ReadSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	1	1	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T57
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	1	1	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DescrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
DescrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T102,T12
DescrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
DescrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T12,T95
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T130,T35
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T102,T12
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T7
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
DigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T102,T12
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T12,T95
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T15
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	Covered	T1,T2,T15
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	Covered	T1,T2,T15
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
DigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T2,T15
DigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T2,T3
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	656	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	659	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	724	if (otp_ctrl_part_pkg::PartInfo[part_idx].secret)
-2-:	728	if ((otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset)))
-3-:	732	if (((base_sel_q == DaiOffset) && ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	768	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	771	if ((!rst_ni))
-2-:	780	if (data_clr)
-3-:	782	if (data_en)
-4-:	783	if ((data_sel == ScrmblData))
-5-:	785	if ((data_sel == DaiData))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	1	-	Covered	T1,T2,T3
0	0	1	0	1	Covered	T1,T2,T3
0	0	1	0	0	Covered	T1,T2,T3
0	0	0	-	-	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_dai

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckNativeOtpWidth0_A	1155	1155	0	0
CheckNativeOtpWidth1_A	1155	1155	0	0
DaiIdleKnown_A	1907808725	1906948445	0	0
DaiRdataKnown_A	1907808725	1906948445	0	0
ErrorKnown_A	1907808725	1906948445	0	0
InitDoneKnown_A	1907808725	1906948445	0	0
OtpAddrKnown_A	1907808725	1906948445	0	0
OtpCmdKnown_A	1907808725	1906948445	0	0
OtpErrorState_A	1907808725	377	0	0
OtpReqKnown_A	1907808725	1906948445	0	0
OtpSizeKnown_A	1907808725	1906948445	0	0
OtpWdataKnown_A	1907808725	1906948445	0	0
PartInitReqKnown_A	1907808725	1906948445	0	0
PartSelMustBeOnehot_A	1907808725	1906948445	0	0
ScrmblBlockWidthGe8_A	1907808725	1906948445	0	0
ScrmblCmdKnown_A	1907808725	1906948445	0	0
ScrmblDataKnown_A	1907808725	1906948445	0	0
ScrmblModeKnown_A	1907808725	1906948445	0	0
ScrmblMtxReqKnown_A	1907808725	1906948445	0	0
ScrmblSelKnown_A	1907808725	1906948445	0	0
ScrmblValidKnown_A	1907808725	1906948445	0	0
gen_part_sel[0].PartEndMax_A	1155	1155	0	0
gen_part_sel[1].PartEndMax_A	1155	1155	0	0
gen_part_sel[2].PartEndMax_A	1155	1155	0	0
gen_part_sel[3].PartEndMax_A	1155	1155	0	0
gen_part_sel[4].PartEndMax_A	1155	1155	0	0
gen_part_sel[5].PartEndMax_A	1155	1155	0	0
gen_part_sel[6].PartEndMax_A	1155	1155	0	0
gen_part_sel[7].PartEndMax_A	1155	1155	0	0
u_state_regs_A	1907808725	1906948445	0	0

CheckNativeOtpWidth0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

CheckNativeOtpWidth1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

DaiIdleKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

DaiRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	377	0	0
T2	85442	7	0	0
T3	16626	0	0	0
T4	29296	2	0	0
T6	10723	0	0	0
T7	8457	0	0	0
T8	12849	1	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	0	0	0
T13	0	2	0	0
T35	0	4	0	0
T93	0	2	0	0
T94	0	1	0	0
T95	0	1	0	0
T127	0	7	0	0
T130	0	1	0	0
T131	8474	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

PartInitReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ScrmblBlockWidthGe8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ScrmblCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ScrmblDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ScrmblModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ScrmblMtxReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ScrmblSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ScrmblValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

gen_part_sel[0].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_part_sel[1].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_part_sel[2].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_part_sel[3].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_part_sel[4].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_part_sel[5].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_part_sel[6].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_part_sel[7].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

Line Coverage for Instance : tb.dut.u_otp_ctrl_dai

	Line No.	Total	Covered	Percent
TOTAL		235	222	94.47
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
ALWAYS	174	193	180	93.26
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
ALWAYS	720	11	11	100.00
CONT_ASSIGN	761	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
ALWAYS	768	3	3	100.00
ALWAYS	771	14	14	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
164	1	1
166	1	1
167	1	1
171	1	1
174	1	1
177	1	1
178	1	1
181	1	1
182	1	1
183	1	1
186	1	1
187	1	1
190	1	1
193	1	1
194	1	1
195	1	1
196	1	1
199	1	1
200	1	1
201	1	1
204	1	1
205	1	1
206	1	1
209	1	1
210	1	1
212	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			==> MISSING_ELSE
			MISSING_ELSE
234	1	1
235	1	1
236	1	1
237	1	1
238	0	1
239	0	1
241	1	1
			MISSING_ELSE
250	1	1
251	1	1
252	1	1
253	1	1
254	1	1
			MISSING_ELSE
261	1	1
262	1	1
264	1	1
265	1	1
266	1	1
268	1	1
270	1	1
271	1	1
274	1	1
276	1	1
277	1	1
279	1	1
280	1	1
282	1	1
286	1	1
287	1	1
288	1	1
			MISSING_ELSE
300	1	1
303	1	1
304	1	1
305	1	1
306	1	1
			MISSING_ELSE
309	1	1
310	1	1
311	1	1
321	1	1
324	1	1
327	1	1
329	1	1
331	1	1
332	1	1
334	1	1
335	1	1
342	1	1
343	1	1
			MISSING_ELSE
346	1	1
347	1	1
			MISSING_ELSE
354	0	1
355	0	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
370	1	1
			MISSING_ELSE
378	1	1
379	1	1
380	1	1
381	1	1
382	1	1
383	1	1
384	1	1
			MISSING_ELSE
395	1	1
396	1	1
405	1	1
406	1	1
407	1	1
408	1	1
			MISSING_ELSE
412	1	1
413	1	1
414	1	1
415	1	1
423	1	1
425	1	1
435	1	1
437	1	1
438	0	1
439	0	1
442	1	1
443	1	1
444	1	1
446	1	1
447	1	1
			MISSING_ELSE
			MISSING_ELSE
455	0	1
456	0	1
466	1	1
468	1	1
474	1	1
475	1	1
476	1	1
477	1	1
478	1	1
			MISSING_ELSE
481	1	1
482	1	1
483	1	1
491	1	1
493	1	1
498	1	1
499	1	1
500	1	1
501	1	1
			MISSING_ELSE
507	0	1
508	0	1
515	1	1
516	1	1
518	1	1
519	1	1
520	1	1
			MISSING_ELSE
528	1	1
529	1	1
531	1	1
532	1	1
533	1	1
534	1	1
			MISSING_ELSE
537	1	1
538	1	1
539	1	1
549	1	1
550	1	1
551	1	1
553	1	1
554	0	1
555	0	1
557	1	1
558	1	1
560	1	1
561	0	1
			MISSING_ELSE
			MISSING_ELSE
572	1	1
573	1	1
575	1	1
577	1	1
578	1	1
579	1	1
580	1	1
			==> MISSING_ELSE
583	1	1
584	1	1
			MISSING_ELSE
588	1	1
589	1	1
			MISSING_ELSE
592	1	1
593	1	1
			MISSING_ELSE
602	1	1
603	1	1
604	1	1
605	1	1
606	1	1
			==> MISSING_ELSE
613	1	1
614	1	1
615	1	1
616	1	1
617	1	1
			MISSING_ELSE
628	1	1
629	1	1
630	1	1
631	1	1
632	1	1
			MISSING_ELSE
640	1	1
641	1	1
			MISSING_ELSE
656	1	1
657	1	1
658	1	1
659	1	1
660	1	1
			MISSING_ELSE
			MISSING_ELSE
689	8	8
720	1	1
721	1	1
724	1	1
725	1	1
726	1	1
728	1	1
729	1	1
730	1	1
732	1	1
734	1	1
735	1	1
			MISSING_ELSE
761	1	1
762	1	1
768	3	3
771	1	1
772	1	1
773	1	1
774	1	1
776	1	1
777	1	1
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
785	1	1
786	1	1
788	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_otp_ctrl_dai

	Total	Covered	Percent
Conditions	80	71	88.75
Logical	80	71	88.75
Non-Logical	0	0
Event	0	0

 LINE       171
 EXPRESSION ((state_q == IdleSt) ? data_q : '0)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 SUB-EXPRESSION (state_q == IdleSt)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       253
 EXPRESSION (part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}})
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       327
 EXPRESSION 
 Number  Term
      1  (((!otp_ctrl_part_pkg::PartInfo[part_idx].ecc_fatal)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || 
      2  (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T127,T128,T129

 LINE       327
 SUB-EXPRESSION (((!otp_ctrl_part_pkg::PartInfo[part_idx].ecc_fatal)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 --------------------------1-------------------------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Covered	T1,T2,T4
1	1	Covered	T127,T128,T129

 LINE       327
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T8

 LINE       331
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx]))
             ----------------------1---------------------    --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       331
 SUB-EXPRESSION (otp_addr_o != digest_addr_lut[part_idx])
                --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T2,T4,T57

 LINE       369
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       446
 EXPRESSION (otp_err_e'(otp_err_i) == MacroWriteBlankError)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T130,T35

 LINE       477
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       519
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION (otp_err_e'(otp_err_i) == MacroEccCorrError)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       575
 EXPRESSION (otp_addr_o == digest_addr_lut[part_idx])
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       640
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T21,T22,T23

 LINE       659
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b0) & ({1'b0, dai_addr_i} < gen_part_sel[0].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ----------1----------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b00001000000) & ({1'b0, dai_addr_i} < gen_part_sel[1].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b01101100000) & ({1'b0, dai_addr_i} < gen_part_sel[2].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b11010000000) & ({1'b0, dai_addr_i} < gen_part_sel[3].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b11011010000) & ({1'b0, dai_addr_i} < gen_part_sel[4].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b11011111000) & ({1'b0, dai_addr_i} < gen_part_sel[5].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b11101010000) & ({1'b0, dai_addr_i} < gen_part_sel[6].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       689
 EXPRESSION ((dai_addr_i >= 11'b11110101000) & ({1'b0, dai_addr_i} < gen_part_sel[7].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0]))
             ---------------1---------------   -------------------------------------------2-------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       728
 EXPRESSION (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset))
             -----------------------1-----------------------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T15

 LINE       728
 SUB-EXPRESSION (base_sel_q == PartOffset)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T15

 LINE       732
 EXPRESSION ((base_sel_q == DaiOffset) && ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx]))
             ------------1------------    ----------------------------------------------2----------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       732
 SUB-EXPRESSION (base_sel_q == DaiOffset)
                ------------1------------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T1,T2,T3

 LINE       732
 SUB-EXPRESSION ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])
                ----------------------------------------------1----------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       783
 EXPRESSION (data_sel == ScrmblData)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       785
 EXPRESSION (data_sel == DaiData)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_otp_ctrl_dai

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	48	43	89.58
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DescrSt	332	Covered	T18
DescrWaitSt	370	Covered	T18
DigClrSt	286	Covered	T18
DigFinSt	580	Covered	T18
DigPadSt	584	Covered	T18
DigReadSt	520	Covered	T18
DigReadWaitSt	534	Covered	T18
DigSt	558	Covered	T18
DigWaitSt	617	Covered	T18
ErrorSt	238	Covered	T18
IdleSt	254	Covered	T18
InitOtpSt	225	Covered	T18
InitPartSt	241	Covered	T18
ReadSt	268	Covered	T18
ReadWaitSt	306	Covered	T18
ResetSt	218	Covered	T18
ScrSt	280	Covered	T18
ScrWaitSt	478	Covered	T18
WriteSt	282	Covered	T18
WriteWaitSt	408	Covered	T18

transitions	Line No.	Covered	Tests
DescrSt->DescrWaitSt	370	Covered	T18
DescrSt->ErrorSt	657	Covered	T18
DescrWaitSt->ErrorSt	657	Covered	T18
DescrWaitSt->IdleSt	382	Covered	T18
DigClrSt->DigReadSt	520	Covered	T18
DigClrSt->ErrorSt	657	Not Covered
DigFinSt->DigWaitSt	617	Covered	T18
DigFinSt->ErrorSt	657	Covered	T18
DigPadSt->DigFinSt	606	Covered	T18
DigPadSt->ErrorSt	657	Covered	T18
DigReadSt->DigReadWaitSt	534	Covered	T18
DigReadSt->ErrorSt	657	Covered	T18
DigReadSt->IdleSt	537	Covered	T18
DigReadWaitSt->DigSt	558	Covered	T18
DigReadWaitSt->ErrorSt	554	Covered	T18
DigSt->DigFinSt	580	Covered	T18
DigSt->DigPadSt	584	Covered	T18
DigSt->DigReadSt	593	Covered	T18
DigSt->ErrorSt	657	Covered	T18
DigWaitSt->ErrorSt	657	Covered	T18
DigWaitSt->WriteSt	631	Covered	T18
IdleSt->DigClrSt	286	Covered	T18
IdleSt->ErrorSt	657	Covered	T18
IdleSt->ReadSt	268	Covered	T18
IdleSt->ScrSt	280	Covered	T18
IdleSt->WriteSt	282	Covered	T18
InitOtpSt->ErrorSt	238	Covered	T18
InitOtpSt->InitPartSt	241	Covered	T18
InitPartSt->ErrorSt	657	Covered	T18
InitPartSt->IdleSt	254	Covered	T18
ReadSt->ErrorSt	657	Not Covered
ReadSt->IdleSt	309	Covered	T18
ReadSt->ReadWaitSt	306	Covered	T18
ReadWaitSt->DescrSt	332	Covered	T18
ReadWaitSt->ErrorSt	346	Covered	T18
ReadWaitSt->IdleSt	334	Covered	T18
ResetSt->ErrorSt	657	Covered	T18
ResetSt->InitOtpSt	225	Covered	T18
ScrSt->ErrorSt	657	Not Covered
ScrSt->IdleSt	481	Covered	T18
ScrSt->ScrWaitSt	478	Covered	T18
ScrWaitSt->ErrorSt	507	Not Covered
ScrWaitSt->WriteSt	500	Covered	T18
WriteSt->ErrorSt	657	Not Covered
WriteSt->IdleSt	413	Covered	T18
WriteSt->WriteWaitSt	408	Covered	T18
WriteWaitSt->ErrorSt	438	Covered	T18
WriteWaitSt->IdleSt	443	Covered	T18

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	9	8	88.89
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	310	Covered	T18
FsmStateError	355	Covered	T18
MacroEccCorrError	343	Covered	T18
NoError	264	Covered	T18

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->FsmStateError	355	Covered	T18
AccessError->MacroEccCorrError	343	Excluded		VC_COV_UNR
AccessError->NoError	264	Covered	T18
FsmStateError->AccessError	310	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	343	Excluded		VC_COV_UNR
FsmStateError->NoError	264	Covered	T18
MacroEccCorrError->AccessError	310	Not Covered
MacroEccCorrError->FsmStateError	355	Covered	T18
MacroEccCorrError->NoError	264	Covered	T18
NoError->AccessError	310	Covered	T18
NoError->FsmStateError	355	Covered	T18
NoError->MacroEccCorrError	343	Covered	T18

---

Branch Coverage for Instance : tb.dut.u_otp_ctrl_dai

	Line No.	Total	Covered	Percent
Branches		85	74	87.06
TERNARY	171	2	2	100.00
CASE	212	68	57	83.82
IF	656	3	3	100.00
IF	724	4	4	100.00
IF	768	2	2	100.00
IF	771	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_dai.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	171	((state_q == IdleSt)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	212	case (state_q)
-2-:	222	if (init_req_i)
-3-:	224	if (otp_gnt_i)
-4-:	236	if (otp_rvalid_i)
-5-:	237	if ((!(otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	253	if ((part_init_done_i == {otp_ctrl_reg_pkg::NumPart {1'b1}}))
-7-:	262	if (dai_req_i)
-8-:	266	case (dai_cmd_i)
-9-:	279	if (otp_ctrl_part_pkg::PartInfo[part_idx].secret)
-10-:	300	if ((prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx]))))
-11-:	305	if (otp_gnt_i)
-12-:	321	if ((prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) || (otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (otp_addr_o == digest_addr_lut[part_idx]))))
-13-:	324	if (otp_rvalid_i)
-14-:	327	if ((((!otp_ctrl_part_pkg::PartInfo[part_idx].ecc_fatal) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-15-:	331	if ((otp_ctrl_part_pkg::PartInfo[part_idx].secret && (otp_addr_o != digest_addr_lut[part_idx])))
-16-:	342	if ((otp_err_e'(otp_err_i) != NoError))
-17-:	369	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-18-:	381	if (scrmbl_valid_i)
-19-:	396	if ((prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset)))))
-20-:	407	if (otp_gnt_i)
-21-:	425	if ((prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock) && ((((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == PartOffset)) && (otp_addr_o == digest_addr_lut[part_idx])) || ((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))) || ((otp_ctrl_part_pkg::PartInfo[part_idx].variant != Buffered) && (base_sel_q == DaiOffset)))))
-22-:	435	if (otp_rvalid_i)
-23-:	437	if ((!(otp_err_e'(otp_err_i) inside {NoError, MacroWriteBlankError})))
-24-:	446	if ((otp_err_e'(otp_err_i) == MacroWriteBlankError))
-25-:	468	if ((prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))))
-26-:	477	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-:	493	if ((prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock) && (((((otp_ctrl_part_pkg::PartInfo[part_idx].variant == Buffered) && otp_ctrl_part_pkg::PartInfo[part_idx].secret) && otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest) && (base_sel_q == DaiOffset)) && (otp_addr_o < digest_addr_lut[part_idx]))))
-28-:	499	if (scrmbl_valid_i)
-29-:	519	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-30-:	529	if ((prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].read_lock) && prim_mubi_pkg::mubi8_test_false_strict(part_access_i[part_idx].write_lock)))
-31-:	533	if (otp_gnt_i)
-32-:	550	if (otp_rvalid_i)
-33-:	553	if ((!(otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-34-:	560	if ((otp_err_e'(otp_err_i) == MacroEccCorrError))
-35-:	575	if ((otp_addr_o == digest_addr_lut[part_idx]))
-36-:	577	if ((!cnt[0]))
-37-:	579	if (scrmbl_ready_i)
-38-:	583	if (scrmbl_ready_i)
-39-:	588	if ((!cnt[0]))
-40-:	592	if (scrmbl_ready_i)
-41-:	605	if (scrmbl_ready_i)
-42-:	616	if (scrmbl_ready_i)
-43-:	630	if (scrmbl_valid_i)
-44-:	640	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	-41-	-42-	-43-	-44-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitOtpSt	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitOtpSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitOtpSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitPartSt	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitPartSt	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	DaiRead	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	DaiWrite	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	DaiWrite	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	DaiDigest	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T12,T95
ReadSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	1	1	1	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T57
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	1	1	1	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DescrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
DescrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T102,T12
DescrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
DescrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T12,T95
WriteSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T130,T35
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
WriteWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T102,T12
ScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T7
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
DigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T102,T12
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T35,T12,T95
DigReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T15
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	Not Covered
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
DigReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	Not Covered
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	Covered	T1,T2,T15
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	Covered	T1,T2,T15
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
DigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
DigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T2,T15
DigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T2,T3
DigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
DigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	656	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	659	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	724	if (otp_ctrl_part_pkg::PartInfo[part_idx].secret)
-2-:	728	if ((otp_ctrl_part_pkg::PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset)))
-3-:	732	if (((base_sel_q == DaiOffset) && ({dai_addr_i[(otp_ctrl_reg_pkg::OtpByteAddrWidth - 1):3], 2'b0} == digest_addr_lut[part_idx])))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	768	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	771	if ((!rst_ni))
-2-:	780	if (data_clr)
-3-:	782	if (data_en)
-4-:	783	if ((data_sel == ScrmblData))
-5-:	785	if ((data_sel == DaiData))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	1	-	Covered	T1,T2,T3
0	0	1	0	1	Covered	T1,T2,T3
0	0	1	0	0	Covered	T1,T2,T3
0	0	0	-	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_otp_ctrl_dai

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	30	30	100.00	30	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	30	30	100.00	30	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckNativeOtpWidth0_A	1155	1155	0	0
CheckNativeOtpWidth1_A	1155	1155	0	0
DaiIdleKnown_A	1907808725	1906948445	0	0
DaiRdataKnown_A	1907808725	1906948445	0	0
ErrorKnown_A	1907808725	1906948445	0	0
InitDoneKnown_A	1907808725	1906948445	0	0
OtpAddrKnown_A	1907808725	1906948445	0	0
OtpCmdKnown_A	1907808725	1906948445	0	0
OtpErrorState_A	1907808725	377	0	0
OtpReqKnown_A	1907808725	1906948445	0	0
OtpSizeKnown_A	1907808725	1906948445	0	0
OtpWdataKnown_A	1907808725	1906948445	0	0
PartInitReqKnown_A	1907808725	1906948445	0	0
PartSelMustBeOnehot_A	1907808725	1906948445	0	0
ScrmblBlockWidthGe8_A	1907808725	1906948445	0	0
ScrmblCmdKnown_A	1907808725	1906948445	0	0
ScrmblDataKnown_A	1907808725	1906948445	0	0
ScrmblModeKnown_A	1907808725	1906948445	0	0
ScrmblMtxReqKnown_A	1907808725	1906948445	0	0
ScrmblSelKnown_A	1907808725	1906948445	0	0
ScrmblValidKnown_A	1907808725	1906948445	0	0
gen_part_sel[0].PartEndMax_A	1155	1155	0	0
gen_part_sel[1].PartEndMax_A	1155	1155	0	0
gen_part_sel[2].PartEndMax_A	1155	1155	0	0
gen_part_sel[3].PartEndMax_A	1155	1155	0	0
gen_part_sel[4].PartEndMax_A	1155	1155	0	0
gen_part_sel[5].PartEndMax_A	1155	1155	0	0
gen_part_sel[6].PartEndMax_A	1155	1155	0	0
gen_part_sel[7].PartEndMax_A	1155	1155	0	0
u_state_regs_A	1907808725	1906948445	0	0

CheckNativeOtpWidth0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

CheckNativeOtpWidth1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

DaiIdleKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

DaiRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	377	0	0
T2	85442	7	0	0
T3	16626	0	0	0
T4	29296	2	0	0
T6	10723	0	0	0
T7	8457	0	0	0
T8	12849	1	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	0	0	0
T13	0	2	0	0
T35	0	4	0	0
T93	0	2	0	0
T94	0	1	0	0
T95	0	1	0	0
T127	0	7	0	0
T130	0	1	0	0
T131	8474	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

PartInitReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ScrmblBlockWidthGe8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ScrmblCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ScrmblDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ScrmblModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ScrmblMtxReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ScrmblSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ScrmblValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

gen_part_sel[0].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_part_sel[1].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_part_sel[2].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_part_sel[3].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_part_sel[4].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_part_sel[5].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_part_sel[6].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

gen_part_sel[7].PartEndMax_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0