Unified Coverage Report :: Module :: otp_ctrl_part_unbuf

Module : otp_ctrl_part_unbuf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.06	98.11	97.78		66.67	97.73	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf	93.17	97.62	95.56		83.33	93.18	96.15
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.17	97.62	95.56		83.33	93.18	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.53	98.44	95.74	97.87	83.33	94.64	97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.76		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	99.57	100.00	100.00	97.87		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.26	100.00	100.00	97.87	91.67	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.76		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	99.57	100.00	100.00	97.87		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.26	100.00	100.00	97.87	91.67	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.76		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	99.57	100.00	100.00	97.87		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
93.17	97.62

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	83	94.32
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	62	92.54
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			==> MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	0	1
210	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	0	1
271	0	1
273	0	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	88	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	67	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=226594821,DigestOffset=1656,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	88	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	67	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
93.17	95.56

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T107,T108

 LINE       197
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T3
-	1	Covered	T6,T107,T108

 LINE       197
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T107,T108

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T107,T108

 LINE       258
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T4
1	0	Covered	T4,T93,T128

 LINE       258
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T4
-	1	Covered	T4,T93,T128

 LINE       258
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T93,T128

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T6,T9
1	Covered	T2,T4,T57

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T21,T22,T23

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T132,T133,T134
1	Covered	T132,T133,T134

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 + Info=226594821,DigestOffset=1656,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T107,T108
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T72,T25,T135

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T127
0	1	Covered	T1,T2,T4
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T6,T8
1	Covered	T2,T4,T57

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T21,T22,T23

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T136,T137,T132
1	Covered	T136,T137,T132

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : otp_ctrl_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T18
IdleSt	199	Covered	T18
InitSt	175	Covered	T18
InitWaitSt	185	Covered	T18
ReadSt	221	Covered	T18
ReadWaitSt	239	Covered	T18
ResetSt	173	Covered	T18

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T18
IdleSt->ReadSt	221	Covered	T18
InitSt->ErrorSt	309	Covered	T18
InitSt->InitWaitSt	185	Covered	T18
InitWaitSt->ErrorSt	209	Covered	T18
InitWaitSt->IdleSt	199	Covered	T18
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T18
ReadSt->ReadWaitSt	239	Covered	T18
ReadWaitSt->ErrorSt	270	Covered	T18
ReadWaitSt->IdleSt	260	Covered	T18
ResetSt->ErrorSt	309	Covered	T18
ResetSt->InitSt	175	Covered	T18

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	20	10	50.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T18
CheckFailError	311	Covered	T18
FsmStateError	283	Covered	T18
MacroEccCorrError	206	Covered	T18
NoError	220	Covered	T18

transitions	Line No.	Covered	Tests
AccessError->CheckFailError	311	Not Covered
AccessError->FsmStateError	319	Covered	T18
AccessError->MacroEccCorrError	206	Not Covered
AccessError->NoError	220	Covered	T18
CheckFailError->AccessError	243	Not Covered
CheckFailError->FsmStateError	319	Not Covered
CheckFailError->MacroEccCorrError	206	Not Covered
CheckFailError->NoError	220	Covered	T18
FsmStateError->AccessError	243	Not Covered
FsmStateError->CheckFailError	311	Not Covered
FsmStateError->MacroEccCorrError	206	Not Covered
FsmStateError->NoError	220	Covered	T18
MacroEccCorrError->AccessError	243	Not Covered
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T18
MacroEccCorrError->NoError	220	Covered	T18
NoError->AccessError	243	Covered	T18
NoError->CheckFailError	311	Covered	T18
NoError->FsmStateError	283	Covered	T18
NoError->MacroEccCorrError	206	Covered	T18

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T25,T135,T62
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T6,T107,T108
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T35,T12,T95
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T2,T4,T57
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T6,T10
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T128,T129,T138
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T137,T133,T134
1	0	Covered	T137,T133,T134
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=226594821,DigestOffset=1656,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T72,T62,T40
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T110,T135,T139
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T35,T95,T96
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T2,T57,T113
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T6,T8
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T2,T4,T127
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T136,T137,T132
1	0	Covered	T136,T137,T132
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.17	93.18

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	41	93.18
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	20	86.96
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b0) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T6,T107,T108
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T35,T12,T13
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T2,T4,T57
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T6,T9
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T132,T133,T134
1	0	Covered	T132,T133,T134
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2147483647	2147483647	0	0
DigestKnown_A	2147483647	2147483647	0	0
DigestOffsetMustBeRepresentable_A	3465	3465	0	0
EccErrorState_A	2147483647	75227	0	0
ErrorKnown_A	2147483647	2147483647	0	0
FsmStateKnown_A	2147483647	2147483647	0	0
InitDoneKnown_A	2147483647	2147483647	0	0
InitReadLocksPartition_A	2147483647	1172733758	0	0
InitWriteLocksPartition_A	2147483647	1172733758	0	0
OffsetMustBeBlockAligned_A	3465	3465	0	0
OtpAddrKnown_A	2147483647	2147483647	0	0
OtpCmdKnown_A	2147483647	2147483647	0	0
OtpErrorState_A	2147483647	133	0	0
OtpReqKnown_A	2147483647	2147483647	0	0
OtpSizeKnown_A	2147483647	2147483647	0	0
OtpWdataKnown_A	2147483647	2147483647	0	0
ReadLockPropagation_A	2147483647	2147483647	0	0
SizeMustBeBlockAligned_A	3465	3465	0	0
TlulGntKnown_A	2147483647	2147483647	0	0
TlulRdataKnown_A	2147483647	2147483647	0	0
TlulReadOnReadLock_A	2147483647	32564	0	0
TlulRerrorKnown_A	2147483647	2147483647	0	0
TlulRvalidKnown_A	2147483647	2147483647	0	0
WriteLockPropagation_A	2147483647	4012990	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2147483647	58490581	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3465	3465	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0
T11	3	3	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	75227	0	0
T28	18524	0	0	0
T64	13308	0	0	0
T132	10441	6266	0	0
T133	0	5594	0	0
T134	0	9063	0	0
T136	15568	3867	0	0
T137	11339	5580	0	0
T140	0	2129	0	0
T141	0	2517	0	0
T142	0	2790	0	0
T143	0	2496	0	0
T144	0	2477	0	0
T145	0	11946	0	0
T146	0	7536	0	0
T147	0	3513	0	0
T148	0	3139	0	0
T149	0	2788	0	0
T150	0	3526	0	0
T151	9121	0	0	0
T152	11688	0	0	0
T153	48175	0	0	0
T154	38948	0	0	0
T155	13693	0	0	0
T156	11297	0	0	0
T157	14463	0	0	0
T158	44701	0	0	0
T159	5799	0	0	0
T160	11015	0	0	0
T161	14106	0	0	0
T162	14705	0	0	0
T163	11653	0	0	0
T164	16639	0	0	0
T165	20757	0	0	0
T166	16230	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1172733758	0	0
T1	224238	20922	0	0
T2	256326	10730	0	0
T3	49878	17775	0	0
T4	87888	9332	0	0
T6	32169	10130	0	0
T7	25371	7404	0	0
T8	38547	14328	0	0
T9	26040	510	0	0
T10	35433	15168	0	0
T11	119322	77748	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1172733758	0	0
T1	224238	20922	0	0
T2	256326	10730	0	0
T3	49878	17775	0	0
T4	87888	9332	0	0
T6	32169	10130	0	0
T7	25371	7404	0	0
T8	38547	14328	0	0
T9	26040	510	0	0
T10	35433	15168	0	0
T11	119322	77748	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3465	3465	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0
T11	3	3	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	133	0	0
T2	85442	1	0	0
T3	16626	0	0	0
T4	29296	1	0	0
T6	21446	1	0	0
T7	16914	0	0	0
T8	25698	0	0	0
T9	17360	0	0	0
T10	23622	0	0	0
T11	79548	0	0	0
T15	42761	0	0	0
T16	3968	0	0	0
T107	11581	1	0	0
T108	0	1	0	0
T110	0	1	0	0
T127	0	2	0	0
T128	0	2	0	0
T131	16948	0	0	0
T135	0	1	0	0
T139	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	25502	0	0
T2	256326	1282	0	0
T3	49878	20267	0	0
T4	87888	0	0	0
T6	32169	0	0	0
T7	25371	0	0	0
T8	38547	16140	0	0
T9	26040	0	0	0
T10	35433	0	0	0
T11	119322	8863	0	0
T15	0	1330	0	0
T35	0	175683	0	0
T57	0	18762	0	0
T102	0	19414	0	0
T111	0	1568	0	0
T127	0	6058	0	0
T130	0	67540	0	0
T176	0	9641	0	0
T177	0	31883	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3465	3465	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0
T11	3	3	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32564	0	0
T1	224238	42	0	0
T2	256326	13	0	0
T3	49878	12	0	0
T4	87888	22	0	0
T6	32169	0	0	0
T7	25371	12	0	0
T8	38547	46	0	0
T9	26040	0	0	0
T10	35433	0	0	0
T11	119322	86	0	0
T57	0	22	0	0
T109	0	29	0	0
T131	0	17	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4012990	0	0
T1	224238	13932	0	0
T2	256326	0	0	0
T3	49878	0	0	0
T4	87888	0	0	0
T6	32169	0	0	0
T7	25371	0	0	0
T8	38547	0	0	0
T9	26040	0	0	0
T10	35433	0	0	0
T11	119322	0	0	0
T30	0	1379	0	0
T35	0	19848	0	0
T54	0	637	0	0
T57	0	2850	0	0
T93	0	1855	0	0
T94	0	43592	0	0
T95	0	42266	0	0
T96	0	1952	0	0
T97	0	11348	0	0
T98	0	8516	0	0
T99	0	9470	0	0
T100	0	270	0	0
T101	0	760	0	0
T102	0	24208	0	0
T127	0	4889	0	0
T178	0	6970	0	0
T179	0	2854	0	0
T180	0	4960	0	0
T181	0	8352	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	58490581	0	0
T1	224238	176333	0	0
T2	256326	16998	0	0
T3	49878	2858	0	0
T4	87888	26051	0	0
T6	32169	4803	0	0
T7	25371	0	0	0
T8	38547	0	0	0
T9	26040	0	0	0
T10	35433	0	0	0
T11	119322	61527	0	0
T15	0	18389	0	0
T35	0	203503	0	0
T57	0	163587	0	0
T94	0	165612	0	0
T95	0	62802	0	0
T96	0	23076	0	0
T107	0	7119	0	0
T108	0	7419	0	0
T110	0	4021	0	0
T111	0	4741	0	0
T127	0	22167	0	0
T167	0	3180	0	0
T177	0	3442	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	224238	220437	0	0
T2	256326	250236	0	0
T3	49878	49194	0	0
T4	87888	85926	0	0
T6	32169	31425	0	0
T7	25371	24417	0	0
T8	38547	37770	0	0
T9	26040	25293	0	0
T10	35433	34569	0	0
T11	119322	118017	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		84	82	97.62
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	63	61	96.83
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			==> MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	0	1
210	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270		excluded
			Exclude Annotation: VC_COV_UNR
271		excluded
			Exclude Annotation: VC_COV_UNR
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T107,T108

 LINE       197
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T3
-	1	Covered	T6,T107,T108

 LINE       197
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T107,T108

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T107,T108

 LINE       258
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T4
1	0	Covered	T4,T93,T128

 LINE       258
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T4
-	1	Covered	T4,T93,T128

 LINE       258
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T93,T128

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T6,T9
1	Covered	T2,T4,T57

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T21,T22,T23

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T132,T133,T134
1	Covered	T132,T133,T134

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T18
IdleSt	199	Covered	T18
InitSt	175	Covered	T18
InitWaitSt	185	Covered	T18
ReadSt	221	Covered	T18
ReadWaitSt	239	Covered	T18
ResetSt	173	Covered	T18

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T18
IdleSt->ReadSt	221	Covered	T18
InitSt->ErrorSt	309	Not Covered
InitSt->InitWaitSt	185	Covered	T18
InitWaitSt->ErrorSt	209	Covered	T18
InitWaitSt->IdleSt	199	Covered	T18
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T18
ReadSt->ReadWaitSt	239	Covered	T18
ReadWaitSt->ErrorSt	270	Not Covered
ReadWaitSt->IdleSt	260	Covered	T18
ResetSt->ErrorSt	309	Covered	T18
ResetSt->InitSt	175	Covered	T18

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T18
CheckFailError	311	Covered	T18
FsmStateError	283	Covered	T18
MacroEccCorrError	206	Covered	T18
NoError	220	Covered	T18

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T18
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T18
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Covered	T18
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T18
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T18
MacroEccCorrError->NoError	220	Covered	T18
NoError->AccessError	243	Covered	T18
NoError->CheckFailError	311	Covered	T18
NoError->FsmStateError	283	Covered	T18
NoError->MacroEccCorrError	206	Covered	T18

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	41	93.18
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	20	86.96
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b0) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T6,T107,T108
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T35,T12,T13
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T2,T4,T57
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T6,T9
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T132,T133,T134
1	0	Covered	T132,T133,T134
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	1907808725	1906948445	0	0
DigestKnown_A	1907808725	1906948445	0	0
DigestOffsetMustBeRepresentable_A	1155	1155	0	0
EccErrorState_A	1907808725	30125	0	0
ErrorKnown_A	1907808725	1906948445	0	0
FsmStateKnown_A	1907808725	1906948445	0	0
InitDoneKnown_A	1907808725	1906948445	0	0
InitReadLocksPartition_A	1907808725	390730911	0	0
InitWriteLocksPartition_A	1907808725	390730911	0	0
OffsetMustBeBlockAligned_A	1155	1155	0	0
OtpAddrKnown_A	1907808725	1906948445	0	0
OtpCmdKnown_A	1907808725	1906948445	0	0
OtpErrorState_A	1907808725	0	0	0
OtpReqKnown_A	1907808725	1906948445	0	0
OtpSizeKnown_A	1907808725	1906948445	0	0
OtpWdataKnown_A	1907808725	1906948445	0	0
ReadLockPropagation_A	1907808725	969773524	0	0
SizeMustBeBlockAligned_A	1155	1155	0	0
TlulGntKnown_A	1907808725	1906948445	0	0
TlulRdataKnown_A	1907808725	1906948445	0	0
TlulReadOnReadLock_A	1907808725	10553	0	0
TlulRerrorKnown_A	1907808725	1906948445	0	0
TlulRvalidKnown_A	1907808725	1906948445	0	0
WriteLockPropagation_A	1907808725	538595	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	1907808725	8062951	0	0
u_state_regs_A	1907808725	1906948445	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	30125	0	0
T132	10441	3133	0	0
T133	0	2797	0	0
T134	0	3021	0	0
T140	0	2129	0	0
T141	0	2517	0	0
T144	0	2477	0	0
T145	0	3982	0	0
T146	0	3768	0	0
T147	0	3513	0	0
T149	0	2788	0	0
T158	44701	0	0	0
T159	5799	0	0	0
T160	11015	0	0	0
T161	14106	0	0	0
T162	14705	0	0	0
T163	11653	0	0	0
T164	16639	0	0	0
T165	20757	0	0	0
T166	16230	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	390730911	0	0
T1	74746	6787	0	0
T2	85442	3151	0	0
T3	16626	5874	0	0
T4	29296	2974	0	0
T6	10723	3355	0	0
T7	8457	2417	0	0
T8	12849	4742	0	0
T9	8680	136	0	0
T10	11811	5005	0	0
T11	39774	25831	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	390730911	0	0
T1	74746	6787	0	0
T2	85442	3151	0	0
T3	16626	5874	0	0
T4	29296	2974	0	0
T6	10723	3355	0	0
T7	8457	2417	0	0
T8	12849	4742	0	0
T9	8680	136	0	0
T10	11811	5005	0	0
T11	39774	25831	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	969773524	0	0
T1	74746	7583	0	0
T2	85442	287	0	0
T3	16626	7121	0	0
T4	29296	0	0	0
T6	10723	0	0	0
T7	8457	0	0	0
T8	12849	5944	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	4434	0	0
T15	0	1330	0	0
T57	0	6579	0	0
T111	0	1568	0	0
T127	0	3035	0	0
T130	0	22520	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	10553	0	0
T1	74746	15	0	0
T2	85442	5	0	0
T3	16626	3	0	0
T4	29296	6	0	0
T6	10723	0	0	0
T7	8457	3	0	0
T8	12849	12	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	32	0	0
T57	0	9	0	0
T109	0	10	0	0
T131	0	7	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	538595	0	0
T1	74746	6148	0	0
T2	85442	0	0	0
T3	16626	0	0	0
T4	29296	0	0	0
T6	10723	0	0	0
T7	8457	0	0	0
T8	12849	0	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	0	0	0
T35	0	3743	0	0
T54	0	637	0	0
T94	0	9169	0	0
T95	0	7698	0	0
T100	0	270	0	0
T178	0	6970	0	0
T179	0	2854	0	0
T180	0	4960	0	0
T181	0	8352	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	8062951	0	0
T1	74746	55069	0	0
T2	85442	4783	0	0
T3	16626	0	0	0
T4	29296	0	0	0
T6	10723	2404	0	0
T7	8457	0	0	0
T8	12849	0	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	0	0	0
T35	0	65612	0	0
T94	0	165612	0	0
T95	0	62802	0	0
T96	0	23076	0	0
T107	0	3562	0	0
T108	0	3712	0	0
T167	0	3180	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		87	87	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	66	66	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T107,T108
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T25,T135,T62

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T128,T129,T138
0	1	Covered	T1,T2,T4
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T6,T10
1	Covered	T2,T4,T57

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T21,T22,T23

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T137,T133,T134
1	Covered	T137,T133,T134

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T18
IdleSt	199	Covered	T18
InitSt	175	Covered	T18
InitWaitSt	185	Covered	T18
ReadSt	221	Covered	T18
ReadWaitSt	239	Covered	T18
ResetSt	173	Covered	T18

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T18
IdleSt->ReadSt	221	Covered	T18
InitSt->ErrorSt	309	Covered	T18
InitSt->InitWaitSt	185	Covered	T18
InitWaitSt->ErrorSt	209	Covered	T18
InitWaitSt->IdleSt	199	Covered	T18
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T18
ReadSt->ReadWaitSt	239	Covered	T18
ReadWaitSt->ErrorSt	270	Covered	T18
ReadWaitSt->IdleSt	260	Covered	T18
ResetSt->ErrorSt	309	Covered	T18
ResetSt->InitSt	175	Covered	T18

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T18
CheckFailError	311	Covered	T18
FsmStateError	283	Covered	T18
MacroEccCorrError	206	Covered	T18
NoError	220	Covered	T18

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T18
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T18
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Covered	T18
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T18
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T18
MacroEccCorrError->NoError	220	Covered	T18
NoError->AccessError	243	Covered	T18
NoError->CheckFailError	311	Covered	T18
NoError->FsmStateError	283	Covered	T18
NoError->MacroEccCorrError	206	Covered	T18

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T25,T135,T62
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T6,T107,T108
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T35,T12,T95
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T8
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T2,T4,T57
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T6,T10
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T128,T129,T138
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T137,T133,T134
1	0	Covered	T137,T133,T134
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	1907808725	1906948445	0	0
DigestKnown_A	1907808725	1906948445	0	0
DigestOffsetMustBeRepresentable_A	1155	1155	0	0
EccErrorState_A	1907808725	18225	0	0
ErrorKnown_A	1907808725	1906948445	0	0
FsmStateKnown_A	1907808725	1906948445	0	0
InitDoneKnown_A	1907808725	1906948445	0	0
InitReadLocksPartition_A	1907808725	390911609	0	0
InitWriteLocksPartition_A	1907808725	390911609	0	0
OffsetMustBeBlockAligned_A	1155	1155	0	0
OtpAddrKnown_A	1907808725	1906948445	0	0
OtpCmdKnown_A	1907808725	1906948445	0	0
OtpErrorState_A	1907808725	72	0	0
OtpReqKnown_A	1907808725	1906948445	0	0
OtpSizeKnown_A	1907808725	1906948445	0	0
OtpWdataKnown_A	1907808725	1906948445	0	0
ReadLockPropagation_A	1907808725	1010575826	0	0
SizeMustBeBlockAligned_A	1155	1155	0	0
TlulGntKnown_A	1907808725	1906948445	0	0
TlulRdataKnown_A	1907808725	1906948445	0	0
TlulReadOnReadLock_A	1907808725	11051	0	0
TlulRerrorKnown_A	1907808725	1906948445	0	0
TlulRvalidKnown_A	1907808725	1906948445	0	0
WriteLockPropagation_A	1907808725	1554474	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	1907808725	26145127	0	0
u_state_regs_A	1907808725	1906948445	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	18225	0	0
T28	18524	0	0	0
T64	13308	0	0	0
T133	0	2797	0	0
T134	0	3021	0	0
T137	11339	2790	0	0
T143	0	2496	0	0
T145	0	3982	0	0
T148	0	3139	0	0
T151	9121	0	0	0
T152	11688	0	0	0
T153	48175	0	0	0
T154	38948	0	0	0
T155	13693	0	0	0
T156	11297	0	0	0
T157	14463	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	390911609	0	0
T1	74746	6974	0	0
T2	85442	3576	0	0
T3	16626	5925	0	0
T4	29296	3110	0	0
T6	10723	3379	0	0
T7	8457	2468	0	0
T8	12849	4776	0	0
T9	8680	170	0	0
T10	11811	5056	0	0
T11	39774	25916	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	390911609	0	0
T1	74746	6974	0	0
T2	85442	3576	0	0
T3	16626	5925	0	0
T4	29296	3110	0	0
T6	10723	3379	0	0
T7	8457	2468	0	0
T8	12849	4776	0	0
T9	8680	170	0	0
T10	11811	5056	0	0
T11	39774	25916	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	72	0	0
T6	10723	1	0	0
T7	8457	0	0	0
T8	12849	0	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	0	0	0
T15	42761	0	0	0
T16	3968	0	0	0
T107	11581	1	0	0
T108	0	1	0	0
T128	0	1	0	0
T131	8474	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1010575826	0	0
T1	74746	8635	0	0
T2	85442	641	0	0
T3	16626	6038	0	0
T4	29296	0	0	0
T6	10723	0	0	0
T7	8457	0	0	0
T8	12849	5099	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	4429	0	0
T35	0	97815	0	0
T57	0	5944	0	0
T130	0	22512	0	0
T176	0	9641	0	0
T177	0	16011	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	11051	0	0
T1	74746	10	0	0
T2	85442	5	0	0
T3	16626	4	0	0
T4	29296	10	0	0
T6	10723	0	0	0
T7	8457	5	0	0
T8	12849	14	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	23	0	0
T57	0	4	0	0
T109	0	12	0	0
T131	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1554474	0	0
T1	74746	4487	0	0
T2	85442	0	0	0
T3	16626	0	0	0
T4	29296	0	0	0
T6	10723	0	0	0
T7	8457	0	0	0
T8	12849	0	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	0	0	0
T30	0	1379	0	0
T35	0	11022	0	0
T57	0	1425	0	0
T94	0	9860	0	0
T95	0	30043	0	0
T98	0	8516	0	0
T101	0	760	0	0
T102	0	19859	0	0
T127	0	4889	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	26145127	0	0
T1	74746	60717	0	0
T2	85442	0	0	0
T3	16626	2858	0	0
T4	29296	15491	0	0
T6	10723	2399	0	0
T7	8457	0	0	0
T8	12849	0	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	30789	0	0
T15	0	18389	0	0
T57	0	81921	0	0
T107	0	3557	0	0
T108	0	3707	0	0
T111	0	2379	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		87	87	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	66	66	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T110,T135,T139
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T72,T62,T40

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T127
0	1	Covered	T1,T2,T6
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T6,T8
1	Covered	T2,T57,T113

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T21,T22,T23

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T136,T137,T132
1	Covered	T136,T137,T132

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T6

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T18
IdleSt	199	Covered	T18
InitSt	175	Covered	T18
InitWaitSt	185	Covered	T18
ReadSt	221	Covered	T18
ReadWaitSt	239	Covered	T18
ResetSt	173	Covered	T18

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T18
IdleSt->ReadSt	221	Covered	T18
InitSt->ErrorSt	309	Covered	T18
InitSt->InitWaitSt	185	Covered	T18
InitWaitSt->ErrorSt	209	Covered	T18
InitWaitSt->IdleSt	199	Covered	T18
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T18
ReadSt->ReadWaitSt	239	Covered	T18
ReadWaitSt->ErrorSt	270	Covered	T18
ReadWaitSt->IdleSt	260	Covered	T18
ResetSt->ErrorSt	309	Covered	T18
ResetSt->InitSt	175	Covered	T18

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T18
CheckFailError	311	Covered	T18
FsmStateError	283	Covered	T18
MacroEccCorrError	206	Covered	T18
NoError	220	Covered	T18

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T18
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T18
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Covered	T18
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T18
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T18
MacroEccCorrError->NoError	220	Covered	T18
NoError->AccessError	243	Covered	T18
NoError->CheckFailError	311	Covered	T18
NoError->FsmStateError	283	Covered	T18
NoError->MacroEccCorrError	206	Covered	T18

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T72,T62,T40
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T110,T135,T139
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T35,T95,T96
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T2,T57,T113
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T6,T8
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T2,T4,T127
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T136,T137,T132
1	0	Covered	T136,T137,T132
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	1907808725	1906948445	0	0
DigestKnown_A	1907808725	1906948445	0	0
DigestOffsetMustBeRepresentable_A	1155	1155	0	0
EccErrorState_A	1907808725	26877	0	0
ErrorKnown_A	1907808725	1906948445	0	0
FsmStateKnown_A	1907808725	1906948445	0	0
InitDoneKnown_A	1907808725	1906948445	0	0
InitReadLocksPartition_A	1907808725	391091238	0	0
InitWriteLocksPartition_A	1907808725	391091238	0	0
OffsetMustBeBlockAligned_A	1155	1155	0	0
OtpAddrKnown_A	1907808725	1906948445	0	0
OtpCmdKnown_A	1907808725	1906948445	0	0
OtpErrorState_A	1907808725	61	0	0
OtpReqKnown_A	1907808725	1906948445	0	0
OtpSizeKnown_A	1907808725	1906948445	0	0
OtpWdataKnown_A	1907808725	1906948445	0	0
ReadLockPropagation_A	1907808725	948242795	0	0
SizeMustBeBlockAligned_A	1155	1155	0	0
TlulGntKnown_A	1907808725	1906948445	0	0
TlulRdataKnown_A	1907808725	1906948445	0	0
TlulReadOnReadLock_A	1907808725	10960	0	0
TlulRerrorKnown_A	1907808725	1906948445	0	0
TlulRvalidKnown_A	1907808725	1906948445	0	0
WriteLockPropagation_A	1907808725	1919921	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	1907808725	24282503	0	0
u_state_regs_A	1907808725	1906948445	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	26877	0	0
T12	393152	0	0	0
T13	232981	0	0	0
T25	10655	0	0	0
T93	65685	0	0	0
T94	463639	0	0	0
T95	513147	0	0	0
T113	14733	0	0	0
T132	0	3133	0	0
T134	0	3021	0	0
T136	15568	3867	0	0
T137	0	2790	0	0
T142	0	2790	0	0
T145	0	3982	0	0
T146	0	3768	0	0
T150	0	3526	0	0
T168	13008	0	0	0
T182	10031	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	391091238	0	0
T1	74746	7161	0	0
T2	85442	4003	0	0
T3	16626	5976	0	0
T4	29296	3248	0	0
T6	10723	3396	0	0
T7	8457	2519	0	0
T8	12849	4810	0	0
T9	8680	204	0	0
T10	11811	5107	0	0
T11	39774	26001	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	391091238	0	0
T1	74746	7161	0	0
T2	85442	4003	0	0
T3	16626	5976	0	0
T4	29296	3248	0	0
T6	10723	3396	0	0
T7	8457	2519	0	0
T8	12849	4810	0	0
T9	8680	204	0	0
T10	11811	5107	0	0
T11	39774	26001	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	61	0	0
T2	85442	1	0	0
T3	16626	0	0	0
T4	29296	1	0	0
T6	10723	0	0	0
T7	8457	0	0	0
T8	12849	0	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	0	0	0
T110	0	1	0	0
T127	0	2	0	0
T128	0	1	0	0
T131	8474	0	0	0
T135	0	1	0	0
T139	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	948242795	0	0
T1	74746	9284	0	0
T2	85442	354	0	0
T3	16626	7108	0	0
T4	29296	0	0	0
T6	10723	0	0	0
T7	8457	0	0	0
T8	12849	5097	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	0	0	0
T35	0	77868	0	0
T57	0	6239	0	0
T102	0	19414	0	0
T127	0	3023	0	0
T130	0	22508	0	0
T177	0	15872	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	10960	0	0
T1	74746	17	0	0
T2	85442	3	0	0
T3	16626	5	0	0
T4	29296	6	0	0
T6	10723	0	0	0
T7	8457	4	0	0
T8	12849	20	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	31	0	0
T57	0	9	0	0
T109	0	7	0	0
T131	0	8	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1919921	0	0
T1	74746	3297	0	0
T2	85442	0	0	0
T3	16626	0	0	0
T4	29296	0	0	0
T6	10723	0	0	0
T7	8457	0	0	0
T8	12849	0	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	0	0	0
T35	0	5083	0	0
T57	0	1425	0	0
T93	0	1855	0	0
T94	0	24563	0	0
T95	0	4525	0	0
T96	0	1952	0	0
T97	0	11348	0	0
T99	0	9470	0	0
T102	0	4349	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	24282503	0	0
T1	74746	60547	0	0
T2	85442	12215	0	0
T3	16626	0	0	0
T4	29296	10560	0	0
T6	10723	0	0	0
T7	8457	0	0	0
T8	12849	0	0	0
T9	8680	0	0	0
T10	11811	0	0	0
T11	39774	30738	0	0
T35	0	137891	0	0
T57	0	81666	0	0
T110	0	4021	0	0
T111	0	2362	0	0
T127	0	22167	0	0
T177	0	3442	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907808725	1906948445	0	0
T1	74746	73479	0	0
T2	85442	83412	0	0
T3	16626	16398	0	0
T4	29296	28642	0	0
T6	10723	10475	0	0
T7	8457	8139	0	0
T8	12849	12590	0	0
T9	8680	8431	0	0
T10	11811	11523	0	0
T11	39774	39339	0	0