Module : prim_sec_anchor_buf
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sec_anchor_0.1/rtl/prim_sec_anchor_buf.sv
Module self-instances :
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[1].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[1].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[1].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[1].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[2].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[2].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[2].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[2].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[3].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[3].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[3].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[3].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[4].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[4].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[4].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[4].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[5].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[5].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[5].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[5].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[6].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[6].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[6].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[6].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[7].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[7].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[7].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[7].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[8].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[8].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[8].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[8].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[9].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[9].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[9].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[9].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[10].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[10].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[10].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[10].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[11].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[11].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[11].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[11].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[12].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[12].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[12].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[12].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[13].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[13].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[13].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[13].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[14].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[14].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[14].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[14].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[15].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[15].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[15].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_buffs[15].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_creator_seed_sw_rw_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_creator_seed_sw_rw_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_creator_seed_sw_rw_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_creator_seed_sw_rw_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_owner_seed_sw_rw_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_owner_seed_sw_rw_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_owner_seed_sw_rw_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_owner_seed_sw_rw_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_seed_hw_rd_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_seed_hw_rd_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_seed_hw_rd_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_seed_hw_rd_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[1].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[1].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[1].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[1].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[2].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[2].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[2].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[2].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_check_byp_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_check_byp_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_check_byp_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_check_byp_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_check_byp_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_check_byp_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sync_check_byp_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_prim_lc_sync_check_byp_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_err_en_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_err_en_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_err_en_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_err_en_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_err_en_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_err_en_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_err_en_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | u_err_en_sync |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_otp_ctrl_scrmbl.gen_anchor_keys[0].u_key_anchor_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_otp_ctrl_scrmbl |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_otp_ctrl_scrmbl.gen_anchor_keys[1].u_key_anchor_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_otp_ctrl_scrmbl |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_otp_ctrl_scrmbl.gen_anchor_keys[2].u_key_anchor_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_otp_ctrl_scrmbl |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_otp_ctrl_scrmbl.gen_anchor_digests[0].u_const_anchor_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_otp_ctrl_scrmbl |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_otp_ctrl_scrmbl.gen_anchor_digests[0].u_iv_anchor_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_otp_ctrl_scrmbl |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_otp_ctrl_scrmbl.gen_anchor_digests[1].u_const_anchor_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_otp_ctrl_scrmbl |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_otp_ctrl_scrmbl.gen_anchor_digests[1].u_iv_anchor_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_otp_ctrl_scrmbl |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_otp_ctrl_scrmbl.gen_anchor_digests[2].u_const_anchor_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_otp_ctrl_scrmbl |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_otp_ctrl_scrmbl.gen_anchor_digests[2].u_iv_anchor_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_otp_ctrl_scrmbl |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_otp_ctrl_scrmbl.gen_anchor_digests[3].u_const_anchor_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_otp_ctrl_scrmbl |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_otp_ctrl_scrmbl.gen_anchor_digests[3].u_iv_anchor_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_otp_ctrl_scrmbl |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_otp_ctrl_kdi.u_flash_data_key_anchor
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_otp_ctrl_kdi |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_otp_ctrl_kdi.u_flash_addr_key_anchor
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_otp_ctrl_kdi |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_otp_ctrl_kdi.u_sram_data_key_anchor
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | u_otp_ctrl_kdi |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sender_test_tokens_valid.gen_no_flops.gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | u_prim_lc_sender_test_tokens_valid |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sender_test_tokens_valid.gen_no_flops.gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | u_prim_lc_sender_test_tokens_valid |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sender_test_tokens_valid.gen_no_flops.gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | u_prim_lc_sender_test_tokens_valid |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sender_test_tokens_valid.gen_no_flops.gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | u_prim_lc_sender_test_tokens_valid |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sender_rma_token_valid.gen_no_flops.gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | u_prim_lc_sender_rma_token_valid |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sender_rma_token_valid.gen_no_flops.gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | u_prim_lc_sender_rma_token_valid |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sender_rma_token_valid.gen_no_flops.gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | u_prim_lc_sender_rma_token_valid |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sender_rma_token_valid.gen_no_flops.gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | u_prim_lc_sender_rma_token_valid |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sender_secrets_valid.gen_no_flops.gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | u_prim_lc_sender_secrets_valid |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sender_secrets_valid.gen_no_flops.gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | u_prim_lc_sender_secrets_valid |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sender_secrets_valid.gen_no_flops.gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | u_prim_lc_sender_secrets_valid |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |
Module Instance : tb.dut.u_prim_lc_sender_secrets_valid.gen_no_flops.gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 0.00 | 0.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 0.00 | 0.00 | 0.00 | u_prim_lc_sender_secrets_valid |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_secure_anchor_buf | 0.00 | 0.00 |