PATTGEN Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: 213e792ea

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2340441291

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 9.000s 336.850us 50 50 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 2.000s 16.446us 5 5 100.00
V1 csr_rw pattgen_csr_rw 3.000s 32.790us 20 20 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 5.000s 126.375us 5 5 100.00
V1 csr_aliasing pattgen_csr_aliasing 3.000s 61.922us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 4.000s 44.243us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 3.000s 32.790us 20 20 100.00
pattgen_csr_aliasing 3.000s 61.922us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 perf pattgen_perf 2.650m 56.335ms 50 50 100.00
V2 cnt_rollover cnt_rollover 1.883m 11.443ms 50 50 100.00
V2 error pattgen_error 4.000s 29.075us 50 50 100.00
V2 stress_all pattgen_stress_all 4.483m 27.989ms 50 50 100.00
V2 alert_test pattgen_alert_test 4.000s 22.882us 50 50 100.00
V2 intr_test pattgen_intr_test 4.000s 14.031us 50 50 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 5.000s 76.200us 20 20 100.00
V2 tl_d_illegal_access pattgen_tl_errors 5.000s 76.200us 20 20 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 2.000s 16.446us 5 5 100.00
pattgen_csr_rw 3.000s 32.790us 20 20 100.00
pattgen_csr_aliasing 3.000s 61.922us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 29.460us 20 20 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 2.000s 16.446us 5 5 100.00
pattgen_csr_rw 3.000s 32.790us 20 20 100.00
pattgen_csr_aliasing 3.000s 61.922us 5 5 100.00
pattgen_same_csr_outstanding 3.000s 29.460us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err pattgen_tl_intg_err 4.000s 48.549us 20 20 100.00
pattgen_sec_cm 3.000s 60.911us 5 5 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 4.000s 48.549us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 30.717m 221.648ms 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 517 520 99.42

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.81 100.00 100.00 100.00 99.06 96.13 -- 100.00 90.43

Failure Buckets

Past Results