877a77116
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pattgen_smoke | 8.000s | 158.037us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pattgen_csr_hw_reset | 3.000s | 47.032us | 5 | 5 | 100.00 |
V1 | csr_rw | pattgen_csr_rw | 5.000s | 17.351us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pattgen_csr_bit_bash | 5.000s | 2.043ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | pattgen_csr_aliasing | 3.000s | 43.701us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 5.000s | 20.205us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 5.000s | 17.351us | 20 | 20 | 100.00 |
pattgen_csr_aliasing | 3.000s | 43.701us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | perf | pattgen_perf | 2.650m | 3.948ms | 50 | 50 | 100.00 |
V2 | cnt_rollover | cnt_rollover | 1.683m | 2.742ms | 50 | 50 | 100.00 |
V2 | error | pattgen_error | 4.000s | 39.296us | 50 | 50 | 100.00 |
V2 | stress_all | pattgen_stress_all | 1.850m | 5.379ms | 50 | 50 | 100.00 |
V2 | alert_test | pattgen_alert_test | 3.000s | 66.957us | 50 | 50 | 100.00 |
V2 | intr_test | pattgen_intr_test | 3.000s | 28.628us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pattgen_tl_errors | 7.000s | 221.547us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pattgen_tl_errors | 7.000s | 221.547us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 3.000s | 47.032us | 5 | 5 | 100.00 |
pattgen_csr_rw | 5.000s | 17.351us | 20 | 20 | 100.00 | ||
pattgen_csr_aliasing | 3.000s | 43.701us | 5 | 5 | 100.00 | ||
pattgen_same_csr_outstanding | 4.000s | 26.016us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pattgen_csr_hw_reset | 3.000s | 47.032us | 5 | 5 | 100.00 |
pattgen_csr_rw | 5.000s | 17.351us | 20 | 20 | 100.00 | ||
pattgen_csr_aliasing | 3.000s | 43.701us | 5 | 5 | 100.00 | ||
pattgen_same_csr_outstanding | 4.000s | 26.016us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 340 | 340 | 100.00 | |||
V2S | tl_intg_err | pattgen_tl_intg_err | 4.000s | 238.007us | 20 | 20 | 100.00 |
pattgen_sec_cm | 3.000s | 115.383us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 4.000s | 238.007us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 34.317m | 204.529ms | 47 | 50 | 94.00 |
V3 | TOTAL | 47 | 50 | 94.00 | |||
TOTAL | 517 | 520 | 99.42 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 8 | 8 | 8 | 100.00 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.81 | 100.00 | 100.00 | 100.00 | 99.06 | 96.13 | -- | 100.00 | 90.43 |
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard]
has 3 failures:
9.pattgen_stress_all_with_rand_reset.2663205583
Line 885, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36152596111 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
31.pattgen_stress_all_with_rand_reset.3380953437
Line 467, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/31.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13597416898 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
... and 1 more failures.