0c759b93ab| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 17.000s | 85.269us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 7.000s | 13.317us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 7.000s | 46.008us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 8.000s | 573.658us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 8.000s | 30.643us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 10.000s | 23.397us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 7.000s | 46.008us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 8.000s | 30.643us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 2.600m | 16.432ms | 50 | 50 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 1.833m | 10.110ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 16.000s | 91.746us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 3.650m | 10.637ms | 50 | 50 | 100.00 |
| V2 | alert_test | pattgen_alert_test | 19.000s | 34.824us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 16.000s | 38.822us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 17.000s | 178.594us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 17.000s | 178.594us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 7.000s | 13.317us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 7.000s | 46.008us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 8.000s | 30.643us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 12.000s | 49.935us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 7.000s | 13.317us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 7.000s | 46.008us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 8.000s | 30.643us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 12.000s | 49.935us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 340 | 340 | 100.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 10.000s | 59.950us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 6.000s | 35.371us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 10.000s | 59.950us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 46.283m | 279.824ms | 44 | 50 | 88.00 |
| V3 | TOTAL | 44 | 50 | 88.00 | |||
| TOTAL | 514 | 520 | 98.85 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 8 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.79 | 100.00 | 100.00 | 100.00 | 99.06 | 96.13 | -- | 100.00 | 90.43 |
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
4.pattgen_stress_all_with_rand_reset.12933198971710488094984479062931602904728202979609464291787463489560901758995
Line 497, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 26908943840 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
13.pattgen_stress_all_with_rand_reset.88668740816752375293285827910378142724591952032387126747499823938282536614960
Line 572, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/13.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 90030575432 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
... and 4 more failures.