PWM Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	6.000s	522.200us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	87.975us	5	5	100.00
V1	csr_rw	pwm_csr_rw	4.000s	14.741us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	13.000s	2.766ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	308.595us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	5.000s	136.290us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	4.000s	14.741us	20	20	100.00
		pwm_csr_aliasing	5.000s	308.595us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	59.000s	52.488ms	49	50	98.00
V2	pulse	pwm_rand_output	59.000s	52.488ms	49	50	98.00
V2	blink	pwm_rand_output	59.000s	52.488ms	49	50	98.00
V2	heartbeat	pwm_rand_output	59.000s	52.488ms	49	50	98.00
V2	resolution	pwm_rand_output	59.000s	52.488ms	49	50	98.00
V2	multi_channel	pwm_rand_output	59.000s	52.488ms	49	50	98.00
V2	polarity	pwm_rand_output	59.000s	52.488ms	49	50	98.00
V2	phase	pwm_rand_output	59.000s	52.488ms	49	50	98.00
V2	lowpower	pwm_rand_output	59.000s	52.488ms	49	50	98.00
V2	perf	pwm_perf	51.000s	10.611ms	49	50	98.00
V2	stress_all	pwm_stress_all	4.433m	317.496ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	23.617us	50	50	100.00
V2	intr_test	pwm_intr_test	4.000s	13.654us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	8.000s	456.109us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	8.000s	456.109us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	87.975us	5	5	100.00
		pwm_csr_rw	4.000s	14.741us	20	20	100.00
		pwm_csr_aliasing	5.000s	308.595us	5	5	100.00
		pwm_same_csr_outstanding	5.000s	60.164us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	87.975us	5	5	100.00
		pwm_csr_rw	4.000s	14.741us	20	20	100.00
		pwm_csr_aliasing	5.000s	308.595us	5	5	100.00
		pwm_same_csr_outstanding	5.000s	60.164us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	pwm_tl_intg_err	7.000s	142.947us	20	20	100.00
		pwm_sec_cm	2.000s	570.593us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	7.000s	142.947us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			416	420	99.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	4	57.14
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.23	99.19	98.52	99.80	94.45	94.92	--	100.00	99.34

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test pwm_perf has 1 failures.

29.pwm_perf.905600655
Line 354, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/29.pwm_perf/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test pwm_rand_output has 1 failures.

39.pwm_rand_output.421155821
Line 6117, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/39.pwm_rand_output/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

38.pwm_stress_all.944716811
Line 578, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/38.pwm_stress_all/latest/run.log

  UVM_ERROR @ 11364035199 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [1] did not MATCH
  UVM_INFO @ 11364035199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.pwm_stress_all.1501188068
Line 998, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/45.pwm_stress_all/latest/run.log

  UVM_ERROR @ 249942370884 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [3] did not MATCH
  UVM_INFO @ 249942370884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---