PWRMGR Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.760s	33.436us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.730s	56.872us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.700s	22.149us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.310s	344.181us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.980s	40.319us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.410s	97.450us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.700s	22.149us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	40.319us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.470s	207.775us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.470s	207.775us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.830s	68.659us	50	50	100.00
		pwrmgr_lowpower_invalid	0.760s	45.682us	50	50	100.00
V2	reset	pwrmgr_reset	1.460s	97.442us	50	50	100.00
		pwrmgr_reset_invalid	1.170s	108.060us	49	50	98.00
V2	main_power_glitch_reset	pwrmgr_reset	1.460s	97.442us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.790s	307.535us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.410s	209.526us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.950s	54.524us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.370s	1.764ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.710s	22.960us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.900s	539.457us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.900s	539.457us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.730s	56.872us	5	5	100.00
		pwrmgr_csr_rw	0.700s	22.149us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	40.319us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	39.020us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.730s	56.872us	5	5	100.00
		pwrmgr_csr_rw	0.700s	22.149us	20	20	100.00
		pwrmgr_csr_aliasing	0.980s	40.319us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.930s	39.020us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.610s	207.742us	20	20	100.00
		pwrmgr_sec_cm	2.070s	684.959us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.070s	684.959us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.070s	684.959us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.610s	207.742us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.030s	843.789us	49	50	98.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.370s	816.191us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.960s	79.191us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	30.172us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.070s	684.959us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.070s	684.959us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.070s	684.959us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.660s	47.794us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	60.626us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.750s	291.516us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.700s	22.149us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.700s	22.149us	20	20	100.00
V2S		TOTAL			374	375	99.73
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	40.500s	8.729ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1068	1070	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	8	88.89
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	98.21	96.58	99.44	96.00	96.27	100.00	99.02

Failure Buckets

Offending '(((!esc_rst_req_d) && (fetch_en_o != On)) || slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx])' has 1 failures:

Test pwrmgr_reset_invalid has 1 failures.

0.pwrmgr_reset_invalid.778722195
Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest/run.log

      Offending '(((!esc_rst_req_d) && (fetch_en_o != On)) || slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx])'
  UVM_ERROR @ 201886972 ps: (pwrmgr.sv:155) [ASSERT FAILED] PwrmgrSecCmEscToSlowResetReq_A
  UVM_INFO @ 201886972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 1 failures.
  - 15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3923550652
    Line 670, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
```
  UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```