PWRMGR Simulation Results

Sunday September 03 2023 19:02:20 UTC

GitHub Revision: `769fa7328`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1741510204

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.710s	32.598us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.650s	30.440us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.670s	22.070us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.790s	485.743us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.950s	24.966us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.430s	50.839us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.670s	22.070us	20	20	100.00
		pwrmgr_csr_aliasing	0.950s	24.966us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.710s	313.805us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.710s	313.805us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.800s	60.907us	50	50	100.00
		pwrmgr_lowpower_invalid	0.780s	43.253us	50	50	100.00
V2	reset	pwrmgr_reset	1.180s	110.095us	50	50	100.00
		pwrmgr_reset_invalid	1.020s	71.419us	0	50	0.00
V2	main_power_glitch_reset	pwrmgr_reset	1.180s	110.095us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.610s	269.740us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.470s	204.179us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.930s	74.920us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	10.660s	2.707ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.630s	22.132us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.540s	161.955us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.540s	161.955us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.650s	30.440us	5	5	100.00
		pwrmgr_csr_rw	0.670s	22.070us	20	20	100.00
		pwrmgr_csr_aliasing	0.950s	24.966us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.870s	149.275us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.650s	30.440us	5	5	100.00
		pwrmgr_csr_rw	0.670s	22.070us	20	20	100.00
		pwrmgr_csr_aliasing	0.950s	24.966us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.870s	149.275us	20	20	100.00
V2		TOTAL			490	540	90.74
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.730s	189.295us	20	20	100.00
		pwrmgr_sec_cm	1.690s	677.476us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.690s	677.476us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.690s	677.476us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.730s	189.295us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.180s	819.556us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.370s	921.963us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.980s	71.923us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.660s	29.479us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.690s	677.476us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.690s	677.476us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.690s	677.476us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.670s	118.918us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.680s	49.283us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.730s	273.180us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.670s	22.070us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.670s	22.070us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	47.280s	10.309ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1019	1070	95.23

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.80	98.22	96.58	99.44	74.00	96.32	100.00	99.02

Failure Buckets

Offending '(fast_state == FastPwrStateRomCheckGood)' has 50 failures:

Test pwrmgr_reset_invalid has 50 failures.

0.pwrmgr_reset_invalid.3399191342
Line 356, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest/run.log

      Offending '(fast_state == FastPwrStateRomCheckGood)'
  UVM_ERROR @  80204426 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
  UVM_INFO @  80204426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_reset_invalid.868625363
Line 305, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest/run.log

      Offending '(fast_state == FastPwrStateRomCheckGood)'
  UVM_ERROR @  77402606 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
  UVM_INFO @  77402606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:
- Test pwrmgr_stress_all_with_rand_reset has 1 failures.
  - 27.pwrmgr_stress_all_with_rand_reset.4034540204
    Line 4342, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest/run.log
```
      Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
  UVM_ERROR @ 15720819468 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
  UVM_INFO @ 15720819468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```