ROM_CTRL Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	36.790s	8.165ms	47	50	94.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.050s	3.273ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	12.140s	6.376ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.250s	2.013ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	13.140s	1.796ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.490s	4.066ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	12.140s	6.376ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.140s	1.796ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.000s	4.101ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.880s	4.645ms	5	5	100.00
V1		TOTAL			112	115	97.39
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	15.530s	8.835ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.981m	12.022ms	47	50	94.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	30.950s	39.907ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	14.690s	2.049ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.760s	1.998ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.760s	1.998ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.050s	3.273ms	5	5	100.00
		rom_ctrl_csr_rw	12.140s	6.376ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.140s	1.796ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.900s	8.346ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.050s	3.273ms	5	5	100.00
		rom_ctrl_csr_rw	12.140s	6.376ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.140s	1.796ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.900s	8.346ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.104m	126.437ms	47	50	94.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	5.260m	160.510ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.617m	4.928ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.202m	14.317ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.617m	4.928ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.104m	126.437ms	47	50	94.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.104m	126.437ms	47	50	94.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.104m	126.437ms	47	50	94.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.104m	126.437ms	47	50	94.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.104m	126.437ms	47	50	94.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.617m	4.928ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.617m	4.928ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	36.790s	8.165ms	47	50	94.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	36.790s	8.165ms	47	50	94.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	36.790s	8.165ms	47	50	94.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.202m	14.317ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.104m	126.437ms	47	50	94.00
		rom_ctrl_kmac_err_chk	30.950s	39.907ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.104m	126.437ms	47	50	94.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.104m	126.437ms	47	50	94.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.104m	126.437ms	47	50	94.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	5.260m	160.510ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.617m	4.928ms	5	5	100.00
V2S		TOTAL			91	95	95.79
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.552h	101.486ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			473	500	94.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	2	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.66	97.16	92.83	97.88	86.67	98.68	98.04	98.38

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 14 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.1638930360
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:d7b4a45d-8e59-4e3a-9780-e03d841803e1
```
  - 4.rom_ctrl_stress_all_with_rand_reset.1060039673
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:a8ea7a3f-67ff-4b11-ab0b-1a15fccfbbe1
```
  - ... and 12 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 9 failures:

Test rom_ctrl_stress_all has 3 failures.

10.rom_ctrl_stress_all.1178031591
Line 220, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/10.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10123307745 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xc4a8d426
  UVM_INFO @ 10123307745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.rom_ctrl_stress_all.492063343
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/34.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10008540220 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x433bb3cb
  UVM_INFO @ 10008540220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rom_ctrl_smoke has 3 failures.

11.rom_ctrl_smoke.1688528888
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10008703922 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x5b6522a4
  UVM_INFO @ 10008703922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.rom_ctrl_smoke.113984512
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/32.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10010709716 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xb8ec0e51
  UVM_INFO @ 10010709716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rom_ctrl_stress_all_with_rand_reset has 3 failures.

21.rom_ctrl_stress_all_with_rand_reset.2874813160
Line 221, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10019841822 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xaf59eba
  UVM_INFO @ 10019841822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.rom_ctrl_stress_all_with_rand_reset.1834306942
Line 222, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/26.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10144350760 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x51d6b5a
  UVM_INFO @ 10144350760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:595) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 2 failures:

Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.

9.rom_ctrl_corrupt_sig_fatal_chk.4098794697
Line 223, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_ERROR @ 202869339 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 202869339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.rom_ctrl_corrupt_sig_fatal_chk.1576419490
Line 224, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/47.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_ERROR @ 508305687 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 508305687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 14.rom_ctrl_passthru_mem_tl_intg_err.488202972
    Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/14.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 10009883819 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x23e90008
  UVM_INFO @ 10009883819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 32.rom_ctrl_corrupt_sig_fatal_chk.4095204756
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```