4e80560e2
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | rom_ctrl_smoke | 43.700s | 4.379ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 15.420s | 1.824ms | 5 | 5 | 100.00 |
V1 | csr_rw | rom_ctrl_csr_rw | 16.890s | 2.129ms | 20 | 20 | 100.00 |
V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 16.520s | 12.725ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | rom_ctrl_csr_aliasing | 15.830s | 10.028ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 17.640s | 2.148ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 16.890s | 2.129ms | 20 | 20 | 100.00 |
rom_ctrl_csr_aliasing | 15.830s | 10.028ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | rom_ctrl_mem_walk | 15.330s | 7.630ms | 5 | 5 | 100.00 |
V1 | mem_partial_access | rom_ctrl_mem_partial_access | 14.070s | 6.032ms | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 17.970s | 26.494ms | 50 | 50 | 100.00 |
V2 | stress_all | rom_ctrl_stress_all | 2.122m | 13.147ms | 50 | 50 | 100.00 |
V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 36.390s | 17.079ms | 50 | 50 | 100.00 |
V2 | alert_test | rom_ctrl_alert_test | 17.090s | 8.259ms | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 21.090s | 4.408ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 21.090s | 4.408ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 15.420s | 1.824ms | 5 | 5 | 100.00 |
rom_ctrl_csr_rw | 16.890s | 2.129ms | 20 | 20 | 100.00 | ||
rom_ctrl_csr_aliasing | 15.830s | 10.028ms | 5 | 5 | 100.00 | ||
rom_ctrl_same_csr_outstanding | 16.620s | 4.186ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 15.420s | 1.824ms | 5 | 5 | 100.00 |
rom_ctrl_csr_rw | 16.890s | 2.129ms | 20 | 20 | 100.00 | ||
rom_ctrl_csr_aliasing | 15.830s | 10.028ms | 5 | 5 | 100.00 | ||
rom_ctrl_same_csr_outstanding | 16.620s | 4.186ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 240 | 240 | 100.00 | |||
V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 9.251m | 56.150ms | 49 | 50 | 98.00 |
V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 6.379m | 175.849ms | 18 | 20 | 90.00 |
V2S | tl_intg_err | rom_ctrl_sec_cm | 1.961m | 10.095ms | 5 | 5 | 100.00 |
rom_ctrl_tl_intg_err | 1.425m | 2.066ms | 20 | 20 | 100.00 | ||
V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.961m | 10.095ms | 5 | 5 | 100.00 |
V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.251m | 56.150ms | 49 | 50 | 98.00 |
V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.251m | 56.150ms | 49 | 50 | 98.00 |
V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 9.251m | 56.150ms | 49 | 50 | 98.00 |
V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.251m | 56.150ms | 49 | 50 | 98.00 |
V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.251m | 56.150ms | 49 | 50 | 98.00 |
V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.961m | 10.095ms | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.961m | 10.095ms | 5 | 5 | 100.00 |
V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 43.700s | 4.379ms | 50 | 50 | 100.00 |
V2S | sec_cm_mem_digest | rom_ctrl_smoke | 43.700s | 4.379ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 43.700s | 4.379ms | 50 | 50 | 100.00 |
V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.425m | 2.066ms | 20 | 20 | 100.00 |
V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 9.251m | 56.150ms | 49 | 50 | 98.00 |
rom_ctrl_kmac_err_chk | 36.390s | 17.079ms | 50 | 50 | 100.00 | ||
V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 9.251m | 56.150ms | 49 | 50 | 98.00 |
V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.251m | 56.150ms | 49 | 50 | 98.00 |
V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 9.251m | 56.150ms | 49 | 50 | 98.00 |
V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 6.379m | 175.849ms | 18 | 20 | 90.00 |
V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.961m | 10.095ms | 5 | 5 | 100.00 |
V2S | TOTAL | 92 | 95 | 96.84 | |||
V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.969h | 47.233ms | 34 | 50 | 68.00 |
V3 | TOTAL | 34 | 50 | 68.00 | |||
TOTAL | 481 | 500 | 96.20 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 6 | 6 | 6 | 100.00 |
V2S | 4 | 4 | 2 | 50.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.72 | 97.11 | 93.12 | 97.88 | 100.00 | 98.69 | 97.89 | 99.30 |
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 13 failures:
1.rom_ctrl_stress_all_with_rand_reset.3875048202
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:a7a46ed8-2073-48f1-b91f-a43fc910f4fc
5.rom_ctrl_stress_all_with_rand_reset.1196642008
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:b50c40e7-7413-4a98-8de6-2e2ad8d16619
... and 11 more failures.
UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=*
has 5 failures:
Test rom_ctrl_passthru_mem_tl_intg_err has 2 failures.
5.rom_ctrl_passthru_mem_tl_intg_err.3888216051
Line 207, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 10013693104 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x878b0004
UVM_INFO @ 10013693104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.rom_ctrl_passthru_mem_tl_intg_err.1519761897
Line 207, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 10013025894 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xf4dd0008
UVM_INFO @ 10013025894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
29.rom_ctrl_stress_all_with_rand_reset.2742504444
Line 209, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/29.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10006566147 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x7a55cc7b
UVM_INFO @ 10006566147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.rom_ctrl_stress_all_with_rand_reset.916326346
Line 209, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10014648642 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x7f4b10da
UVM_INFO @ 10014648642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:595) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
has 1 failures:
32.rom_ctrl_corrupt_sig_fatal_chk.1734617393
Line 207, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/32.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 384845314 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
UVM_INFO @ 384845314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---