ROM_CTRL Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: `0c759b93ab`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	38.090s	3.749ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.410s	2.115ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.860s	1.901ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.670s	4.737ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.280s	7.321ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.680s	27.235ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.860s	1.901ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.280s	7.321ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.810s	2.119ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	16.070s	4.268ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.190s	2.130ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.579m	26.251ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.970s	18.095ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.060s	2.030ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.420s	10.563ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.420s	10.563ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.410s	2.115ms	5	5	100.00
		rom_ctrl_csr_rw	14.860s	1.901ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.280s	7.321ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.060s	7.775ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.410s	2.115ms	5	5	100.00
		rom_ctrl_csr_rw	14.860s	1.901ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.280s	7.321ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	17.060s	7.775ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.794m	339.222ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	5.299m	79.411ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.121m	2.387ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.401m	12.361ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.121m	2.387ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.794m	339.222ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.794m	339.222ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.794m	339.222ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.794m	339.222ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.794m	339.222ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.121m	2.387ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.121m	2.387ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	38.090s	3.749ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	38.090s	3.749ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	38.090s	3.749ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.401m	12.361ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.794m	339.222ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.970s	18.095ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.794m	339.222ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.794m	339.222ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.794m	339.222ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	5.299m	79.411ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.121m	2.387ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.566h	52.503ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			482	500	96.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.60	97.11	92.68	97.88	100.00	98.37	97.89	99.30

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 15 failures.
  - 3.rom_ctrl_stress_all_with_rand_reset.92549486806963298740769466190491765874996059820375807095167930284719936441395
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1c17eb47-1f4b-4b6b-9c4e-c42c392f469d
```
  - 4.rom_ctrl_stress_all_with_rand_reset.50283225328058723029624131875461872853963406822236294436998054397752631634386
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:d6649749-e669-406d-979e-9235ece61973
```
  - ... and 13 more failures.
UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 13.rom_ctrl_stress_all_with_rand_reset.87713719438600530523063120216043546362953891590528631014726077577625809862108
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10018929550 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x50725689
  UVM_INFO @ 10018929550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.rom_ctrl_stress_all_with_rand_reset.94565865882056459561982911599115699044396335486612270098376619022245907633758
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/47.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10024058195 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x5dfc970b
  UVM_INFO @ 10024058195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 16.rom_ctrl_passthru_mem_tl_intg_err.97885297920898354378818064559872925272410904296799333220331095646590367003396
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/16.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 10007349022 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x5de9000c
  UVM_INFO @ 10007349022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: 0c759b93ab

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0c759b93ab`