ROM_CTRL/32KB Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	1.212m	7.389ms	49	50	98.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	35.360s	13.763ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	33.150s	12.303ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	27.100s	12.360ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	26.040s	31.991ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	33.300s	8.520ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	33.150s	12.303ms	20	20	100.00
		rom_ctrl_csr_aliasing	26.040s	31.991ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	18.890s	7.205ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	27.140s	3.162ms	5	5	100.00
V1		TOTAL			114	115	99.13
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	34.350s	63.104ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	3.157m	37.057ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	1.135m	55.754ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	34.680s	7.149ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	37.320s	20.443ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	37.320s	20.443ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	35.360s	13.763ms	5	5	100.00
		rom_ctrl_csr_rw	33.150s	12.303ms	20	20	100.00
		rom_ctrl_csr_aliasing	26.040s	31.991ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.600s	8.892ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	35.360s	13.763ms	5	5	100.00
		rom_ctrl_csr_rw	33.150s	12.303ms	20	20	100.00
		rom_ctrl_csr_aliasing	26.040s	31.991ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	33.600s	8.892ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	18.495m	239.887ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	3.409m	32.197ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.243m	15.604ms	5	5	100.00
		rom_ctrl_tl_intg_err	2.946m	4.108ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.243m	15.604ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.495m	239.887ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.495m	239.887ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	18.495m	239.887ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.495m	239.887ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.495m	239.887ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.243m	15.604ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.243m	15.604ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	1.212m	7.389ms	49	50	98.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	1.212m	7.389ms	49	50	98.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	1.212m	7.389ms	49	50	98.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.946m	4.108ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	18.495m	239.887ms	50	50	100.00
		rom_ctrl_kmac_err_chk	1.135m	55.754ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	18.495m	239.887ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	18.495m	239.887ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	18.495m	239.887ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	3.409m	32.197ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.243m	15.604ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.469h	92.260ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			461	500	92.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.68	96.96	93.11	97.88	100.00	98.68	98.04	99.07

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 26 failures.

    • 1.rom_ctrl_stress_all_with_rand_reset.42029234917899521768674268285185327625792863467975370912078989149736881044654
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 161889257 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 161889257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.rom_ctrl_stress_all_with_rand_reset.8288003478570906697855429520378901920441096913783718883776455525522985759657
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3659655692 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3659655692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 7 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 7 failures.

    • 4.rom_ctrl_stress_all_with_rand_reset.46173351740615816575009880651520321185419874014561643979869276836214099028411
      Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10684448590 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xfdb7c96d
        UVM_INFO @ 10684448590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.rom_ctrl_stress_all_with_rand_reset.338540270930812394511847338274522615951030009406926024007236844065748371014
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10006429328 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x5d2e1ff1
        UVM_INFO @ 10006429328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 5 failures.

    • 2.rom_ctrl_stress_all_with_rand_reset.86586028493316470759931805423648014592290803477140922593932031919870326522554
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:d509f2aa-9db5-4fc5-b915-e7a4ceb16a87
      

    • 12.rom_ctrl_stress_all_with_rand_reset.59822901947368763368542530811968045534868033822993272548408212624982350709237
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:e26ed46d-b9f4-4cb3-9490-a557641bfb52
      

    • ... and 3 more failures.

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
  • Test rom_ctrl_smoke has 1 failures.

    • 5.rom_ctrl_smoke.94951936580855218316617924197455070233609535520531185752320032402254751313394
      Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_smoke/latest/run.log

        UVM_FATAL @ 40010429300 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x93e34f94
        UVM_INFO @ 40010429300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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