70ad420931| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 49.380s | 4.450ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 17.300s | 4.257ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 16.930s | 4.501ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 13.350s | 3.172ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 16.100s | 10.981ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 16.780s | 7.572ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 16.930s | 4.501ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 16.100s | 10.981ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 15.070s | 1.971ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 15.810s | 8.848ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 17.680s | 7.607ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 2.079m | 98.884ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 34.740s | 35.493ms | 49 | 50 | 98.00 |
| V2 | alert_test | rom_ctrl_alert_test | 16.790s | 2.248ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 18.460s | 13.444ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 18.460s | 13.444ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 17.300s | 4.257ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 16.930s | 4.501ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 16.100s | 10.981ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 16.940s | 1.910ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 17.300s | 4.257ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 16.930s | 4.501ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 16.100s | 10.981ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 16.940s | 1.910ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 239 | 240 | 99.58 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 9.044m | 221.851ms | 50 | 50 | 100.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 1.544m | 46.255ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.766m | 6.913ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 1.337m | 2.159ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.766m | 6.913ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.044m | 221.851ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.044m | 221.851ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 9.044m | 221.851ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.044m | 221.851ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.044m | 221.851ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.766m | 6.913ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.766m | 6.913ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 49.380s | 4.450ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 49.380s | 4.450ms | 50 | 50 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 49.380s | 4.450ms | 50 | 50 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.337m | 2.159ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 9.044m | 221.851ms | 50 | 50 | 100.00 |
| rom_ctrl_kmac_err_chk | 34.740s | 35.493ms | 49 | 50 | 98.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 9.044m | 221.851ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.044m | 221.851ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 9.044m | 221.851ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 1.544m | 46.255ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.766m | 6.913ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 95 | 95 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.451h | 105.021ms | 13 | 50 | 26.00 |
| V3 | TOTAL | 13 | 50 | 26.00 | |||
| TOTAL | 462 | 500 | 92.40 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 5 | 83.33 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.74 | 96.96 | 93.25 | 97.88 | 100.00 | 99.01 | 98.04 | 99.07 |
UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
0.rom_ctrl_stress_all_with_rand_reset.96889975183257681185365672296446070567750445645217950278985394673667168378148
Line 312, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4626489206 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4626489206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_stress_all_with_rand_reset.85878240772386193318588430401349501803828611697413975142949713432108407335387
Line 326, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5579677729 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5579677729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
2.rom_ctrl_stress_all_with_rand_reset.26448448232980267270103244521239562568782478270421320500047982627525086822064
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:2dbaa02b-8d50-4571-a969-67d672ad0c25
5.rom_ctrl_stress_all_with_rand_reset.30710032571514584958108207953750759180919198583653359567938858060014511688422
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:173b26f0-842b-444d-8983-b9595baf62a4
... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
19.rom_ctrl_stress_all_with_rand_reset.68421472747942962385083232386563157407905710663121471810935025272940656864636
Line 298, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/19.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 50184457706 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x5ec21f35
UVM_INFO @ 50184457706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
47.rom_ctrl_kmac_err_chk.12463586845699181243632098709081096839155627557731436662660452482460433480121
Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/47.rom_ctrl_kmac_err_chk/latest/run.log
UVM_ERROR @ 3322055282 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 3322055282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---