b111fbcef3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 44.070s | 3.717ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | rom_ctrl_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 50 | 115 | 43.48 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 18.690s | 8.530ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 2.018m | 56.278ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 35.730s | 17.672ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 16.300s | 2.067ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 200 | 240 | 83.33 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 9.208m | 55.272ms | 50 | 50 | 100.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.711m | 327.475us | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.711m | 327.475us | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.208m | 55.272ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.208m | 55.272ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 9.208m | 55.272ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.208m | 55.272ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.208m | 55.272ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.711m | 327.475us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.711m | 327.475us | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 44.070s | 3.717ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 44.070s | 3.717ms | 50 | 50 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 44.070s | 3.717ms | 50 | 50 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 9.208m | 55.272ms | 50 | 50 | 100.00 |
| rom_ctrl_kmac_err_chk | 35.730s | 17.672ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 9.208m | 55.272ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.208m | 55.272ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 9.208m | 55.272ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.711m | 327.475us | 5 | 5 | 100.00 |
| V2S | TOTAL | 55 | 95 | 57.89 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.403h | 248.254ms | 18 | 50 | 36.00 |
| V3 | TOTAL | 18 | 50 | 36.00 | |||
| TOTAL | 323 | 500 | 64.60 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 1 | 12.50 |
| V2 | 6 | 6 | 4 | 66.67 |
| V2S | 4 | 4 | 2 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 145 failures:
0.rom_ctrl_passthru_mem_tl_intg_err.84489938427913905216078262815020604952899207748058714925456865882075682043641
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
1.rom_ctrl_passthru_mem_tl_intg_err.17092357074536941051160113730014365923551928338785246398426430159083550252018
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
... and 18 more failures.
0.rom_ctrl_tl_errors.11418558171688175738979527017835496943279971496576167940426986341591307475016
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_tl_errors/latest/run.log
1.rom_ctrl_tl_errors.12166954557722192516028641045452516696305732698350153750492546919529049188247
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_tl_errors/latest/run.log
... and 18 more failures.
0.rom_ctrl_tl_intg_err.114104206208301279383923394848668689065558098383243956197756779402360491328965
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_tl_intg_err/latest/run.log
1.rom_ctrl_tl_intg_err.115704724731138792675554384166611330892981655436358576851992218552927425980748
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_tl_intg_err/latest/run.log
... and 18 more failures.
0.rom_ctrl_mem_walk.56967570977715693221546792690599517943339569552297268603212032423012715117337
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_mem_walk/latest/run.log
1.rom_ctrl_mem_walk.106056426389848108503278567202448976236925982727411089152428486137700727271608
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_mem_walk/latest/run.log
... and 3 more failures.
0.rom_ctrl_mem_partial_access.6004317282874700278419758620981869758819592265125607085917318480497619264673
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_mem_partial_access/latest/run.log
1.rom_ctrl_mem_partial_access.28062288259404083495262994121413011098836698130616798992613215885209400521975
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_mem_partial_access/latest/run.log
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
2.rom_ctrl_stress_all_with_rand_reset.17842489018444959469532915869046478653711050924802355115696266343194668693165
Line 316, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30609121922 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 30609121922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rom_ctrl_stress_all_with_rand_reset.49899180935856660307981166266976011598117092085837118189967461441772840783515
Line 443, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 39731183987 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 39731183987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
11.rom_ctrl_stress_all_with_rand_reset.4956324986799945877210212355478394136835277442914472981418980769050074915183
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:0aa60250-a497-4fe2-b0c8-0ae3829c6c69
22.rom_ctrl_stress_all_with_rand_reset.109089524329614857589530906141816107669607370659035726695159082015998749505451
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:505a83e8-caf9-401f-845a-cd9bdf117070
... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 4 failures:
10.rom_ctrl_stress_all_with_rand_reset.69358653367870117469651515583633964062097398733671006469060969771052929193839
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10020977673 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x63fff847
UVM_INFO @ 10020977673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.rom_ctrl_stress_all_with_rand_reset.43081570462946241896028369819613628011297506412724740798903669202690726342037
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/28.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10006637881 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xc5d47019
UVM_INFO @ 10006637881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
tar (child): /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/cover_reg_top/output.tar.gz: Cannot open: No such file or directory tar (child): Error is not recoverable: exiting now tar: Child returned status * tar: Error is not recoverable: exiting now has 1 failures:
Job rom_ctrl-sim-vcs_cov_report killed due to: Exit reason: Job lost from admin server: generic::not_found: generic::not_found: job is not found has 1 failures:
cov_report
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/cov_report/cov_report.log
Job ID: smart:94f826dc-a999-483e-823a-9c80c55b6032