ROM_CTRL/32KB Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: 70ad420931

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	43.230s	8.265ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.110s	4.591ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.340s	6.938ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.110s	8.496ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.000s	9.353ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.150s	16.001ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.340s	6.938ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.000s	9.353ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	17.250s	4.304ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.120s	3.922ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.710s	4.499ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.024m	14.942ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	36.060s	8.668ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.030s	2.125ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.830s	2.096ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.830s	2.096ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.110s	4.591ms	5	5	100.00
		rom_ctrl_csr_rw	14.340s	6.938ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.000s	9.353ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.680s	37.713ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.110s	4.591ms	5	5	100.00
		rom_ctrl_csr_rw	14.340s	6.938ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.000s	9.353ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.680s	37.713ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.555m	270.800ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.753m	51.242ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.816m	4.990ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.315m	9.435ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.816m	4.990ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.555m	270.800ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.555m	270.800ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.555m	270.800ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.555m	270.800ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.555m	270.800ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.816m	4.990ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.816m	4.990ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	43.230s	8.265ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	43.230s	8.265ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	43.230s	8.265ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.315m	9.435ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.555m	270.800ms	50	50	100.00
		rom_ctrl_kmac_err_chk	36.060s	8.668ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.555m	270.800ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.555m	270.800ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.555m	270.800ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.753m	51.242ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.816m	4.990ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.987h	150.232ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			460	500	92.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 29 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.79708424798572445604927604518681088952267626649489855322284896751850047128878
      Line 528, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 352467863042 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 352467863042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.rom_ctrl_stress_all_with_rand_reset.19086726091076868154545698334459102271660314675022932219554848252918401252613
      Line 518, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 62819008557 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 62819008557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

• Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 8 failures.

    • 1.rom_ctrl_stress_all_with_rand_reset.59607037437333705462223557502217775711191094213852519560576929144546260976746
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:3108827d-81aa-4db5-810a-97b2a7937f75
      

    • 4.rom_ctrl_stress_all_with_rand_reset.52472352148815803541533703498147379863036126771266305400286328488149252407797
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:887c66cf-92a1-4601-8ce8-8298fad4cc8b
      

    • ... and 6 more failures.

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 3 failures.

    • 11.rom_ctrl_stress_all_with_rand_reset.26474226991621933459139680537824860913102136564252653535001950273064658630555
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10014527852 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xaed4b3d3
        UVM_INFO @ 10014527852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 16.rom_ctrl_stress_all_with_rand_reset.29771636388065691435422193051129480116800301460828202123954266306294485045119
      Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 11569538585 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xe863b64f
        UVM_INFO @ 11569538585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Copying gs://7fa5dc6d-7dd3-3f84-9a7e-4f1238163bf8/EDAFarmArchive/tarballs/*/*/*/*/opentitan1_cluster:smart-3fd1b51e-e952-4e1e-ba55-77a2ac588ff0/output.tar.gz... OSError: No such file or directory. / [* files][ * B/* KiB] has 1 failures:

  • Test rom_ctrl has 1 failures.
    • cov_merge
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/cov_merge/merged.vdb/cov_merge.log

• Job killed most likely because its dependent job failed. has 1 failures:

  • Test rom_ctrl has 1 failures.
    • cov_report
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/cov_report/cov_report.log

Past Results

• Latest
• lint
• 2024.03.22_04.45.06
• 2024.03.22_04.44.12
• 2024.03.20_03.47.58
• 2024.03.20_03.47.10
• 2024.03.18_04.43.49
• 2024.03.18_04.43.05