Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rom_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	368	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7857

1

T2

318

T4

2

T11

227

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2167	1			T2	77		T4	6		T5	4
values[0x0]	2963	1			T2	121		T11	92		T12	108
values[0x1]	3095	1			T2	128		T4	3		T5	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	214	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8011

1

T2

322

T4

5

T5

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21	1			T5	1		T11	1		T71	1
valid_sources[0x01]	18	1			T11	2		T19	3		T26	1
valid_sources[0x02]	22	1			T12	1		T8	10		T19	2
valid_sources[0x03]	31	1			T11	1		T12	2		T23	3
valid_sources[0x04]	46	1			T11	2		T12	1		T19	2
valid_sources[0x05]	16	1			T11	2		T12	2		T19	2
valid_sources[0x06]	11	1			T12	2		T26	1		T38	1
valid_sources[0x07]	22	1			T12	2		T26	1		T39	1
valid_sources[0x08]	30	1			T11	1		T12	1		T19	1
valid_sources[0x09]	22	1			T26	1		T39	2		T72	2
valid_sources[0x0a]	16	1			T12	1		T19	2		T26	1
valid_sources[0x0b]	47	1			T12	3		T24	1		T26	2
valid_sources[0x0c]	23	1			T2	4		T11	1		T73	1
valid_sources[0x0d]	15	1			T11	1		T12	1		T20	1
valid_sources[0x0e]	20	1			T2	4		T11	2		T19	2
valid_sources[0x0f]	16	1			T12	3		T19	1		T71	1
valid_sources[0x10]	25	1			T12	2		T39	3		T71	2
valid_sources[0x11]	18	1			T24	1		T26	1		T39	2
valid_sources[0x12]	17	1			T11	1		T19	1		T26	1
valid_sources[0x13]	35	1			T2	3		T12	3		T19	2
valid_sources[0x14]	15	1			T12	2		T36	3		T74	2
valid_sources[0x15]	31	1			T11	1		T19	3		T24	2
valid_sources[0x16]	28	1			T11	3		T26	1		T39	1
valid_sources[0x17]	18	1			T2	2		T12	1		T24	1
valid_sources[0x18]	41	1			T2	3		T11	1		T12	1
valid_sources[0x19]	21	1			T2	1		T23	2		T75	2
valid_sources[0x1a]	21	1			T2	1		T11	1		T19	2
valid_sources[0x1b]	35	1			T2	7		T11	3		T19	1
valid_sources[0x1c]	17	1			T12	1		T19	1		T39	1
valid_sources[0x1d]	26	1			T5	1		T11	4		T12	4
valid_sources[0x1e]	30	1			T2	1		T11	2		T12	1
valid_sources[0x1f]	42	1			T2	1		T11	2		T12	5
valid_sources[0x20]	21	1			T11	1		T24	2		T39	4
valid_sources[0x21]	33	1			T2	6		T11	1		T12	1
valid_sources[0x22]	19	1			T11	1		T12	1		T19	1
valid_sources[0x23]	33	1			T2	6		T11	1		T12	1
valid_sources[0x24]	32	1			T19	2		T24	1		T71	2
valid_sources[0x25]	23	1			T2	6		T24	1		T26	1
valid_sources[0x26]	30	1			T11	2		T12	1		T19	1
valid_sources[0x27]	22	1			T2	4		T24	1		T26	2
valid_sources[0x28]	20	1			T11	1		T12	2		T39	1
valid_sources[0x29]	34	1			T2	7		T11	1		T12	1
valid_sources[0x2a]	28	1			T2	3		T11	1		T23	1
valid_sources[0x2b]	13	1			T19	1		T73	2		T76	2
valid_sources[0x2c]	31	1			T2	3		T12	1		T26	1
valid_sources[0x2d]	35	1			T2	11		T12	1		T26	1
valid_sources[0x2e]	31	1			T11	3		T24	1		T39	3
valid_sources[0x2f]	17	1			T12	2		T73	7		T77	1
valid_sources[0x30]	84	1			T11	1		T12	1		T22	14
valid_sources[0x31]	26	1			T11	1		T12	1		T19	1
valid_sources[0x32]	36	1			T11	1		T19	2		T39	2
valid_sources[0x33]	43	1			T12	1		T19	2		T39	6
valid_sources[0x34]	36	1			T11	1		T12	1		T19	3
valid_sources[0x35]	23	1			T2	3		T11	1		T19	1
valid_sources[0x36]	19	1			T12	2		T36	5		T26	1
valid_sources[0x37]	30	1			T11	5		T24	1		T26	2
valid_sources[0x38]	15	1			T12	2		T39	1		T72	2
valid_sources[0x39]	22	1			T2	1		T11	2		T12	2
valid_sources[0x3a]	34	1			T11	2		T12	3		T39	2
valid_sources[0x3b]	29	1			T11	1		T12	3		T72	2
valid_sources[0x3c]	37	1			T12	2		T19	1		T10	1
valid_sources[0x3d]	48	1			T11	2		T12	3		T24	1
valid_sources[0x3e]	25	1			T12	1		T26	1		T39	1
valid_sources[0x3f]	36	1			T11	1		T12	1		T19	1
valid_sources[0x40]	14	1			T11	1		T12	1		T19	3
valid_sources[0x41]	21	1			T19	1		T23	1		T73	1
valid_sources[0x42]	33	1			T2	1		T11	2		T12	1
valid_sources[0x43]	30	1			T11	1		T12	2		T19	2
valid_sources[0x44]	21	1			T23	1		T26	1		T39	6
valid_sources[0x45]	17	1			T2	1		T11	1		T12	1
valid_sources[0x46]	42	1			T2	7		T11	2		T12	1
valid_sources[0x47]	30	1			T11	2		T12	3		T19	4
valid_sources[0x48]	27	1			T2	3		T11	1		T12	1
valid_sources[0x49]	24	1			T2	3		T11	2		T12	1
valid_sources[0x4a]	34	1			T11	2		T12	2		T19	1
valid_sources[0x4b]	37	1			T19	2		T39	1		T15	1
valid_sources[0x4c]	31	1			T2	6		T11	1		T26	1
valid_sources[0x4d]	10	1			T11	1		T19	1		T39	1
valid_sources[0x4e]	28	1			T2	1		T11	1		T12	2
valid_sources[0x4f]	25	1			T2	1		T12	1		T39	5
valid_sources[0x50]	30	1			T2	5		T11	2		T12	3
valid_sources[0x51]	25	1			T2	1		T11	3		T12	2
valid_sources[0x52]	12	1			T11	1		T12	1		T19	2
valid_sources[0x53]	32	1			T12	2		T19	1		T39	7
valid_sources[0x54]	36	1			T2	5		T11	3		T12	1
valid_sources[0x55]	39	1			T2	2		T12	1		T19	1
valid_sources[0x56]	46	1			T5	1		T12	3		T23	1
valid_sources[0x57]	23	1			T12	1		T19	1		T26	3
valid_sources[0x58]	25	1			T12	1		T73	6		T78	3
valid_sources[0x59]	11	1			T10	1		T39	1		T72	1
valid_sources[0x5a]	66	1			T2	2		T4	4		T12	1
valid_sources[0x5b]	320	1			T12	1		T24	1		T26	1
valid_sources[0x5c]	21	1			T2	4		T37	2		T26	2
valid_sources[0x5d]	23	1			T2	5		T11	1		T12	3
valid_sources[0x5e]	24	1			T2	1		T11	1		T26	1
valid_sources[0x5f]	18	1			T11	1		T12	1		T26	3
valid_sources[0x60]	41	1			T12	1		T39	1		T71	1
valid_sources[0x61]	25	1			T72	1		T78	5		T76	2
valid_sources[0x62]	25	1			T12	5		T19	2		T24	1
valid_sources[0x63]	24	1			T26	1		T39	2		T71	1
valid_sources[0x64]	35	1			T12	1		T19	1		T24	1
valid_sources[0x65]	25	1			T2	1		T11	1		T19	3
valid_sources[0x66]	24	1			T2	5		T11	2		T19	1
valid_sources[0x67]	19	1			T2	1		T11	3		T12	3
valid_sources[0x68]	30	1			T11	1		T12	3		T19	1
valid_sources[0x69]	21	1			T11	1		T12	1		T72	3
valid_sources[0x6a]	21	1			T11	4		T12	1		T19	1
valid_sources[0x6b]	37	1			T2	2		T11	3		T12	1
valid_sources[0x6c]	32	1			T2	3		T24	1		T39	2
valid_sources[0x6d]	31	1			T2	5		T12	1		T19	2
valid_sources[0x6e]	30	1			T11	1		T12	2		T26	3
valid_sources[0x6f]	62	1			T2	2		T12	1		T20	1
valid_sources[0x70]	31	1			T11	2		T12	2		T79	7
valid_sources[0x71]	11	1			T12	1		T24	1		T71	2
valid_sources[0x72]	32	1			T11	1		T19	4		T80	4
valid_sources[0x73]	46	1			T2	4		T12	1		T39	6
valid_sources[0x74]	25	1			T2	3		T11	3		T12	2
valid_sources[0x75]	21	1			T11	1		T12	2		T19	1
valid_sources[0x76]	43	1			T2	5		T11	3		T12	4
valid_sources[0x77]	23	1			T2	3		T11	1		T12	2
valid_sources[0x78]	11	1			T11	1		T37	1		T71	1
valid_sources[0x79]	32	1			T12	1		T33	1		T76	4
valid_sources[0x7a]	41	1			T11	1		T24	1		T72	1
valid_sources[0x7b]	16	1			T11	1		T12	1		T26	1
valid_sources[0x7c]	17	1			T2	1		T12	2		T19	1
valid_sources[0x7d]	20	1			T2	6		T11	1		T12	1
valid_sources[0x7e]	24	1			T12	1		T19	2		T39	2
valid_sources[0x7f]	14	1			T11	1		T80	1		T72	1
valid_sources[0x80]	30	1			T19	2		T39	2		T71	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2063

1

T2

77

T4

1

T11

47

values[0x0]

all_enables

biggest_size

2904

1

T2

120

T11

91

T12

105

values[0x1]

all_enables

biggest_size

2890

1

T2

121

T4

1

T11

89

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4695	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

18633

1

T1

34

T2

182

T3

213

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5885	1			T1	6		T2	47		T3	30
values[0x0]	8418	1			T1	21		T2	73		T3	78
values[0x1]	9025	1			T1	15		T2	93		T3	105

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3246	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

20082

1

T1

34

T2

201

T3

213

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	76	1			T3	1		T5	1		T27	14
valid_sources[0x01]	66	1			T2	1		T5	1		T27	5
valid_sources[0x02]	61	1			T4	4		T5	1		T11	7
valid_sources[0x03]	71	1			T2	1		T4	3		T27	4
valid_sources[0x04]	162	1			T5	1		T28	1		T29	1
valid_sources[0x05]	51	1			T2	1		T3	2		T5	1
valid_sources[0x06]	83	1			T2	1		T14	2		T19	2
valid_sources[0x07]	124	1			T2	2		T3	3		T4	3
valid_sources[0x08]	120	1			T2	2		T3	7		T4	1
valid_sources[0x09]	84	1			T2	1		T4	3		T11	3
valid_sources[0x0a]	77	1			T2	2		T27	2		T28	1
valid_sources[0x0b]	230	1			T3	2		T14	1		T4	2
valid_sources[0x0c]	127	1			T27	2		T28	2		T44	1
valid_sources[0x0d]	82	1			T3	2		T5	1		T12	2
valid_sources[0x0e]	63	1			T2	2		T3	9		T12	2
valid_sources[0x0f]	112	1			T2	1		T3	5		T11	5
valid_sources[0x10]	132	1			T2	1		T5	1		T17	3
valid_sources[0x11]	62	1			T2	2		T12	1		T27	1
valid_sources[0x12]	81	1			T2	4		T3	1		T4	1
valid_sources[0x13]	80	1			T2	1		T4	2		T5	2
valid_sources[0x14]	110	1			T2	1		T4	3		T5	1
valid_sources[0x15]	115	1			T2	1		T14	1		T4	2
valid_sources[0x16]	93	1			T2	1		T4	1		T27	1
valid_sources[0x17]	118	1			T2	1		T5	3		T28	1
valid_sources[0x18]	81	1			T5	1		T12	1		T27	1
valid_sources[0x19]	74	1			T2	1		T3	1		T27	1
valid_sources[0x1a]	50	1			T3	2		T4	1		T5	5
valid_sources[0x1b]	64	1			T2	1		T12	1		T27	2
valid_sources[0x1c]	157	1			T27	3		T30	1		T20	5
valid_sources[0x1d]	95	1			T5	2		T12	1		T27	1
valid_sources[0x1e]	121	1			T2	1		T4	1		T5	2
valid_sources[0x1f]	59	1			T2	1		T3	1		T5	4
valid_sources[0x20]	102	1			T3	4		T4	4		T5	2
valid_sources[0x21]	101	1			T2	1		T4	5		T5	3
valid_sources[0x22]	53	1			T5	6		T27	1		T20	4
valid_sources[0x23]	45	1			T3	1		T27	2		T28	2
valid_sources[0x24]	66	1			T2	1		T5	2		T11	1
valid_sources[0x25]	95	1			T11	11		T17	2		T12	4
valid_sources[0x26]	77	1			T2	2		T5	1		T6	1
valid_sources[0x27]	131	1			T4	3		T5	1		T27	2
valid_sources[0x28]	100	1			T3	1		T12	1		T19	1
valid_sources[0x29]	73	1			T2	2		T17	3		T6	1
valid_sources[0x2a]	73	1			T2	2		T18	5		T19	3
valid_sources[0x2b]	69	1			T2	2		T4	2		T17	1
valid_sources[0x2c]	102	1			T3	1		T4	1		T19	1
valid_sources[0x2d]	117	1			T2	1		T3	3		T11	10
valid_sources[0x2e]	87	1			T11	5		T27	1		T20	9
valid_sources[0x2f]	144	1			T3	1		T5	1		T11	4
valid_sources[0x30]	166	1			T3	1		T27	2		T19	2
valid_sources[0x31]	57	1			T2	2		T5	2		T17	1
valid_sources[0x32]	68	1			T1	10		T14	2		T4	1
valid_sources[0x33]	115	1			T2	4		T5	6		T28	1
valid_sources[0x34]	43	1			T3	1		T27	1		T42	1
valid_sources[0x35]	62	1			T2	1		T3	1		T6	2
valid_sources[0x36]	95	1			T5	1		T6	1		T27	2
valid_sources[0x37]	51	1			T2	2		T3	1		T12	2
valid_sources[0x38]	149	1			T2	1		T4	7		T12	1
valid_sources[0x39]	103	1			T14	2		T4	1		T11	8
valid_sources[0x3a]	99	1			T19	2		T50	1		T25	5
valid_sources[0x3b]	75	1			T17	1		T13	11		T28	1
valid_sources[0x3c]	70	1			T3	1		T4	1		T27	1
valid_sources[0x3d]	116	1			T2	3		T17	3		T27	10
valid_sources[0x3e]	65	1			T3	1		T12	2		T27	1
valid_sources[0x3f]	78	1			T14	1		T11	1		T6	1
valid_sources[0x40]	92	1			T3	1		T27	5		T28	1
valid_sources[0x41]	138	1			T2	1		T4	2		T12	1
valid_sources[0x42]	87	1			T2	1		T4	5		T5	4
valid_sources[0x43]	114	1			T2	1		T12	1		T28	1
valid_sources[0x44]	80	1			T4	6		T12	1		T27	2
valid_sources[0x45]	69	1			T2	1		T5	1		T17	2
valid_sources[0x46]	105	1			T2	1		T3	1		T5	9
valid_sources[0x47]	70	1			T2	2		T27	1		T28	1
valid_sources[0x48]	101	1			T3	3		T5	2		T27	1
valid_sources[0x49]	101	1			T2	1		T5	2		T11	2
valid_sources[0x4a]	58	1			T2	1		T12	2		T28	1
valid_sources[0x4b]	84	1			T3	1		T12	1		T28	1
valid_sources[0x4c]	55	1			T2	1		T12	1		T19	2
valid_sources[0x4d]	85	1			T2	1		T3	3		T4	2
valid_sources[0x4e]	88	1			T5	3		T12	3		T27	1
valid_sources[0x4f]	98	1			T2	1		T11	3		T8	21
valid_sources[0x50]	50	1			T11	1		T12	1		T19	3
valid_sources[0x51]	63	1			T2	4		T5	1		T11	12
valid_sources[0x52]	59	1			T2	1		T5	1		T11	1
valid_sources[0x53]	84	1			T4	3		T5	3		T27	2
valid_sources[0x54]	81	1			T2	3		T4	6		T27	4
valid_sources[0x55]	69	1			T2	5		T6	1		T12	2
valid_sources[0x56]	68	1			T2	3		T3	4		T12	8
valid_sources[0x57]	109	1			T2	3		T14	1		T27	4
valid_sources[0x58]	102	1			T2	2		T3	1		T4	1
valid_sources[0x59]	84	1			T2	1		T5	3		T12	2
valid_sources[0x5a]	55	1			T2	1		T3	2		T4	1
valid_sources[0x5b]	56	1			T2	1		T4	1		T27	8
valid_sources[0x5c]	140	1			T5	2		T6	1		T19	1
valid_sources[0x5d]	115	1			T2	3		T3	5		T5	2
valid_sources[0x5e]	88	1			T2	1		T5	1		T20	1
valid_sources[0x5f]	113	1			T1	3		T2	1		T4	3
valid_sources[0x60]	86	1			T17	1		T28	2		T22	9
valid_sources[0x61]	60	1			T2	3		T27	4		T20	1
valid_sources[0x62]	72	1			T4	1		T5	5		T17	3
valid_sources[0x63]	69	1			T2	1		T5	2		T12	1
valid_sources[0x64]	57	1			T5	1		T12	2		T29	1
valid_sources[0x65]	118	1			T2	2		T14	2		T4	1
valid_sources[0x66]	75	1			T2	1		T14	4		T12	2
valid_sources[0x67]	136	1			T2	1		T4	1		T27	4
valid_sources[0x68]	75	1			T2	1		T3	5		T17	4
valid_sources[0x69]	64	1			T2	1		T3	1		T6	3
valid_sources[0x6a]	109	1			T2	1		T27	1		T30	1
valid_sources[0x6b]	116	1			T2	1		T3	3		T4	1
valid_sources[0x6c]	171	1			T27	5		T29	1		T19	2
valid_sources[0x6d]	68	1			T2	2		T4	1		T5	1
valid_sources[0x6e]	113	1			T3	2		T4	1		T5	3
valid_sources[0x6f]	49	1			T3	2		T5	1		T30	1
valid_sources[0x70]	154	1			T5	2		T11	20		T28	1
valid_sources[0x71]	106	1			T4	3		T12	2		T27	1
valid_sources[0x72]	89	1			T2	1		T3	1		T4	3
valid_sources[0x73]	69	1			T5	2		T27	5		T19	3
valid_sources[0x74]	118	1			T2	1		T5	1		T6	1
valid_sources[0x75]	103	1			T3	3		T4	1		T5	2
valid_sources[0x76]	81	1			T2	1		T12	6		T27	2
valid_sources[0x77]	46	1			T28	1		T24	1		T44	1
valid_sources[0x78]	80	1			T2	1		T12	1		T27	5
valid_sources[0x79]	141	1			T2	1		T14	1		T5	1
valid_sources[0x7a]	101	1			T2	1		T4	1		T5	2
valid_sources[0x7b]	90	1			T2	1		T3	1		T5	4
valid_sources[0x7c]	79	1			T2	1		T11	5		T17	3
valid_sources[0x7d]	72	1			T2	1		T3	3		T4	3
valid_sources[0x7e]	107	1			T2	2		T27	1		T18	7
valid_sources[0x7f]	76	1			T3	1		T14	3		T17	2
valid_sources[0x80]	92	1			T2	1		T5	1		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3031

1

T2

46

T3

30

T4

6

values[0x0]

all_enables

biggest_size

7796

1

T1

20

T2

72

T3

78

values[0x1]

all_enables

biggest_size

7806

1

T1

14

T2

64

T3

105