Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15516

1

T2

568

T4

7

T5

10

full_word

9286

1

T2

352

T4

3

T11

249

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	24512	1			T2	920		T11	586		T12	1456
auto[TlIntgErrCmd]	94	1			T4	3		T5	2		T13	2
auto[TlIntgErrData]	90	1			T4	6		T5	5		T13	4
auto[TlIntgErrBoth]	106	1			T4	1		T5	3		T13	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3694

1

T2

104

T4

6

T5

6

auto[1]

21108

1

T2

816

T4

4

T5

4

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1314	1			T2	23		T11	17		T12	95
auto[TlIntgErrNone]	partial	auto[1]	13938	1			T2	545		T11	320		T12	964
auto[TlIntgErrNone]	full_word	auto[0]	2246	1			T2	81		T11	47		T12	81
auto[TlIntgErrNone]	full_word	auto[1]	7014	1			T2	271		T11	202		T12	316
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T4	1		T5	2		T13	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T13	1		T18	4		T20	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T4	1		T23	1		T69	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T4	1		T23	1		T62	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T4	4		T5	4		T13	1
auto[TlIntgErrData]	partial	auto[1]	39	1			T4	1		T5	1		T18	3
auto[TlIntgErrData]	full_word	auto[0]	9	1			T13	3		T37	1		T66	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T4	1		T23	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T20	4		T23	6		T36	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T4	1		T5	3		T13	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T36	1		T63	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T13	2		T64	2		T70	1