Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 0.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 gen_cmd_intg_check.u_cmd_intg_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_chk 100.00 100.00



Module Instance : tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_chk 100.00 100.00

Line Coverage for Module : tlul_data_integ_dec
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1

Line Coverage for Instance : tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN25100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 0 1

Line Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_data_integ_dec.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%