Module Definition
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Module Instance : tb.dut.u_mux.u_sel_bus_q_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sel_bus_q_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_mux.u_sel_bus_qq_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sel_bus_qq_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_state_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_done_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_state_flop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_flop
Line No.TotalCoveredPercent
TOTAL300.00
ALWAYS18300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 0 1
19 0 1
21 0 1


Branch Coverage for Module : prim_generic_flop
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 18 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_mux.u_sel_bus_q_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL300.00
ALWAYS18300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 0 1
19 0 1
21 0 1


Branch Coverage for Instance : tb.dut.u_mux.u_sel_bus_q_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 18 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_mux.u_sel_bus_qq_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL300.00
ALWAYS18300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 0 1
19 0 1
21 0 1


Branch Coverage for Instance : tb.dut.u_mux.u_sel_bus_qq_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 18 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL300.00
ALWAYS18300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 0 1
19 0 1
21 0 1


Branch Coverage for Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 18 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_done_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL300.00
ALWAYS18300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 0 1
19 0 1
21 0 1


Branch Coverage for Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_compare.u_done_sender.gen_flops.u_prim_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 18 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL300.00
ALWAYS18300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 0 1
19 0 1
21 0 1


Branch Coverage for Instance : tb.dut.gen_fsm_scramble_enabled.u_checker_fsm.u_state_regs.u_state_flop.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 18 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

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