Unified Coverage Report :: Module :: prim_generic_rom

Module : prim_generic_rom

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.gen_generic.u_impl_generic	0.00	0.00				0.00

---

Module Instance : tb.dut.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_rom

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
CONT_ASSIGN	22	1	0	0.00
ALWAYS	27	2	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv' or '../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	0	1
27	0	1
28	0	1
			==> MISSING_ELSE

---

Branch Coverage for Module : prim_generic_rom

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	27	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv' or '../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	27	if (req_i)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered