1f410ef5dc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | rom_ctrl_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 115 | 0.00 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 0 | 50 | 0.00 | ||
| V2 | stress_all | rom_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 0 | 50 | 0.00 | ||
| V2 | alert_test | rom_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 240 | 0.00 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | tl_intg_err | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| rom_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| rom_ctrl_kmac_err_chk | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 95 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 500 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 0 | 0.00 |
| V2 | 6 | 6 | 0 | 0.00 |
| V2S | 4 | 4 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
User terminated with CTRL-C has 500 failures:
0.rom_ctrl_smoke.6473836741792262173301959710972613812850698850157361717528614073539860513765
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_smoke/latest/run.log
1.rom_ctrl_smoke.19062428458558704225448594530533362749113180681354949405183671647868596927550
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_smoke/latest/run.log
... and 48 more failures.
0.rom_ctrl_stress_all.15405341512894888654634073290644162311041632790233174250604608062654315894550
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all/latest/run.log
1.rom_ctrl_stress_all.82173768158596741151098263024933871409923539795974805268782342021987725874473
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all/latest/run.log
... and 48 more failures.
0.rom_ctrl_max_throughput_chk.21833041106065859151538800349374951333880058809269690812745441458630723308037
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_max_throughput_chk/latest/run.log
1.rom_ctrl_max_throughput_chk.101468666649473694505748564766483348372385200344112573679126871993339508585055
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_max_throughput_chk/latest/run.log
... and 48 more failures.
0.rom_ctrl_corrupt_sig_fatal_chk.112389435278253912369600800696924772524085348021708894576368471315680590724323
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
1.rom_ctrl_corrupt_sig_fatal_chk.43314830390569590537937636777273480350706485160726191556826559542210542686541
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
... and 48 more failures.
0.rom_ctrl_kmac_err_chk.60042839460610922690956252586303961262490417888381098656155078922777479439379
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_kmac_err_chk/latest/run.log
1.rom_ctrl_kmac_err_chk.87649233708457953950718558966526345500858265413518117405197030868438403546687
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_kmac_err_chk/latest/run.log
... and 48 more failures.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/cov_report/cov_report.log