ROM_CTRL/32KB Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	39.810s	3.691ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.660s	2.188ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.490s	3.996ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.420s	3.937ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.830s	2.148ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.420s	23.911ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.490s	3.996ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.830s	2.148ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.010s	522.794us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.650s	8.036ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.780s	2.148ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.384m	45.592ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.410s	4.372ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.020s	5.721ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.900s	8.116ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.900s	8.116ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.660s	2.188ms	5	5	100.00
		rom_ctrl_csr_rw	15.490s	3.996ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.830s	2.148ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.490s	9.323ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.660s	2.188ms	5	5	100.00
		rom_ctrl_csr_rw	15.490s	3.996ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.830s	2.148ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.490s	9.323ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.735m	167.823ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.402m	9.790ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.725m	1.114ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.304m	3.542ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.725m	1.114ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.735m	167.823ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.735m	167.823ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.735m	167.823ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.735m	167.823ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.735m	167.823ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.725m	1.114ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.725m	1.114ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	39.810s	3.691ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	39.810s	3.691ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	39.810s	3.691ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.304m	3.542ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.735m	167.823ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.410s	4.372ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.735m	167.823ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.735m	167.823ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.735m	167.823ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.402m	9.790ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.725m	1.114ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.880h	86.066ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			469	500	93.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	96.97	93.01	97.88	100.00	98.37	98.03	99.07

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 25 failures.

    • 0.rom_ctrl_stress_all_with_rand_reset.22750637729416332311003930542921520179166461598424571507999280953198464767563
      Line 268, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2101675773 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2101675773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.rom_ctrl_stress_all_with_rand_reset.81769884859438652635190354100056951715070964253634524007790852360564427832413
      Line 323, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37548418317 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 37548418317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 5 failures.

    • 1.rom_ctrl_stress_all_with_rand_reset.33471521531520531907484069663863366770523807259558971161958599154473156880599
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:64e40dc8-b356-4736-847a-43781b3226af
      

    • 7.rom_ctrl_stress_all_with_rand_reset.36521879149234622396070754090251487125484118733883254185299912532938239258283
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:9e1564e8-7c60-4c91-8c83-9d89fce2e688
      

    • ... and 3 more failures.

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.rom_ctrl_stress_all_with_rand_reset.14998270093493832493573114014910704841214202976118077027451076234613609413632
      Line 261, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10040385798 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xb8e89fa0
        UVM_INFO @ 10040385798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.04.26_07.56.37
• 2024.04.24_08.07.19
• 2024.04.22_07.31.13