Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rom_ctrl_32kB-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rom_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

627548

1

T2

316

T3

37

T4

81

full_word

397136

1

T2

44

T3

3

T4

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1024394	1			T2	360		T3	40		T4	88
auto[TlIntgErrCmd]	99	1			T66	9		T67	3		T68	2
auto[TlIntgErrData]	95	1			T66	7		T67	4		T68	8
auto[TlIntgErrBoth]	96	1			T66	4		T67	3		T68	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

186003

1

T2

360

T3

40

T4

88

auto[1]

838681

1

T12

746

T13

6674

T14

4043

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	89458	1			T2	316		T3	37		T4	81
auto[TlIntgErrNone]	partial	auto[1]	537828	1			T12	581		T13	3933		T14	2479
auto[TlIntgErrNone]	full_word	auto[0]	96419	1			T2	44		T3	3		T4	7
auto[TlIntgErrNone]	full_word	auto[1]	300689	1			T12	165		T13	2741		T14	1564
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T66	3		T67	3		T68	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T66	5		T68	1		T108	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T66	1		T116	1		T115	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T108	2		T113	1		T117	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T66	4		T67	3		T68	4
auto[TlIntgErrData]	partial	auto[1]	46	1			T66	2		T67	1		T68	4
auto[TlIntgErrData]	full_word	auto[0]	2	1			T66	1		T108	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T113	1		T118	1		T110	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T66	1		T67	2		T68	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T66	2		T67	1		T68	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T68	1		T109	1		T113	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T66	1		T68	1		T108	1