Module Definition
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Module Instance : tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_cmd_intg_check.u_cmd_intg_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_chk 100.00 100.00



Module Instance : tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_data_chk 100.00 100.00

Line Coverage for Module : tlul_data_integ_dec
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2511100.00

24 25 1/1 assign data_err_o = |data_err; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_tl_adapter_rom.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2511100.00

24 25 1/1 assign data_err_o = |data_err; Tests: T2 T3 T4 
Line Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN2511100.00

24 25 1/1 assign data_err_o = |data_err; Tests: T1 T3 T5 
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%