ae68723071| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.565m | 8.668ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 38.620s | 9.721ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 31.230s | 4.252ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 22.790s | 10.724ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 27.060s | 6.530ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 31.240s | 18.287ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 31.230s | 4.252ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 27.060s | 6.530ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 27.520s | 3.628ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 31.100s | 17.061ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 36.660s | 52.040ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 3.470m | 102.252ms | 49 | 50 | 98.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.160m | 33.249ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 34.660s | 19.814ms | 47 | 50 | 94.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 35.920s | 4.204ms | 19 | 20 | 95.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 35.920s | 4.204ms | 19 | 20 | 95.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 38.620s | 9.721ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 31.230s | 4.252ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 27.060s | 6.530ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 32.580s | 13.382ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 38.620s | 9.721ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 31.230s | 4.252ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 27.060s | 6.530ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 32.580s | 13.382ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 235 | 240 | 97.92 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 17.143m | 427.895ms | 48 | 50 | 96.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 3.314m | 114.070ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 4.018m | 13.195ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 2.832m | 9.009ms | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 4.018m | 13.195ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 17.143m | 427.895ms | 48 | 50 | 96.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 17.143m | 427.895ms | 48 | 50 | 96.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 17.143m | 427.895ms | 48 | 50 | 96.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 17.143m | 427.895ms | 48 | 50 | 96.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 17.143m | 427.895ms | 48 | 50 | 96.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 4.018m | 13.195ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 4.018m | 13.195ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.565m | 8.668ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.565m | 8.668ms | 49 | 50 | 98.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.565m | 8.668ms | 49 | 50 | 98.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 2.832m | 9.009ms | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 17.143m | 427.895ms | 48 | 50 | 96.00 |
| rom_ctrl_kmac_err_chk | 1.160m | 33.249ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 17.143m | 427.895ms | 48 | 50 | 96.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 17.143m | 427.895ms | 48 | 50 | 96.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 17.143m | 427.895ms | 48 | 50 | 96.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 3.314m | 114.070ms | 20 | 20 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 4.018m | 13.195ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 93 | 95 | 97.89 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.486h | 30.124ms | 7 | 50 | 14.00 |
| V3 | TOTAL | 7 | 50 | 14.00 | |||
| TOTAL | 449 | 500 | 89.80 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 6 | 6 | 3 | 50.00 |
| V2S | 4 | 4 | 3 | 75.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.50 | 96.97 | 93.01 | 97.88 | 100.00 | 98.37 | 97.88 | 98.37 |
UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
0.rom_ctrl_stress_all_with_rand_reset.77582427770009005918393957158471675166536293567764909960593644096704127823012
Line 273, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5982802784 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5982802784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_ctrl_stress_all_with_rand_reset.47593990901710835872236695802904138894287076879204450256678975348463184873309
Line 291, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24880279447 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 24880279447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
3.rom_ctrl_stress_all_with_rand_reset.87057460526917615194147289540495893876391192350096517263508340618461764835859
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:47a2b71f-fbde-4a1a-876a-e022b6b67f96
5.rom_ctrl_stress_all_with_rand_reset.88291961577721617771936580689316143318622756866174720529541516272094451032406
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:b6505af1-02b4-43f4-b28e-a1806679dd23
... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 7 failures:
7.rom_ctrl_stress_all_with_rand_reset.54761508873275800948816487960780236579782575502366695413468549634771108245297
Line 261, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10163081442 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xcf072fc5
UVM_INFO @ 10163081442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rom_ctrl_stress_all_with_rand_reset.98939577454584151477970247687253071213660866328377776415393660802324275193660
Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10175682234 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x1a80c8c9
UVM_INFO @ 10175682234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Job rom_ctrl_64kB-sim-vcs_run_default killed due to: Exit reason: Submit error: generic::out_of_range: The scheduling requirements for the job cannot be met: CPU: *, RAM: *, disk: *. Please work with the project contact (['opentitan-dev+eda@google.com']) to request machines that can run this job. has 7 failures:
Test rom_ctrl_alert_test has 3 failures.
35.rom_ctrl_alert_test.91399665064023319908687973168846024416192225290392048638256359893031635514001
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/35.rom_ctrl_alert_test/latest/run.log
Job ID: smart:6d9b06bb-c130-4225-902f-91fef9601b86
40.rom_ctrl_alert_test.11526712287203060806955539687238053028447621621752014165879274484439981630277
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/40.rom_ctrl_alert_test/latest/run.log
Job ID: smart:58b5c84c-e7ef-4e19-baae-f298d0969748
... and 1 more failures.
Test rom_ctrl_stress_all has 1 failures.
36.rom_ctrl_stress_all.14795747373052931511643877443041926561585021573350800155921743992832074146764
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/36.rom_ctrl_stress_all/latest/run.log
Job ID: smart:f58f658d-6f6d-4412-913c-e8d2292fa339
Test rom_ctrl_smoke has 1 failures.
39.rom_ctrl_smoke.78592157182139442489410663419272784544023781464033132130793336939887111215568
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_smoke/latest/run.log
Job ID: smart:69dd7cee-51f1-442c-814d-987bd7e280f6
Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
39.rom_ctrl_stress_all_with_rand_reset.61379561766656100185674793677211668979533927642162291366600397583246694329099
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/39.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:b0a82d09-144a-483a-ad89-714a99a2dc89
42.rom_ctrl_stress_all_with_rand_reset.90407210098780456971238701018703066581621102786291746560915230864108325613530
Log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/42.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:15291056-bbda-42df-a6cd-95d45a10e9ad
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 3 failures:
Test rom_ctrl_tl_errors has 1 failures.
7.rom_ctrl_tl_errors.94487960525966803364196803053164324800795995666798052304366094617191996451695
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/7.rom_ctrl_tl_errors/latest/run.log
UVM_ERROR @ 3294655524 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 3294655524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.
11.rom_ctrl_corrupt_sig_fatal_chk.51205580607961777275922531341535022441087000824588350613622988080465317889775
Line 288, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/11.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 65475077137 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 65475077137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.rom_ctrl_corrupt_sig_fatal_chk.40000197586084702672692574125962615819037681478706598993599316163146971780700
Line 289, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_64kB-sim-vcs/29.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
UVM_ERROR @ 48532194893 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
UVM_INFO @ 48532194893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---